188 lines
6.1 KiB
Plaintext
188 lines
6.1 KiB
Plaintext
@c Copyright 2005
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@c Free Software Foundation, Inc.
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@c This is part of the GAS manual.
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@c For copying conditions, see the file as.texinfo.
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@ifset GENERIC
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@page
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@node BFIN-Dependent
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@chapter Blackfin Dependent Features
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@end ifset
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@ifclear GENERIC
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@node Machine Dependencies
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@chapter Blackfin Dependent Features
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@end ifclear
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@cindex Blackfin support
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@menu
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* BFIN Syntax:: BFIN Syntax
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* BFIN Directives:: BFIN Directives
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@end menu
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@node BFIN Syntax
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@section Syntax
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@cindex BFIN syntax
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@cindex syntax, BFIN
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@table @code
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@item Special Characters
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Assembler input is free format and may appear anywhere on the line.
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One instruction may extend across multiple lines or more than one
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instruction may appear on the same line. White space (space, tab,
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comments or newline) may appear anywhere between tokens. A token must
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not have embedded spaces. Tokens include numbers, register names,
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keywords, user identifiers, and also some multicharacter special
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symbols like "+=", "/*" or "||".
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@item Instruction Delimiting
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A semicolon must terminate every instruction. Sometimes a complete
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instruction will consist of more than one operation. There are two
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cases where this occurs. The first is when two general operations
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are combined. Normally a comma separates the different parts, as in
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@smallexample
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a0= r3.h * r2.l, a1 = r3.l * r2.h ;
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@end smallexample
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The second case occurs when a general instruction is combined with one
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or two memory references for joint issue. The latter portions are
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set off by a "||" token.
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@smallexample
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a0 = r3.h * r2.l || r1 = [p3++] || r4 = [i2++];
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@end smallexample
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@item Register Names
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The assembler treats register names and instruction keywords in a case
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insensitive manner. User identifiers are case sensitive. Thus, R3.l,
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R3.L, r3.l and r3.L are all equivalent input to the assembler.
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Register names are reserved and may not be used as program identifiers.
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Some operations (such as "Move Register") require a register pair.
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Register pairs are always data registers and are denoted using a colon,
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eg., R3:2. The larger number must be written firsts. Note that the
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hardware only supports odd-even pairs, eg., R7:6, R5:4, R3:2, and R1:0.
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Some instructions (such as --SP (Push Multiple)) require a group of
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adjacent registers. Adjacent registers are denoted in the syntax by
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the range enclosed in parentheses and separated by a colon, eg., (R7:3).
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Again, the larger number appears first.
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Portions of a particular register may be individually specified. This
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is written with a dot (".") following the register name and then a
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letter denoting the desired portion. For 32-bit registers, ".H"
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denotes the most significant ("High") portion. ".L" denotes the
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least-significant portion. The subdivisions of the 40-bit registers
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are described later.
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@item Accumulators
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The set of 40-bit registers A1 and A0 that normally contain data that
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is being manipulated. Each accumulator can be accessed in four ways.
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@table @code
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@item one 40-bit register
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The register will be referred to as A1 or A0.
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@item one 32-bit register
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The registers are designated as A1.W or A0.W.
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@item two 16-bit registers
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The registers are designated as A1.H, A1.L, A0.H or A0.L.
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@item one 8-bit register
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The registers are designated as A1.X or A0.X for the bits that
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extend beyond bit 31.
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@end table
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@item Data Registers
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The set of 32-bit registers (R0, R1, R2, R3, R4, R5, R6 and R7) that
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normally contain data for manipulation. These are abbreviated as
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D-register or Dreg. Data registers can be accessed as 32-bit registers
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or as two independent 16-bit registers. The least significant 16 bits
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of each register is called the "low" half and is designated with ".L"
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following the register name. The most significant 16 bits are called
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the "high" half and is designated with ".H" following the name.
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@smallexample
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R7.L, r2.h, r4.L, R0.H
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@end smallexample
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@item Pointer Registers
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The set of 32-bit registers (P0, P1, P2, P3, P4, P5, SP and FP) that
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normally contain byte addresses of data structures. These are
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abbreviated as P-register or Preg.
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@smallexample
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p2, p5, fp, sp
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@end smallexample
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@item Stack Pointer SP
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The stack pointer contains the 32-bit address of the last occupied
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byte location in the stack. The stack grows by decrementing the
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stack pointer.
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@item Frame Pointer FP
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The frame pointer contains the 32-bit address of the previous frame
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pointer in the stack. It is located at the top of a frame.
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@item Loop Top
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LT0 and LT1. These registers contain the 32-bit address of the top of
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a zero overhead loop.
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@item Loop Count
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LC0 and LC1. These registers contain the 32-bit counter of the zero
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overhead loop executions.
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@item Loop Bottom
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LB0 and LB1. These registers contain the 32-bit address of the bottom
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of a zero overhead loop.
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@item Index Registers
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The set of 32-bit registers (I0, I1, I2, I3) that normally contain byte
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addresses of data structures. Abbreviated I-register or Ireg.
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@item Modify Registers
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The set of 32-bit registers (M0, M1, M2, M3) that normally contain
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offset values that are added and subracted to one of the index
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registers. Abbreviated as Mreg.
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@item Length Registers
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The set of 32-bit registers (L0, L1, L2, L3) that normally contain the
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length in bytes of the circular buffer. Abbreviated as Lreg. Clear
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the Lreg to disable circular addressing for the corresponding Ireg.
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@item Base Registers
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The set of 32-bit registers (B0, B1, B2, B3) that normally contain the
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base address in bytes of the circular buffer. Abbreviated as Breg.
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@item Floating Point
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The Blackfin family has no hardware floating point but the .float
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directive generates ieee floating point numbers for use with software
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floating point libraries.
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@item Blackfin Opcodes
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For detailed information on the Blackfin machine instruction set, see
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the Blackfin(r) Processor Instruction Set Reference.
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@end table
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@node BFIN Directives
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@section Directives
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@cindex BFIN directives
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@cindex directives, BFIN
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The following directives are provided for compatibility with the VDSP assembler.
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@table @code
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@item .byte2
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Initializes a four byte data object.
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@item .byte4
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Initializes a two byte data object.
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@item .db
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TBD
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@item .dd
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TBD
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@item .dw
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TBD
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@item .var
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Define and initialize a 32 bit data object.
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@end table
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