c0c468d562
BFD's bfd_get_mach () function returns a bfd specific value representing the architecture of the target which is populated from the Tag_CPU_arch build attribute value of that target. Among other users of that interfacem, objdump which uses it to print the architecture version of the binary being examinated and to decide what instruction is available if run with "-m arm" via its own mapping from bfd_mach_arm_X values to feature bits available. However, both BFD and objdump's most recent known architecture is Armv5TE. When encountering a newer architecture bfd_get_mach will return bfd_mach_arm_unknown. This is unfortunate since objdump uses that value to allow all instructions on all architectures which is already what it does by default, making the "-m arm" trick useless. This patch updates BFD and objdump's knowledge of Arm architecture versions up to the latest Armv8-M Baseline and Mainline, Armv8-R and Armv8.4-A architectures. Since several architecture versions (eg. 8.X-A) share the same Tag_CPU_arch build attribute value and bfd_mach_arm values, the mapping from bfd machine value to feature bits need to return the most featureful feature bits that would yield the given bfd machine value otherwise some instruction would not disassemble under "-m arm" mode. The patch rework that mapping to make this clearer and simplify writing the mapping rules. In particular, for simplicity all FPU instructions are allowed in all cases. Finally, the patch also rewrite the cpu_arch_ver table in GAS to use the TAG_CPU_ARCH_X macros rather than hardcode their value. 2018-07-02 Thomas Preud'homme <thomas.preudhomme@arm.com> bfd/ * archures.c (bfd_mach_arm_5TEJ, bfd_mach_arm_6, bfd_mach_arm_6KZ, bfd_mach_arm_6T2, bfd_mach_arm_6K, bfd_mach_arm_7, bfd_mach_arm_6M, bfd_mach_arm_6SM, bfd_mach_arm_7EM, bfd_mach_arm_8, bfd_mach_arm_8R, bfd_mach_arm_8M_BASE, bfd_mach_arm_8M_MAIN): Define. * bfd-in2.h: Regenerate. * cpu-arm.c (arch_info_struct): Add entries for above new bfd_mach_arm values. * elf32-arm.c (bfd_arm_get_mach_from_attributes): Add Tag_CPU_arch to bfd_mach_arm mapping logic for pre Armv4 and Armv5TEJ and later architectures. Force assert failure for any new Tag_CPU_arch value. gas/ * config/tc-arm.c (cpu_arch_ver): Use symbolic TAG_CPU_ARCH macros rather than hardcode their values. ld/ * arm-dis.c (select_arm_features): Fix typo in heading comment. Allow all FPU features and add mapping from new bfd_mach_arm values to allowed CPU feature bits. opcodes/ * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in expected result. * testsuite/ld-arm/tls-descrelax-v7.d: Likewise. * testsuite/ld-arm/tls-longplt-lib.d: Likewise. * testsuite/ld-arm/tls-longplt.d: Likewise.
60 lines
1.5 KiB
Makefile
60 lines
1.5 KiB
Makefile
.*: file format elf32-.*arm
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architecture: armv6t2, flags 0x00000150:
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HAS_SYMS, DYNAMIC, D_PAGED
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start address 0x.*
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Disassembly of section .plt:
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00008170 <.plt>:
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.*: e52de004 push {lr} ; .*
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.*: e59fe004 ldr lr, \[pc, #4\] ; .*
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.*: e08fe00e add lr, pc, lr
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.*: e5bef008 ldr pc, \[lr, #8\]!
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.*: 000080e0 .word 0x000080e0
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.*: e08e0000 add r0, lr, r0
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.*: e5901004 ldr r1, \[r0, #4\]
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.*: e12fff11 bx r1
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.*: e52d2004 push {r2} ; .*
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.*: e59f200c ldr r2, \[pc, #12\] ; .*
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.*: e59f100c ldr r1, \[pc, #12\] ; .*
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.*: e79f2002 ldr r2, \[pc, r2\]
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.*: e081100f add r1, r1, pc
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.*: e12fff12 bx r2
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.*: 000080d8 .word 0x000080d8
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.*: 000080b8 .word 0x000080b8
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Disassembly of section .text:
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000081b0 <text>:
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.*: e59f0004 ldr r0, \[pc, #4\] ; .*
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.*: fafffff2 blx .* <\.plt\+0x14>
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.*: e1a00000 nop ; .*
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.*: 000080b4 .word 0x000080b4
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.*: 4801 ldr r0, \[pc, #4\] ; .*
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.*: f7ff efe0 blx .* <\.plt\+0x14>
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.*: bf00 nop
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.*: 000080a5 .word 0x000080a5
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Disassembly of section .foo:
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04001000 <foo>:
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.*: e59f0004 ldr r0, \[pc, #4\] ; .*
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.*: fa000009 blx 4001030 .*
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.*: e1a00000 nop ; .*
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.*: fc00f264 .word 0xfc00f264
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.*: e59f0004 ldr r0, \[pc, #4\] ; .*
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.*: fa000005 blx 4001030 .*
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.*: e1a00000 nop ; .*
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.*: fc00f25c .word 0xfc00f25c
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.*: 4801 ldr r0, \[pc, #4\] ; .*
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.*: f000 e806 blx 4001030 .*
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.*: bf00 nop
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.*: fc00f245 .word 0xfc00f245
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.*: 00000000 .word 0x00000000
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04001030 <__unnamed_veneer>:
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.*: e59f1000 ldr r1, \[pc\] ; .*
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.*: e08ff001 add pc, pc, r1
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.*: fc007148 .word 0xfc007148
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.*: 00000000 .word 0x00000000
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