914 lines
24 KiB
C
914 lines
24 KiB
C
/* GNU/Linux/MIPS specific low level interface, for the remote server for GDB.
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Copyright (C) 1995-2015 Free Software Foundation, Inc.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#include "server.h"
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#include "linux-low.h"
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#include "nat/gdb_ptrace.h"
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#include <endian.h>
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#include "nat/mips-linux-watch.h"
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#include "gdb_proc_service.h"
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/* Defined in auto-generated file mips-linux.c. */
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void init_registers_mips_linux (void);
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extern const struct target_desc *tdesc_mips_linux;
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/* Defined in auto-generated file mips-dsp-linux.c. */
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void init_registers_mips_dsp_linux (void);
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extern const struct target_desc *tdesc_mips_dsp_linux;
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/* Defined in auto-generated file mips64-linux.c. */
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void init_registers_mips64_linux (void);
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extern const struct target_desc *tdesc_mips64_linux;
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/* Defined in auto-generated file mips64-dsp-linux.c. */
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void init_registers_mips64_dsp_linux (void);
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extern const struct target_desc *tdesc_mips64_dsp_linux;
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#ifdef __mips64
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#define tdesc_mips_linux tdesc_mips64_linux
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#define tdesc_mips_dsp_linux tdesc_mips64_dsp_linux
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#endif
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#ifndef PTRACE_GET_THREAD_AREA
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#define PTRACE_GET_THREAD_AREA 25
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#endif
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#ifdef HAVE_SYS_REG_H
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#include <sys/reg.h>
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#endif
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#define mips_num_regs 73
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#define mips_dsp_num_regs 80
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#include <asm/ptrace.h>
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#ifndef DSP_BASE
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#define DSP_BASE 71
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#define DSP_CONTROL 77
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#endif
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union mips_register
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{
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unsigned char buf[8];
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/* Deliberately signed, for proper sign extension. */
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int reg32;
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long long reg64;
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};
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/* Return the ptrace ``address'' of register REGNO. */
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#define mips_base_regs \
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-1, 1, 2, 3, 4, 5, 6, 7, \
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8, 9, 10, 11, 12, 13, 14, 15, \
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16, 17, 18, 19, 20, 21, 22, 23, \
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24, 25, 26, 27, 28, 29, 30, 31, \
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\
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-1, MMLO, MMHI, BADVADDR, CAUSE, PC, \
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\
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FPR_BASE, FPR_BASE + 1, FPR_BASE + 2, FPR_BASE + 3, \
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FPR_BASE + 4, FPR_BASE + 5, FPR_BASE + 6, FPR_BASE + 7, \
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FPR_BASE + 8, FPR_BASE + 9, FPR_BASE + 10, FPR_BASE + 11, \
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FPR_BASE + 12, FPR_BASE + 13, FPR_BASE + 14, FPR_BASE + 15, \
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FPR_BASE + 16, FPR_BASE + 17, FPR_BASE + 18, FPR_BASE + 19, \
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FPR_BASE + 20, FPR_BASE + 21, FPR_BASE + 22, FPR_BASE + 23, \
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FPR_BASE + 24, FPR_BASE + 25, FPR_BASE + 26, FPR_BASE + 27, \
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FPR_BASE + 28, FPR_BASE + 29, FPR_BASE + 30, FPR_BASE + 31, \
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FPC_CSR, FPC_EIR
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#define mips_dsp_regs \
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DSP_BASE, DSP_BASE + 1, DSP_BASE + 2, DSP_BASE + 3, \
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DSP_BASE + 4, DSP_BASE + 5, \
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DSP_CONTROL
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static int mips_regmap[mips_num_regs] = {
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mips_base_regs,
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0
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};
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static int mips_dsp_regmap[mips_dsp_num_regs] = {
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mips_base_regs,
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mips_dsp_regs,
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0
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};
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/* DSP registers are not in any regset and can only be accessed
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individually. */
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static unsigned char mips_dsp_regset_bitmap[(mips_dsp_num_regs + 7) / 8] = {
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0xfe, 0xff, 0xff, 0xff, 0xfe, 0xff, 0xff, 0xff, 0xff, 0x80
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};
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static int have_dsp = -1;
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/* Try peeking at an arbitrarily chosen DSP register and pick the available
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user register set accordingly. */
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static const struct target_desc *
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mips_read_description (void)
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{
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if (have_dsp < 0)
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{
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int pid = lwpid_of (current_thread);
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errno = 0;
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ptrace (PTRACE_PEEKUSER, pid, DSP_CONTROL, 0);
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switch (errno)
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{
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case 0:
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have_dsp = 1;
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break;
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case EIO:
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have_dsp = 0;
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break;
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default:
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perror_with_name ("ptrace");
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break;
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}
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}
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return have_dsp ? tdesc_mips_dsp_linux : tdesc_mips_linux;
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}
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static void
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mips_arch_setup (void)
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{
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current_process ()->tdesc = mips_read_description ();
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}
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static struct usrregs_info *
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get_usrregs_info (void)
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{
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const struct regs_info *regs_info = the_low_target.regs_info ();
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return regs_info->usrregs;
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}
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/* Per-process arch-specific data we want to keep. */
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struct arch_process_info
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{
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/* -1 if the kernel and/or CPU do not support watch registers.
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1 if watch_readback is valid and we can read style, num_valid
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and the masks.
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0 if we need to read the watch_readback. */
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int watch_readback_valid;
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/* Cached watch register read values. */
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struct pt_watch_regs watch_readback;
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/* Current watchpoint requests for this process. */
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struct mips_watchpoint *current_watches;
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/* The current set of watch register values for writing the
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registers. */
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struct pt_watch_regs watch_mirror;
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};
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/* Per-thread arch-specific data we want to keep. */
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struct arch_lwp_info
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{
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/* Non-zero if our copy differs from what's recorded in the thread. */
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int watch_registers_changed;
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};
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/* From mips-linux-nat.c. */
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/* Pseudo registers can not be read. ptrace does not provide a way to
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read (or set) PS_REGNUM, and there's no point in reading or setting
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ZERO_REGNUM. We also can not set BADVADDR, CAUSE, or FCRIR via
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ptrace(). */
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static int
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mips_cannot_fetch_register (int regno)
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{
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const struct target_desc *tdesc;
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if (get_usrregs_info ()->regmap[regno] == -1)
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return 1;
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tdesc = current_process ()->tdesc;
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if (find_regno (tdesc, "r0") == regno)
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return 1;
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return 0;
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}
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static int
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mips_cannot_store_register (int regno)
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{
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const struct target_desc *tdesc;
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if (get_usrregs_info ()->regmap[regno] == -1)
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return 1;
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tdesc = current_process ()->tdesc;
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if (find_regno (tdesc, "r0") == regno)
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return 1;
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if (find_regno (tdesc, "cause") == regno)
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return 1;
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if (find_regno (tdesc, "badvaddr") == regno)
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return 1;
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if (find_regno (tdesc, "fir") == regno)
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return 1;
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return 0;
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}
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static CORE_ADDR
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mips_get_pc (struct regcache *regcache)
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{
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union mips_register pc;
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collect_register_by_name (regcache, "pc", pc.buf);
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return register_size (regcache->tdesc, 0) == 4 ? pc.reg32 : pc.reg64;
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}
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static void
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mips_set_pc (struct regcache *regcache, CORE_ADDR pc)
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{
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union mips_register newpc;
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if (register_size (regcache->tdesc, 0) == 4)
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newpc.reg32 = pc;
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else
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newpc.reg64 = pc;
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supply_register_by_name (regcache, "pc", newpc.buf);
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}
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/* Correct in either endianness. */
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static const unsigned int mips_breakpoint = 0x0005000d;
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#define mips_breakpoint_len 4
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/* We only place breakpoints in empty marker functions, and thread locking
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is outside of the function. So rather than importing software single-step,
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we can just run until exit. */
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static CORE_ADDR
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mips_reinsert_addr (void)
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{
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struct regcache *regcache = get_thread_regcache (current_thread, 1);
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union mips_register ra;
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collect_register_by_name (regcache, "r31", ra.buf);
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return register_size (regcache->tdesc, 0) == 4 ? ra.reg32 : ra.reg64;
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}
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static int
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mips_breakpoint_at (CORE_ADDR where)
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{
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unsigned int insn;
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(*the_target->read_memory) (where, (unsigned char *) &insn, 4);
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if (insn == mips_breakpoint)
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return 1;
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/* If necessary, recognize more trap instructions here. GDB only uses the
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one. */
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return 0;
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}
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/* Mark the watch registers of lwp, represented by ENTRY, as changed,
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if the lwp's process id is *PID_P. */
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static int
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update_watch_registers_callback (struct inferior_list_entry *entry,
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void *pid_p)
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{
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struct thread_info *thread = (struct thread_info *) entry;
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struct lwp_info *lwp = get_thread_lwp (thread);
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int pid = *(int *) pid_p;
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/* Only update the threads of this process. */
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if (pid_of (thread) == pid)
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{
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/* The actual update is done later just before resuming the lwp,
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we just mark that the registers need updating. */
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lwp->arch_private->watch_registers_changed = 1;
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/* If the lwp isn't stopped, force it to momentarily pause, so
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we can update its watch registers. */
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if (!lwp->stopped)
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linux_stop_lwp (lwp);
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}
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return 0;
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}
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/* This is the implementation of linux_target_ops method
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new_process. */
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static struct arch_process_info *
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mips_linux_new_process (void)
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{
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struct arch_process_info *info = XCNEW (struct arch_process_info);
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return info;
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}
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/* This is the implementation of linux_target_ops method new_thread.
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Mark the watch registers as changed, so the threads' copies will
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be updated. */
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static void
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mips_linux_new_thread (struct lwp_info *lwp)
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{
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struct arch_lwp_info *info = XCNEW (struct arch_lwp_info);
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info->watch_registers_changed = 1;
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lwp->arch_private = info;
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}
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/* Create a new mips_watchpoint and add it to the list. */
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static void
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mips_add_watchpoint (struct arch_process_info *private, CORE_ADDR addr,
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int len, int watch_type)
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{
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struct mips_watchpoint *new_watch;
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struct mips_watchpoint **pw;
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new_watch = XNEW (struct mips_watchpoint);
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new_watch->addr = addr;
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new_watch->len = len;
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new_watch->type = watch_type;
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new_watch->next = NULL;
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pw = &private->current_watches;
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while (*pw != NULL)
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pw = &(*pw)->next;
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*pw = new_watch;
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}
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/* Hook to call when a new fork is attached. */
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static void
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mips_linux_new_fork (struct process_info *parent,
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struct process_info *child)
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{
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struct arch_process_info *parent_private;
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struct arch_process_info *child_private;
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struct mips_watchpoint *wp;
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/* These are allocated by linux_add_process. */
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gdb_assert (parent->priv != NULL
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&& parent->priv->arch_private != NULL);
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gdb_assert (child->priv != NULL
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&& child->priv->arch_private != NULL);
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/* Linux kernel before 2.6.33 commit
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72f674d203cd230426437cdcf7dd6f681dad8b0d
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will inherit hardware debug registers from parent
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on fork/vfork/clone. Newer Linux kernels create such tasks with
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zeroed debug registers.
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GDB core assumes the child inherits the watchpoints/hw
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breakpoints of the parent, and will remove them all from the
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forked off process. Copy the debug registers mirrors into the
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new process so that all breakpoints and watchpoints can be
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removed together. The debug registers mirror will become zeroed
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in the end before detaching the forked off process, thus making
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this compatible with older Linux kernels too. */
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parent_private = parent->priv->arch_private;
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child_private = child->priv->arch_private;
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child_private->watch_readback_valid = parent_private->watch_readback_valid;
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child_private->watch_readback = parent_private->watch_readback;
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for (wp = parent_private->current_watches; wp != NULL; wp = wp->next)
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mips_add_watchpoint (child_private, wp->addr, wp->len, wp->type);
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child_private->watch_mirror = parent_private->watch_mirror;
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}
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/* This is the implementation of linux_target_ops method
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prepare_to_resume. If the watch regs have changed, update the
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thread's copies. */
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static void
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mips_linux_prepare_to_resume (struct lwp_info *lwp)
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{
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ptid_t ptid = ptid_of (get_lwp_thread (lwp));
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struct process_info *proc = find_process_pid (ptid_get_pid (ptid));
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struct arch_process_info *priv = proc->priv->arch_private;
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if (lwp->arch_private->watch_registers_changed)
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{
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/* Only update the watch registers if we have set or unset a
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watchpoint already. */
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if (mips_linux_watch_get_num_valid (&priv->watch_mirror) > 0)
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{
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/* Write the mirrored watch register values. */
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int tid = ptid_get_lwp (ptid);
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if (-1 == ptrace (PTRACE_SET_WATCH_REGS, tid,
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&priv->watch_mirror, NULL))
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perror_with_name ("Couldn't write watch register");
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}
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lwp->arch_private->watch_registers_changed = 0;
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}
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}
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static int
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mips_supports_z_point_type (char z_type)
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{
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switch (z_type)
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{
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case Z_PACKET_WRITE_WP:
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case Z_PACKET_READ_WP:
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case Z_PACKET_ACCESS_WP:
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return 1;
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default:
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return 0;
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}
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}
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/* This is the implementation of linux_target_ops method
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insert_point. */
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static int
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mips_insert_point (enum raw_bkpt_type type, CORE_ADDR addr,
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int len, struct raw_breakpoint *bp)
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{
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struct process_info *proc = current_process ();
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struct arch_process_info *priv = proc->priv->arch_private;
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struct pt_watch_regs regs;
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int pid;
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long lwpid;
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enum target_hw_bp_type watch_type;
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uint32_t irw;
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lwpid = lwpid_of (current_thread);
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if (!mips_linux_read_watch_registers (lwpid,
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&priv->watch_readback,
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&priv->watch_readback_valid,
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0))
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return -1;
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if (len <= 0)
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return -1;
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regs = priv->watch_readback;
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/* Add the current watches. */
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mips_linux_watch_populate_regs (priv->current_watches, ®s);
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/* Now try to add the new watch. */
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watch_type = raw_bkpt_type_to_target_hw_bp_type (type);
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irw = mips_linux_watch_type_to_irw (watch_type);
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if (!mips_linux_watch_try_one_watch (®s, addr, len, irw))
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return -1;
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/* It fit. Stick it on the end of the list. */
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mips_add_watchpoint (priv, addr, len, watch_type);
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priv->watch_mirror = regs;
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/* Only update the threads of this process. */
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pid = pid_of (proc);
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find_inferior (&all_threads, update_watch_registers_callback, &pid);
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return 0;
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}
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/* This is the implementation of linux_target_ops method
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remove_point. */
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static int
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mips_remove_point (enum raw_bkpt_type type, CORE_ADDR addr,
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int len, struct raw_breakpoint *bp)
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{
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struct process_info *proc = current_process ();
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struct arch_process_info *priv = proc->priv->arch_private;
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int deleted_one;
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int pid;
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enum target_hw_bp_type watch_type;
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struct mips_watchpoint **pw;
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struct mips_watchpoint *w;
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/* Search for a known watch that matches. Then unlink and free it. */
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watch_type = raw_bkpt_type_to_target_hw_bp_type (type);
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deleted_one = 0;
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pw = &priv->current_watches;
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while ((w = *pw))
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{
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if (w->addr == addr && w->len == len && w->type == watch_type)
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{
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*pw = w->next;
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free (w);
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|
deleted_one = 1;
|
|
break;
|
|
}
|
|
pw = &(w->next);
|
|
}
|
|
|
|
if (!deleted_one)
|
|
return -1; /* We don't know about it, fail doing nothing. */
|
|
|
|
/* At this point watch_readback is known to be valid because we
|
|
could not have added the watch without reading it. */
|
|
gdb_assert (priv->watch_readback_valid == 1);
|
|
|
|
priv->watch_mirror = priv->watch_readback;
|
|
mips_linux_watch_populate_regs (priv->current_watches,
|
|
&priv->watch_mirror);
|
|
|
|
/* Only update the threads of this process. */
|
|
pid = pid_of (proc);
|
|
find_inferior (&all_threads, update_watch_registers_callback, &pid);
|
|
return 0;
|
|
}
|
|
|
|
/* This is the implementation of linux_target_ops method
|
|
stopped_by_watchpoint. The watchhi R and W bits indicate
|
|
the watch register triggered. */
|
|
|
|
static int
|
|
mips_stopped_by_watchpoint (void)
|
|
{
|
|
struct process_info *proc = current_process ();
|
|
struct arch_process_info *priv = proc->priv->arch_private;
|
|
int n;
|
|
int num_valid;
|
|
long lwpid = lwpid_of (current_thread);
|
|
|
|
if (!mips_linux_read_watch_registers (lwpid,
|
|
&priv->watch_readback,
|
|
&priv->watch_readback_valid,
|
|
1))
|
|
return 0;
|
|
|
|
num_valid = mips_linux_watch_get_num_valid (&priv->watch_readback);
|
|
|
|
for (n = 0; n < MAX_DEBUG_REGISTER && n < num_valid; n++)
|
|
if (mips_linux_watch_get_watchhi (&priv->watch_readback, n)
|
|
& (R_MASK | W_MASK))
|
|
return 1;
|
|
|
|
return 0;
|
|
}
|
|
|
|
/* This is the implementation of linux_target_ops method
|
|
stopped_data_address. */
|
|
|
|
static CORE_ADDR
|
|
mips_stopped_data_address (void)
|
|
{
|
|
struct process_info *proc = current_process ();
|
|
struct arch_process_info *priv = proc->priv->arch_private;
|
|
int n;
|
|
int num_valid;
|
|
long lwpid = lwpid_of (current_thread);
|
|
|
|
/* On MIPS we don't know the low order 3 bits of the data address.
|
|
GDB does not support remote targets that can't report the
|
|
watchpoint address. So, make our best guess; return the starting
|
|
address of a watchpoint request which overlaps the one that
|
|
triggered. */
|
|
|
|
if (!mips_linux_read_watch_registers (lwpid,
|
|
&priv->watch_readback,
|
|
&priv->watch_readback_valid,
|
|
0))
|
|
return 0;
|
|
|
|
num_valid = mips_linux_watch_get_num_valid (&priv->watch_readback);
|
|
|
|
for (n = 0; n < MAX_DEBUG_REGISTER && n < num_valid; n++)
|
|
if (mips_linux_watch_get_watchhi (&priv->watch_readback, n)
|
|
& (R_MASK | W_MASK))
|
|
{
|
|
CORE_ADDR t_low, t_hi;
|
|
int t_irw;
|
|
struct mips_watchpoint *watch;
|
|
|
|
t_low = mips_linux_watch_get_watchlo (&priv->watch_readback, n);
|
|
t_irw = t_low & IRW_MASK;
|
|
t_hi = (mips_linux_watch_get_watchhi (&priv->watch_readback, n)
|
|
| IRW_MASK);
|
|
t_low &= ~(CORE_ADDR)t_hi;
|
|
|
|
for (watch = priv->current_watches;
|
|
watch != NULL;
|
|
watch = watch->next)
|
|
{
|
|
CORE_ADDR addr = watch->addr;
|
|
CORE_ADDR last_byte = addr + watch->len - 1;
|
|
|
|
if ((t_irw & mips_linux_watch_type_to_irw (watch->type)) == 0)
|
|
{
|
|
/* Different type. */
|
|
continue;
|
|
}
|
|
/* Check for overlap of even a single byte. */
|
|
if (last_byte >= t_low && addr <= t_low + t_hi)
|
|
return addr;
|
|
}
|
|
}
|
|
|
|
/* Shouldn't happen. */
|
|
return 0;
|
|
}
|
|
|
|
/* Fetch the thread-local storage pointer for libthread_db. */
|
|
|
|
ps_err_e
|
|
ps_get_thread_area (const struct ps_prochandle *ph,
|
|
lwpid_t lwpid, int idx, void **base)
|
|
{
|
|
if (ptrace (PTRACE_GET_THREAD_AREA, lwpid, NULL, base) != 0)
|
|
return PS_ERR;
|
|
|
|
/* IDX is the bias from the thread pointer to the beginning of the
|
|
thread descriptor. It has to be subtracted due to implementation
|
|
quirks in libthread_db. */
|
|
*base = (void *) ((char *)*base - idx);
|
|
|
|
return PS_OK;
|
|
}
|
|
|
|
#ifdef HAVE_PTRACE_GETREGS
|
|
|
|
static void
|
|
mips_collect_register (struct regcache *regcache,
|
|
int use_64bit, int regno, union mips_register *reg)
|
|
{
|
|
union mips_register tmp_reg;
|
|
|
|
if (use_64bit)
|
|
{
|
|
collect_register (regcache, regno, &tmp_reg.reg64);
|
|
*reg = tmp_reg;
|
|
}
|
|
else
|
|
{
|
|
collect_register (regcache, regno, &tmp_reg.reg32);
|
|
reg->reg64 = tmp_reg.reg32;
|
|
}
|
|
}
|
|
|
|
static void
|
|
mips_supply_register (struct regcache *regcache,
|
|
int use_64bit, int regno, const union mips_register *reg)
|
|
{
|
|
int offset = 0;
|
|
|
|
/* For big-endian 32-bit targets, ignore the high four bytes of each
|
|
eight-byte slot. */
|
|
if (__BYTE_ORDER == __BIG_ENDIAN && !use_64bit)
|
|
offset = 4;
|
|
|
|
supply_register (regcache, regno, reg->buf + offset);
|
|
}
|
|
|
|
static void
|
|
mips_collect_register_32bit (struct regcache *regcache,
|
|
int use_64bit, int regno, unsigned char *buf)
|
|
{
|
|
union mips_register tmp_reg;
|
|
int reg32;
|
|
|
|
mips_collect_register (regcache, use_64bit, regno, &tmp_reg);
|
|
reg32 = tmp_reg.reg64;
|
|
memcpy (buf, ®32, 4);
|
|
}
|
|
|
|
static void
|
|
mips_supply_register_32bit (struct regcache *regcache,
|
|
int use_64bit, int regno, const unsigned char *buf)
|
|
{
|
|
union mips_register tmp_reg;
|
|
int reg32;
|
|
|
|
memcpy (®32, buf, 4);
|
|
tmp_reg.reg64 = reg32;
|
|
mips_supply_register (regcache, use_64bit, regno, &tmp_reg);
|
|
}
|
|
|
|
static void
|
|
mips_fill_gregset (struct regcache *regcache, void *buf)
|
|
{
|
|
union mips_register *regset = buf;
|
|
int i, use_64bit;
|
|
const struct target_desc *tdesc = regcache->tdesc;
|
|
|
|
use_64bit = (register_size (tdesc, 0) == 8);
|
|
|
|
for (i = 1; i < 32; i++)
|
|
mips_collect_register (regcache, use_64bit, i, regset + i);
|
|
|
|
mips_collect_register (regcache, use_64bit,
|
|
find_regno (tdesc, "lo"), regset + 32);
|
|
mips_collect_register (regcache, use_64bit,
|
|
find_regno (tdesc, "hi"), regset + 33);
|
|
mips_collect_register (regcache, use_64bit,
|
|
find_regno (tdesc, "pc"), regset + 34);
|
|
mips_collect_register (regcache, use_64bit,
|
|
find_regno (tdesc, "badvaddr"), regset + 35);
|
|
mips_collect_register (regcache, use_64bit,
|
|
find_regno (tdesc, "status"), regset + 36);
|
|
mips_collect_register (regcache, use_64bit,
|
|
find_regno (tdesc, "cause"), regset + 37);
|
|
|
|
mips_collect_register (regcache, use_64bit,
|
|
find_regno (tdesc, "restart"), regset + 0);
|
|
}
|
|
|
|
static void
|
|
mips_store_gregset (struct regcache *regcache, const void *buf)
|
|
{
|
|
const union mips_register *regset = buf;
|
|
int i, use_64bit;
|
|
|
|
use_64bit = (register_size (regcache->tdesc, 0) == 8);
|
|
|
|
for (i = 0; i < 32; i++)
|
|
mips_supply_register (regcache, use_64bit, i, regset + i);
|
|
|
|
mips_supply_register (regcache, use_64bit,
|
|
find_regno (regcache->tdesc, "lo"), regset + 32);
|
|
mips_supply_register (regcache, use_64bit,
|
|
find_regno (regcache->tdesc, "hi"), regset + 33);
|
|
mips_supply_register (regcache, use_64bit,
|
|
find_regno (regcache->tdesc, "pc"), regset + 34);
|
|
mips_supply_register (regcache, use_64bit,
|
|
find_regno (regcache->tdesc, "badvaddr"), regset + 35);
|
|
mips_supply_register (regcache, use_64bit,
|
|
find_regno (regcache->tdesc, "status"), regset + 36);
|
|
mips_supply_register (regcache, use_64bit,
|
|
find_regno (regcache->tdesc, "cause"), regset + 37);
|
|
|
|
mips_supply_register (regcache, use_64bit,
|
|
find_regno (regcache->tdesc, "restart"), regset + 0);
|
|
}
|
|
|
|
static void
|
|
mips_fill_fpregset (struct regcache *regcache, void *buf)
|
|
{
|
|
union mips_register *regset = buf;
|
|
int i, use_64bit, first_fp, big_endian;
|
|
|
|
use_64bit = (register_size (regcache->tdesc, 0) == 8);
|
|
first_fp = find_regno (regcache->tdesc, "f0");
|
|
big_endian = (__BYTE_ORDER == __BIG_ENDIAN);
|
|
|
|
/* See GDB for a discussion of this peculiar layout. */
|
|
for (i = 0; i < 32; i++)
|
|
if (use_64bit)
|
|
collect_register (regcache, first_fp + i, regset[i].buf);
|
|
else
|
|
collect_register (regcache, first_fp + i,
|
|
regset[i & ~1].buf + 4 * (big_endian != (i & 1)));
|
|
|
|
mips_collect_register_32bit (regcache, use_64bit,
|
|
find_regno (regcache->tdesc, "fcsr"), regset[32].buf);
|
|
mips_collect_register_32bit (regcache, use_64bit,
|
|
find_regno (regcache->tdesc, "fir"),
|
|
regset[32].buf + 4);
|
|
}
|
|
|
|
static void
|
|
mips_store_fpregset (struct regcache *regcache, const void *buf)
|
|
{
|
|
const union mips_register *regset = buf;
|
|
int i, use_64bit, first_fp, big_endian;
|
|
|
|
use_64bit = (register_size (regcache->tdesc, 0) == 8);
|
|
first_fp = find_regno (regcache->tdesc, "f0");
|
|
big_endian = (__BYTE_ORDER == __BIG_ENDIAN);
|
|
|
|
/* See GDB for a discussion of this peculiar layout. */
|
|
for (i = 0; i < 32; i++)
|
|
if (use_64bit)
|
|
supply_register (regcache, first_fp + i, regset[i].buf);
|
|
else
|
|
supply_register (regcache, first_fp + i,
|
|
regset[i & ~1].buf + 4 * (big_endian != (i & 1)));
|
|
|
|
mips_supply_register_32bit (regcache, use_64bit,
|
|
find_regno (regcache->tdesc, "fcsr"),
|
|
regset[32].buf);
|
|
mips_supply_register_32bit (regcache, use_64bit,
|
|
find_regno (regcache->tdesc, "fir"),
|
|
regset[32].buf + 4);
|
|
}
|
|
#endif /* HAVE_PTRACE_GETREGS */
|
|
|
|
static struct regset_info mips_regsets[] = {
|
|
#ifdef HAVE_PTRACE_GETREGS
|
|
{ PTRACE_GETREGS, PTRACE_SETREGS, 0, 38 * 8, GENERAL_REGS,
|
|
mips_fill_gregset, mips_store_gregset },
|
|
{ PTRACE_GETFPREGS, PTRACE_SETFPREGS, 0, 33 * 8, FP_REGS,
|
|
mips_fill_fpregset, mips_store_fpregset },
|
|
#endif /* HAVE_PTRACE_GETREGS */
|
|
{ 0, 0, 0, -1, -1, NULL, NULL }
|
|
};
|
|
|
|
static struct regsets_info mips_regsets_info =
|
|
{
|
|
mips_regsets, /* regsets */
|
|
0, /* num_regsets */
|
|
NULL, /* disabled_regsets */
|
|
};
|
|
|
|
static struct usrregs_info mips_dsp_usrregs_info =
|
|
{
|
|
mips_dsp_num_regs,
|
|
mips_dsp_regmap,
|
|
};
|
|
|
|
static struct usrregs_info mips_usrregs_info =
|
|
{
|
|
mips_num_regs,
|
|
mips_regmap,
|
|
};
|
|
|
|
static struct regs_info dsp_regs_info =
|
|
{
|
|
mips_dsp_regset_bitmap,
|
|
&mips_dsp_usrregs_info,
|
|
&mips_regsets_info
|
|
};
|
|
|
|
static struct regs_info regs_info =
|
|
{
|
|
NULL, /* regset_bitmap */
|
|
&mips_usrregs_info,
|
|
&mips_regsets_info
|
|
};
|
|
|
|
static const struct regs_info *
|
|
mips_regs_info (void)
|
|
{
|
|
if (have_dsp)
|
|
return &dsp_regs_info;
|
|
else
|
|
return ®s_info;
|
|
}
|
|
|
|
struct linux_target_ops the_low_target = {
|
|
mips_arch_setup,
|
|
mips_regs_info,
|
|
mips_cannot_fetch_register,
|
|
mips_cannot_store_register,
|
|
NULL, /* fetch_register */
|
|
mips_get_pc,
|
|
mips_set_pc,
|
|
(const unsigned char *) &mips_breakpoint,
|
|
mips_breakpoint_len,
|
|
mips_reinsert_addr,
|
|
0,
|
|
mips_breakpoint_at,
|
|
mips_supports_z_point_type,
|
|
mips_insert_point,
|
|
mips_remove_point,
|
|
mips_stopped_by_watchpoint,
|
|
mips_stopped_data_address,
|
|
NULL,
|
|
NULL,
|
|
NULL, /* siginfo_fixup */
|
|
mips_linux_new_process,
|
|
mips_linux_new_thread,
|
|
mips_linux_new_fork,
|
|
mips_linux_prepare_to_resume
|
|
};
|
|
|
|
void
|
|
initialize_low_arch (void)
|
|
{
|
|
/* Initialize the Linux target descriptions. */
|
|
init_registers_mips_linux ();
|
|
init_registers_mips_dsp_linux ();
|
|
init_registers_mips64_linux ();
|
|
init_registers_mips64_dsp_linux ();
|
|
|
|
initialize_regsets_info (&mips_regsets_info);
|
|
}
|