4df7aeb3c5
* simops.c (syscall): Use callback->write regardless of
what file descriptor we're writing too.
984 lines
17 KiB
C
984 lines
17 KiB
C
#include <signal.h>
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#include "sysdep.h"
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#include "bfd.h"
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#include "mn10300_sim.h"
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#ifndef INLINE
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#ifdef __GNUC__
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#define INLINE inline
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#else
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#define INLINE
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#endif
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#endif
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host_callback *mn10300_callback;
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int mn10300_debug;
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static SIM_OPEN_KIND sim_kind;
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static char *myname;
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static void dispatch PARAMS ((uint32, uint32, int));
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static long hash PARAMS ((long));
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static void init_system PARAMS ((void));
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#define MAX_HASH 127
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struct hash_entry
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{
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struct hash_entry *next;
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long opcode;
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long mask;
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struct simops *ops;
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#ifdef HASH_STAT
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unsigned long count;
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#endif
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};
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static int max_mem = 0;
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struct hash_entry hash_table[MAX_HASH+1];
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/* This probably doesn't do a very good job at bucket filling, but
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it's simple... */
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static INLINE long
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hash(insn)
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long insn;
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{
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/* These are one byte insns, we special case these since, in theory,
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they should be the most heavily used. */
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if ((insn & 0xffffff00) == 0)
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{
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switch (insn & 0xf0)
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{
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case 0x00:
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return 0x70;
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case 0x40:
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return 0x71;
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case 0x10:
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return 0x72;
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case 0x30:
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return 0x73;
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case 0x50:
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return 0x74;
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case 0x60:
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return 0x75;
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case 0x70:
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return 0x76;
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case 0x80:
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return 0x77;
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case 0x90:
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return 0x78;
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case 0xa0:
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return 0x79;
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case 0xb0:
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return 0x7a;
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case 0xe0:
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return 0x7b;
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default:
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return 0x7c;
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}
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}
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/* These are two byte insns */
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if ((insn & 0xffff0000) == 0)
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{
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if ((insn & 0xf000) == 0x2000
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|| (insn & 0xf000) == 0x5000)
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return ((insn & 0xfc00) >> 8) & 0x7f;
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if ((insn & 0xf000) == 0x4000)
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return ((insn & 0xf300) >> 8) & 0x7f;
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if ((insn & 0xf000) == 0x8000
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|| (insn & 0xf000) == 0x9000
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|| (insn & 0xf000) == 0xa000
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|| (insn & 0xf000) == 0xb000)
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return ((insn & 0xf000) >> 8) & 0x7f;
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if ((insn & 0xff00) == 0xf000
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|| (insn & 0xff00) == 0xf100
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|| (insn & 0xff00) == 0xf200
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|| (insn & 0xff00) == 0xf500
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|| (insn & 0xff00) == 0xf600)
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return ((insn & 0xfff0) >> 4) & 0x7f;
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if ((insn & 0xf000) == 0xc000)
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return ((insn & 0xff00) >> 8) & 0x7f;
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return ((insn & 0xffc0) >> 6) & 0x7f;
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}
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/* These are three byte insns. */
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if ((insn & 0xff000000) == 0)
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{
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if ((insn & 0xf00000) == 0x000000)
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return ((insn & 0xf30000) >> 16) & 0x7f;
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if ((insn & 0xf00000) == 0x200000
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|| (insn & 0xf00000) == 0x300000)
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return ((insn & 0xfc0000) >> 16) & 0x7f;
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if ((insn & 0xff0000) == 0xf80000)
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return ((insn & 0xfff000) >> 12) & 0x7f;
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if ((insn & 0xff0000) == 0xf90000)
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return ((insn & 0xfffc00) >> 10) & 0x7f;
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return ((insn & 0xff0000) >> 16) & 0x7f;
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}
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/* These are four byte or larger insns. */
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if ((insn & 0xf0000000) == 0xf0000000)
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return ((insn & 0xfff00000) >> 20) & 0x7f;
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return ((insn & 0xff000000) >> 24) & 0x7f;
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}
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static INLINE void
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dispatch (insn, extension, length)
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uint32 insn;
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uint32 extension;
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int length;
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{
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struct hash_entry *h;
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h = &hash_table[hash(insn)];
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while ((insn & h->mask) != h->opcode
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|| (length != h->ops->length))
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{
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if (!h->next)
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{
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(*mn10300_callback->printf_filtered) (mn10300_callback,
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"ERROR looking up hash for 0x%x, PC=0x%x\n", insn, PC);
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exit(1);
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}
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h = h->next;
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}
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#ifdef HASH_STAT
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h->count++;
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#endif
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/* Now call the right function. */
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(h->ops->func)(insn, extension);
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PC += length;
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}
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/* FIXME These would more efficient to use than load_mem/store_mem,
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but need to be changed to use the memory map. */
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uint8
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get_byte (x)
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uint8 *x;
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{
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return *x;
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}
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uint16
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get_half (x)
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uint8 *x;
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{
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uint8 *a = x;
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return (a[1] << 8) + (a[0]);
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}
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uint32
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get_word (x)
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uint8 *x;
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{
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uint8 *a = x;
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return (a[3]<<24) + (a[2]<<16) + (a[1]<<8) + (a[0]);
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}
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void
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put_byte (addr, data)
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uint8 *addr;
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uint8 data;
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{
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uint8 *a = addr;
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a[0] = data;
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}
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void
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put_half (addr, data)
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uint8 *addr;
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uint16 data;
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{
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uint8 *a = addr;
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a[0] = data & 0xff;
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a[1] = (data >> 8) & 0xff;
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}
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void
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put_word (addr, data)
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uint8 *addr;
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uint32 data;
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{
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uint8 *a = addr;
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a[0] = data & 0xff;
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a[1] = (data >> 8) & 0xff;
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a[2] = (data >> 16) & 0xff;
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a[3] = (data >> 24) & 0xff;
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}
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uint32
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load_mem (addr, len)
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SIM_ADDR addr;
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int len;
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{
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uint8 *p = addr + State.mem;
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if (addr > max_mem)
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abort ();
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switch (len)
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{
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case 1:
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return p[0];
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case 2:
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return p[1] << 8 | p[0];
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case 3:
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return p[2] << 16 | p[1] << 8 | p[0];
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case 4:
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return p[3] << 24 | p[2] << 16 | p[1] << 8 | p[0];
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default:
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abort ();
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}
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}
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void
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store_mem (addr, len, data)
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SIM_ADDR addr;
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int len;
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uint32 data;
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{
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uint8 *p = addr + State.mem;
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if (addr > max_mem)
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abort ();
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switch (len)
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{
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case 1:
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p[0] = data;
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return;
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case 2:
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p[0] = data;
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p[1] = data >> 8;
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return;
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case 4:
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p[0] = data;
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p[1] = data >> 8;
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p[2] = data >> 16;
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p[3] = data >> 24;
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return;
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default:
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abort ();
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}
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}
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void
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sim_size (power)
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int power;
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{
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if (State.mem)
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free (State.mem);
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max_mem = 1 << power;
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State.mem = (uint8 *) calloc (1, 1 << power);
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if (!State.mem)
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{
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(*mn10300_callback->printf_filtered) (mn10300_callback, "Allocation of main memory failed.\n");
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exit (1);
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}
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}
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static void
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init_system ()
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{
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if (!State.mem)
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sim_size(19);
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}
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int
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sim_write (sd, addr, buffer, size)
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SIM_DESC sd;
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SIM_ADDR addr;
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unsigned char *buffer;
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int size;
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{
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int i;
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init_system ();
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for (i = 0; i < size; i++)
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store_mem (addr + i, 1, buffer[i]);
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return size;
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}
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/* Compare two opcode table entries for qsort. */
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static int
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compare_simops (arg1, arg2)
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const PTR arg1;
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const PTR arg2;
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{
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unsigned long code1 = ((struct simops *)arg1)->opcode;
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unsigned long code2 = ((struct simops *)arg2)->opcode;
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if (code1 < code2)
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return -1;
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if (code2 < code1)
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return 1;
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return 0;
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}
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SIM_DESC
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sim_open (kind,argv)
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SIM_OPEN_KIND kind;
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char **argv;
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{
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struct simops *s;
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struct hash_entry *h;
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char **p;
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int i;
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/* Sort the opcode array from smallest opcode to largest.
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This will generally improve simulator performance as the smaller
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opcodes are generally preferred to the larger opcodes. */
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for (i = 0, s = Simops; s->func; s++, i++)
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;
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qsort (Simops, i, sizeof (Simops[0]), compare_simops);
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sim_kind = kind;
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myname = argv[0];
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for (p = argv + 1; *p; ++p)
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{
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if (strcmp (*p, "-E") == 0)
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++p; /* ignore endian spec */
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else
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#ifdef DEBUG
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if (strcmp (*p, "-t") == 0)
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mn10300_debug = DEBUG;
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else
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#endif
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(*mn10300_callback->printf_filtered) (mn10300_callback, "ERROR: unsupported option(s): %s\n",*p);
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}
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/* put all the opcodes in the hash table */
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for (s = Simops; s->func; s++)
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{
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h = &hash_table[hash(s->opcode)];
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/* go to the last entry in the chain */
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while (h->next)
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{
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/* Don't insert the same opcode more than once. */
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if (h->opcode == s->opcode
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&& h->mask == s->mask
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&& h->ops == s)
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continue;
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else
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h = h->next;
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}
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/* Don't insert the same opcode more than once. */
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if (h->opcode == s->opcode
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&& h->mask == s->mask
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&& h->ops == s)
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continue;
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if (h->ops)
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{
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h->next = calloc(1,sizeof(struct hash_entry));
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h = h->next;
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}
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h->ops = s;
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h->mask = s->mask;
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h->opcode = s->opcode;
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#if HASH_STAT
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h->count = 0;
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#endif
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}
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/* fudge our descriptor for now */
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return (SIM_DESC) 1;
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}
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void
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sim_close (sd, quitting)
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SIM_DESC sd;
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int quitting;
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{
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/* nothing to do */
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}
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void
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sim_set_profile (n)
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int n;
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{
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(*mn10300_callback->printf_filtered) (mn10300_callback, "sim_set_profile %d\n", n);
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}
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void
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sim_set_profile_size (n)
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int n;
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{
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(*mn10300_callback->printf_filtered) (mn10300_callback, "sim_set_profile_size %d\n", n);
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}
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int
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sim_stop (sd)
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SIM_DESC sd;
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{
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return 0;
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}
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void
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sim_resume (sd, step, siggnal)
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SIM_DESC sd;
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int step, siggnal;
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{
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uint32 inst;
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reg_t oldpc;
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struct hash_entry *h;
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if (step)
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State.exception = SIGTRAP;
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else
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State.exception = 0;
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do
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{
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unsigned long insn, extension;
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/* Fetch the current instruction. */
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inst = load_mem_big (PC, 2);
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oldpc = PC;
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/* Using a giant case statement may seem like a waste because of the
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code/rodata size the table itself will consume. However, using
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a giant case statement speeds up the simulator by 10-15% by avoiding
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cascading if/else statements or cascading case statements. */
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switch ((inst >> 8) & 0xff)
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{
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/* All the single byte insns except 0x80, 0x90, 0xa0, 0xb0
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which must be handled specially. */
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case 0x00:
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case 0x04:
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case 0x08:
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case 0x0c:
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case 0x11:
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case 0x12:
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case 0x13:
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case 0x14:
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case 0x15:
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case 0x16:
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case 0x17:
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case 0x18:
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case 0x19:
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case 0x1a:
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case 0x1b:
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case 0x1c:
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case 0x1d:
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case 0x1e:
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case 0x1f:
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case 0x3c:
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case 0x3d:
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case 0x3e:
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case 0x3f:
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case 0x40:
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case 0x41:
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case 0x44:
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case 0x45:
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case 0x48:
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case 0x49:
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case 0x4c:
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case 0x4d:
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case 0x50:
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case 0x51:
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case 0x52:
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case 0x53:
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case 0x54:
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case 0x55:
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case 0x56:
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case 0x57:
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case 0x60:
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case 0x61:
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case 0x62:
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case 0x63:
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case 0x64:
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case 0x65:
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case 0x66:
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case 0x67:
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case 0x68:
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case 0x69:
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case 0x6a:
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case 0x6b:
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case 0x6c:
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case 0x6d:
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case 0x6e:
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case 0x6f:
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case 0x70:
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case 0x71:
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case 0x72:
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case 0x73:
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case 0x74:
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case 0x75:
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case 0x76:
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case 0x77:
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case 0x78:
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case 0x79:
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case 0x7a:
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case 0x7b:
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case 0x7c:
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case 0x7d:
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case 0x7e:
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case 0x7f:
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case 0xcb:
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case 0xd0:
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case 0xd1:
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case 0xd2:
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case 0xd3:
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case 0xd4:
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case 0xd5:
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case 0xd6:
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case 0xd7:
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case 0xd8:
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case 0xd9:
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case 0xda:
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case 0xdb:
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case 0xe0:
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case 0xe1:
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case 0xe2:
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case 0xe3:
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case 0xe4:
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case 0xe5:
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case 0xe6:
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case 0xe7:
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case 0xe8:
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case 0xe9:
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case 0xea:
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case 0xeb:
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case 0xec:
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case 0xed:
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case 0xee:
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case 0xef:
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case 0xff:
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insn = (inst >> 8) & 0xff;
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extension = 0;
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dispatch (insn, extension, 1);
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break;
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/* Special cases where dm == dn is used to encode a different
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instruction. */
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case 0x80:
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case 0x85:
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case 0x8a:
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case 0x8f:
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case 0x90:
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case 0x95:
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case 0x9a:
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case 0x9f:
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case 0xa0:
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case 0xa5:
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case 0xaa:
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case 0xaf:
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case 0xb0:
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case 0xb5:
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case 0xba:
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case 0xbf:
|
|
insn = inst;
|
|
extension = 0;
|
|
dispatch (insn, extension, 2);
|
|
break;
|
|
|
|
case 0x81:
|
|
case 0x82:
|
|
case 0x83:
|
|
case 0x84:
|
|
case 0x86:
|
|
case 0x87:
|
|
case 0x88:
|
|
case 0x89:
|
|
case 0x8b:
|
|
case 0x8c:
|
|
case 0x8d:
|
|
case 0x8e:
|
|
case 0x91:
|
|
case 0x92:
|
|
case 0x93:
|
|
case 0x94:
|
|
case 0x96:
|
|
case 0x97:
|
|
case 0x98:
|
|
case 0x99:
|
|
case 0x9b:
|
|
case 0x9c:
|
|
case 0x9d:
|
|
case 0x9e:
|
|
case 0xa1:
|
|
case 0xa2:
|
|
case 0xa3:
|
|
case 0xa4:
|
|
case 0xa6:
|
|
case 0xa7:
|
|
case 0xa8:
|
|
case 0xa9:
|
|
case 0xab:
|
|
case 0xac:
|
|
case 0xad:
|
|
case 0xae:
|
|
case 0xb1:
|
|
case 0xb2:
|
|
case 0xb3:
|
|
case 0xb4:
|
|
case 0xb6:
|
|
case 0xb7:
|
|
case 0xb8:
|
|
case 0xb9:
|
|
case 0xbb:
|
|
case 0xbc:
|
|
case 0xbd:
|
|
case 0xbe:
|
|
insn = (inst >> 8) & 0xff;
|
|
extension = 0;
|
|
dispatch (insn, extension, 1);
|
|
break;
|
|
|
|
/* The two byte instructions. */
|
|
case 0x20:
|
|
case 0x21:
|
|
case 0x22:
|
|
case 0x23:
|
|
case 0x28:
|
|
case 0x29:
|
|
case 0x2a:
|
|
case 0x2b:
|
|
case 0x42:
|
|
case 0x43:
|
|
case 0x46:
|
|
case 0x47:
|
|
case 0x4a:
|
|
case 0x4b:
|
|
case 0x4e:
|
|
case 0x4f:
|
|
case 0x58:
|
|
case 0x59:
|
|
case 0x5a:
|
|
case 0x5b:
|
|
case 0x5c:
|
|
case 0x5d:
|
|
case 0x5e:
|
|
case 0x5f:
|
|
case 0xc0:
|
|
case 0xc1:
|
|
case 0xc2:
|
|
case 0xc3:
|
|
case 0xc4:
|
|
case 0xc5:
|
|
case 0xc6:
|
|
case 0xc7:
|
|
case 0xc8:
|
|
case 0xc9:
|
|
case 0xca:
|
|
case 0xce:
|
|
case 0xcf:
|
|
case 0xf0:
|
|
case 0xf1:
|
|
case 0xf2:
|
|
case 0xf3:
|
|
case 0xf4:
|
|
case 0xf5:
|
|
case 0xf6:
|
|
insn = inst;
|
|
extension = 0;
|
|
dispatch (insn, extension, 2);
|
|
break;
|
|
|
|
/* The three byte insns with a 16bit operand in little endian
|
|
format. */
|
|
case 0x01:
|
|
case 0x02:
|
|
case 0x03:
|
|
case 0x05:
|
|
case 0x06:
|
|
case 0x07:
|
|
case 0x09:
|
|
case 0x0a:
|
|
case 0x0b:
|
|
case 0x0d:
|
|
case 0x0e:
|
|
case 0x0f:
|
|
case 0x24:
|
|
case 0x25:
|
|
case 0x26:
|
|
case 0x27:
|
|
case 0x2c:
|
|
case 0x2d:
|
|
case 0x2e:
|
|
case 0x2f:
|
|
case 0x30:
|
|
case 0x31:
|
|
case 0x32:
|
|
case 0x33:
|
|
case 0x34:
|
|
case 0x35:
|
|
case 0x36:
|
|
case 0x37:
|
|
case 0x38:
|
|
case 0x39:
|
|
case 0x3a:
|
|
case 0x3b:
|
|
case 0xcc:
|
|
insn = load_mem (PC, 1);
|
|
insn <<= 16;
|
|
insn |= load_mem (PC + 1, 2);
|
|
extension = 0;
|
|
dispatch (insn, extension, 3);
|
|
break;
|
|
|
|
/* The three byte insns without 16bit operand. */
|
|
case 0xde:
|
|
case 0xdf:
|
|
case 0xf8:
|
|
case 0xf9:
|
|
insn = load_mem_big (PC, 3);
|
|
extension = 0;
|
|
dispatch (insn, extension, 3);
|
|
break;
|
|
|
|
/* Four byte insns. */
|
|
case 0xfa:
|
|
case 0xfb:
|
|
if ((inst & 0xfffc) == 0xfaf0
|
|
|| (inst & 0xfffc) == 0xfaf4
|
|
|| (inst & 0xfffc) == 0xfaf8)
|
|
insn = load_mem_big (PC, 4);
|
|
else
|
|
{
|
|
insn = inst;
|
|
insn <<= 16;
|
|
insn |= load_mem (PC + 2, 2);
|
|
extension = 0;
|
|
}
|
|
dispatch (insn, extension, 4);
|
|
break;
|
|
|
|
/* Five byte insns. */
|
|
case 0xcd:
|
|
insn = load_mem (PC, 1);
|
|
insn <<= 24;
|
|
insn |= (load_mem (PC + 1, 2) << 8);
|
|
insn |= load_mem (PC + 3, 1);
|
|
extension = load_mem (PC + 4, 1);
|
|
dispatch (insn, extension, 5);
|
|
break;
|
|
|
|
case 0xdc:
|
|
insn = load_mem (PC, 1);
|
|
insn <<= 24;
|
|
extension = load_mem (PC + 1, 4);
|
|
insn |= (extension & 0xffffff00) >> 8;
|
|
extension &= 0xff;
|
|
dispatch (insn, extension, 5);
|
|
break;
|
|
|
|
/* Six byte insns. */
|
|
case 0xfc:
|
|
case 0xfd:
|
|
insn = (inst << 16);
|
|
extension = load_mem (PC + 2, 4);
|
|
insn |= ((extension & 0xffff0000) >> 16);
|
|
extension &= 0xffff;
|
|
dispatch (insn, extension, 6);
|
|
break;
|
|
|
|
case 0xdd:
|
|
insn = load_mem (PC, 1) << 24;
|
|
extension = load_mem (PC + 1, 4);
|
|
insn |= ((extension >> 8) & 0xffffff);
|
|
extension = (extension & 0xff) << 16;
|
|
extension |= load_mem (PC + 5, 1) << 8;
|
|
extension |= load_mem (PC + 6, 1);
|
|
dispatch (insn, extension, 7);
|
|
break;
|
|
|
|
case 0xfe:
|
|
insn = inst << 16;
|
|
extension = load_mem (PC + 2, 4);
|
|
insn |= ((extension >> 16) & 0xffff);
|
|
extension <<= 8;
|
|
extension &= 0xffff00;
|
|
extension |= load_mem (PC + 6, 1);
|
|
dispatch (insn, extension, 7);
|
|
break;
|
|
|
|
default:
|
|
abort ();
|
|
}
|
|
}
|
|
while (!State.exception);
|
|
|
|
#ifdef HASH_STAT
|
|
{
|
|
int i;
|
|
for (i = 0; i < MAX_HASH; i++)
|
|
{
|
|
struct hash_entry *h;
|
|
h = &hash_table[i];
|
|
|
|
printf("hash 0x%x:\n", i);
|
|
|
|
while (h)
|
|
{
|
|
printf("h->opcode = 0x%x, count = 0x%x\n", h->opcode, h->count);
|
|
h = h->next;
|
|
}
|
|
|
|
printf("\n\n");
|
|
}
|
|
fflush (stdout);
|
|
}
|
|
#endif
|
|
|
|
}
|
|
|
|
int
|
|
sim_trace (sd)
|
|
SIM_DESC sd;
|
|
{
|
|
#ifdef DEBUG
|
|
mn10300_debug = DEBUG;
|
|
#endif
|
|
sim_resume (sd, 0, 0);
|
|
return 1;
|
|
}
|
|
|
|
void
|
|
sim_info (sd, verbose)
|
|
SIM_DESC sd;
|
|
int verbose;
|
|
{
|
|
(*mn10300_callback->printf_filtered) (mn10300_callback, "sim_info\n");
|
|
}
|
|
|
|
SIM_RC
|
|
sim_create_inferior (sd, argv, env)
|
|
SIM_DESC sd;
|
|
char **argv;
|
|
char **env;
|
|
{
|
|
return SIM_RC_OK;
|
|
}
|
|
|
|
void
|
|
sim_kill (sd)
|
|
SIM_DESC sd;
|
|
{
|
|
/* nothing to do */
|
|
}
|
|
|
|
void
|
|
sim_set_callbacks (sd, p)
|
|
SIM_DESC sd;
|
|
host_callback *p;
|
|
{
|
|
mn10300_callback = p;
|
|
}
|
|
|
|
/* All the code for exiting, signals, etc needs to be revamped.
|
|
|
|
This is enough to get c-torture limping though. */
|
|
|
|
void
|
|
sim_stop_reason (sd, reason, sigrc)
|
|
SIM_DESC sd;
|
|
enum sim_stop *reason;
|
|
int *sigrc;
|
|
{
|
|
*reason = sim_stopped;
|
|
if (State.exception == SIGQUIT)
|
|
*sigrc = 0;
|
|
else
|
|
*sigrc = State.exception;
|
|
}
|
|
|
|
void
|
|
sim_fetch_register (sd, rn, memory)
|
|
SIM_DESC sd;
|
|
int rn;
|
|
unsigned char *memory;
|
|
{
|
|
put_word (memory, State.regs[rn]);
|
|
}
|
|
|
|
void
|
|
sim_store_register (sd, rn, memory)
|
|
SIM_DESC sd;
|
|
int rn;
|
|
unsigned char *memory;
|
|
{
|
|
State.regs[rn] = get_word (memory);
|
|
}
|
|
|
|
int
|
|
sim_read (sd, addr, buffer, size)
|
|
SIM_DESC sd;
|
|
SIM_ADDR addr;
|
|
unsigned char *buffer;
|
|
int size;
|
|
{
|
|
int i;
|
|
for (i = 0; i < size; i++)
|
|
buffer[i] = load_mem (addr + i, 1);
|
|
|
|
return size;
|
|
}
|
|
|
|
void
|
|
sim_do_command (sd, cmd)
|
|
SIM_DESC sd;
|
|
char *cmd;
|
|
{
|
|
(*mn10300_callback->printf_filtered) (mn10300_callback, "\"%s\" is not a valid mn10300 simulator command.\n", cmd);
|
|
}
|
|
|
|
SIM_RC
|
|
sim_load (sd, prog, abfd, from_tty)
|
|
SIM_DESC sd;
|
|
char *prog;
|
|
bfd *abfd;
|
|
int from_tty;
|
|
{
|
|
extern bfd *sim_load_file (); /* ??? Don't know where this should live. */
|
|
bfd *prog_bfd;
|
|
|
|
prog_bfd = sim_load_file (sd, myname, mn10300_callback, prog, abfd,
|
|
sim_kind == SIM_OPEN_DEBUG);
|
|
if (prog_bfd == NULL)
|
|
return SIM_RC_FAIL;
|
|
PC = bfd_get_start_address (prog_bfd);
|
|
if (abfd == NULL)
|
|
bfd_close (prog_bfd);
|
|
return SIM_RC_OK;
|
|
}
|