4ed7ed8db2
2015-12-24 Thomas Preud'homme <thomas.preudhomme@arm.com>
bfd/
(tag_cpu_arch_combine): Adjust v4t_plus_v6_m and comb array to account
for new TAG_CPU_ARCH_V4T_PLUS_V6_M value. Deal with NULL values in
comb array.
binutils/
* readelf.c (arm_attr_tag_CPU_arch): Add ARMv8-M Mainline Tag_CPU_arch
value.
(arm_attr_tag_THUMB_ISA_use): Add ARMv8-M Mainline Tag_THUMB_ISA_use
value.
gas/
* config/tc-arm.c (arm_ext_m): Include ARMv8-M.
(arm_ext_v8m): New feature for ARMv8-M.
(arm_ext_atomics): New feature for ARMv8 atomics.
(do_tt): New encoding function for TT* instructions.
(insns): Add new entries for ARMv8-M specific instructions and
reorganize the ones shared by ARMv8-M Mainline and ARMv8-A.
(arm_archs): Define armv8-m.main architecture.
(cpu_arch_ver): Define ARM_ARCH_V8M_MAIN architecture version and
clarify the ordering rule.
(aeabi_set_public_attributes): Use TAG_CPU_ARCH_* macro to refer to
Tag_CPU_arch values for ARMv7e-M detection. Add logic to keep setting
Tag_CPU_arch to ARMv8-A for -march=all. Also set Tag_CPU_arch_profile
to 'A' if extension bit for atomic instructions is set, unless it is
ARMv8-M. Set Tag_THUMB_ISA_use to 3 for ARMv8-M. Set Tag_DIV_use to 0
for ARMv8-M Mainline.
gas/testsuite/
* gas/arm/archv8m.s: New file.
* gas/arm/archv8m-main.d: Likewise.
* gas/arm/attr-march-armv8m.main.d: Likewise.
* gas/arm/any-armv8m.s: Likewise.
* gas/arm/any-armv8m.d: Likewise.
include/elf/
* arm.h (TAG_CPU_ARCH_V8M_MAIN): Declare.
(MAX_TAG_CPU_ARCH): Define to TAG_CPU_ARCH_V8M_MAIN.
(TAG_CPU_ARCH_V4T_PLUS_V6_M): Define to unused value 15.
include/opcode/
* arm.h (ARM_EXT2_ATOMICS): New extension bit.
(ARM_EXT2_V8M): Likewise.
(ARM_EXT_V8): Adjust comment with regards to atomics and remove
mention of legacy use for that bit.
(ARM_AEXT2_V8_1A): New architecture extension bitfield.
(ARM_AEXT2_V8_2A): Likewise.
(ARM_AEXT_V8M_MAIN): Likewise.
(ARM_AEXT2_V8M): Likewise.
(ARM_ARCH_V8A): Use ARM_EXT2_ATOMICS for features in second bitfield.
(ARM_ARCH_V8_1A): Likewise with ARM_AEXT2_V8_1A.
(ARM_ARCH_V8_2A): Likewise with ARM_AEXT2_V8_2A.
(ARM_ARCH_V8M_MAIN): New architecture feature bitfield.
(ARM_ARCH_V8A_FP): Use ARM_EXT2_ATOMICS for features in second bitfield
and reindent.
(ARM_ARCH_V8A_SIMD): Likewise.
(ARM_ARCH_V8A_CRYPTOV1): Likewise.
(ARM_ARCH_V8_1A_FP): Use ARM_AEXT2_V8_1A to set second bitfield of
feature bits.
(ARM_ARCH_V8_1A_SIMD): Likewise.
(ARM_ARCH_V8_1A_CRYPTOV1): Likewise.
opcodes/
* arm-dis.c (arm_opcodes): Guard lda, ldab, ldaex, ldaexb, ldaexh, stl,
stlb, stlh, stlex, stlexb and stlexh by ARM_EXT2_ATOMICS instead of
ARM_EXT_V8.
(thumb32_opcodes): Add entries for wide ARMv8-M instructions.
1176 lines
39 KiB
Plaintext
1176 lines
39 KiB
Plaintext
2015-12-24 Thomas Preud'homme <thomas.preudhomme@arm.com>
|
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|
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* arm-dis.c (arm_opcodes): Guard lda, ldab, ldaex, ldaexb, ldaexh, stl,
|
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stlb, stlh, stlex, stlexb and stlexh by ARM_EXT2_ATOMICS instead of
|
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ARM_EXT_V8.
|
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(thumb32_opcodes): Add entries for wide ARMv8-M instructions.
|
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|
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2015-12-22 Yoshinori Sato <ysato@users.sourceforge.jp>
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|
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opcodes/
|
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* rx-decode.opc (movco): Use uniqe id.
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(movli): Likewise.
|
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(stnz): Condition fix.
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(mvtacgu): Destination fix.
|
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* rx-decode.c: Regenerate.
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|
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2015-12-14 Yoshinori Sato <ysato@users.sourceforge.jp>
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* rx-deocde.opc: Add new instructions pattern.
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* rx-deocde.c: Regenerate.
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* rx-dis.c (register_name): Add new register.
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2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
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* aarch64-asm-2.c: Regenerate.
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* aarch64-dis-2.c: Regenerate.
|
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* aarch64-opc-2.c: Regenerate.
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* aarch64-tbl.h (QL_SSHIFT_H): New.
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(aarch64_opcode_table): Add fp16 versions of scvtf, fcvtzs, ucvtf
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and fcvtzu to the Adv.SIMD scalar shift by immediate group.
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2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
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|
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* aarch64-asm-2.c: Regenerate.
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* aarch64-dis-2.c: Regenerate.
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* aarch64-opc-2.c: Regenerate.
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* aarch64-tbl.h (QL_VSHIFT_H): New.
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(aarch64_opcode_table): Add fp16 versions of scvtf, fcvtzs, ucvtf
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and fcvtzu to the Adv.SIMD shift by immediate group.
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2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
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* aarch64-asm-2.c: Regenerate.
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* aarch64-dis-2.c: Regenerate.
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* aarch64-opc-2.c: Regenerate.
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* aarch64-tbl.h (QL_SISD_PAIR_H): New.
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(aarch64_opcode_table): Add fp16 versions of fmaxnmp, faddp,
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fmaxp, fminnmp, fminp to the Adv.SIMD scalar pairwise group.
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2015-12-14 Matthew Wahab <matthew.wahab@arm.coM>
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* aarch64-dis.c (get_vreg_qualifier_from_value): Update comment
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and adjust calculation to ignore qualifier for type 2H.
|
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* aarch64-opc.c (aarch64_opnd_qualifier): Add "2H".
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2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
|
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* aarch64-asm-2.c: Regenerate.
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* aarch64-dis-2.c: Regenerate.
|
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* aarch64-opc-2.c: Regenerate.
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* aarch64-tbl.h (QL_SIMD_IMM_H): New.
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(aarch64_opcode_table): Add fp16 version of fmov to the Adv.SIMD
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modified immediate group.
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2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
|
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|
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* aarch64-asm-2.c: Regenerate.
|
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* aarch64-dis-2.c: Regenerate.
|
||
* aarch64-opc-2.c: Regenerate.
|
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* aarch64-tbl.h (QL_XLANES_FP_H): New.
|
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(aarch64_opcode_table): Add fp16 versions of fmaxnmv, fmaxv,
|
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fminnmv, fminv to the Adv.SIMD across lanes group.
|
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|
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2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
|
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|
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* aarch64-asm-2.c: Regenerate.
|
||
* aarch64-dis-2.c: Regenerate.
|
||
* aarch64-opc-2.c: Regenerate.
|
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* aarch64-tbl.h (aarch64_opcode_table): Add fp16 versions of fmla,
|
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fmls, fmul and fmulx to the scalar indexed element group.
|
||
|
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2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
|
||
|
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* aarch64-asm-2.c: Regenerate.
|
||
* aarch64-dis-2.c: Regenerate.
|
||
* aarch64-opc-2.c: Regenerate.
|
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* aarch64-tbl.h (QL_ELEMENT_FP_H): New.
|
||
(aarch64_opcode_table): Add fp16 versions of fmla, fmls, fmul and
|
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fmulx to the vector indexed element group.
|
||
|
||
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
|
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|
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* aarch64-asm-2.c: Regenerate.
|
||
* aarch64-dis-2.c: Regenerate.
|
||
* aarch64-opc-2.c: Regenerate.
|
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* aarch64-tbl.h (QL_SISD_FCMP_H_0): new.
|
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(QL_S_2SAMEH): New.
|
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(aarch64_opcode_table): Add fp16 versions of fcvtns, fcvtms,
|
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fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fcvtps, fcvtzs, frecpe,
|
||
frecpx, fcvtnu, fcvtmu, fcvtau, ucvtf, fcmge, fcmle, fcvtpu,
|
||
fcvtzu and frsqrte to the scalar two register misc. group.
|
||
|
||
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
|
||
|
||
* aarch64-asm-2.c: Regenerate.
|
||
* aarch64-dis-2.c: Regenerate.
|
||
* aarch64-opc-2.c: Regenerate.
|
||
* aarch64-tbl.h (QL_V2SAMEH): New.
|
||
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
|
||
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
|
||
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
|
||
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
|
||
and fsqrt to the vector register misc. group.
|
||
|
||
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
|
||
|
||
* aarch64-asm-2.c: Regenerate.
|
||
* aarch64-dis-2.c: Regenerate.
|
||
* aarch64-opc-2.c: Regenerate.
|
||
* aarch64-tbl.h (aarch64_opcode_table): Add fp16 versions of
|
||
fmulx, fcmeq, frecps, frsqrts, fcmge, facge, fabd, fcmgt and facgt
|
||
to the scalar three same group.
|
||
|
||
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
|
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|
||
* aarch64-asm-2.c: Regenerate.
|
||
* aarch64-dis-2.c: Regenerate.
|
||
* aarch64-opc-2.c: Regenerate.
|
||
* aarch64-tbl.h (QL_V3SAMEH): New.
|
||
(aarch64_opcode_table): Add fp16 versions of fmaxnm, fmla, fadd,
|
||
fmulx, fcmeq, fmax, frecps, fminnm, fmls, fsub, fmin, frsqrts,
|
||
fmaxnmp, faddp, fmul, fcmge, facge, fmaxp, fdiv, fminnmp, fabd,
|
||
fcmgt, facgt and fminp to the vector three same group.
|
||
|
||
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
|
||
|
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* aarch64-tbl.h (aarch64_feature_simd_f16): New.
|
||
(SIMD_F16): New.
|
||
|
||
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
|
||
|
||
* aarch64-opc.c (aarch64_sys_reg_supported_p): Add mistakenly
|
||
removed statement.
|
||
(aarch64_pstatefield_supported_p): Move feature checks for AT
|
||
registers ..
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(aarch64_sys_ins_reg_supported_p): .. to here.
|
||
|
||
2015-12-12 Alan Modra <amodra@gmail.com>
|
||
|
||
PR 19359
|
||
* ppc-opc.c (insert_fxm): Remove "ignored" from error message.
|
||
(powerpc_opcodes): Remove single-operand mfcr.
|
||
|
||
2015-12-11 Matthew Wahab <matthew.wahab@arm.com>
|
||
|
||
* aarch64-asm.c (aarch64_ins_hint): New.
|
||
* aarch64-asm.h (aarch64_ins_hint): Declare.
|
||
* aarch64-dis.c (aarch64_ext_hint): New.
|
||
* aarch64-dis.h (aarch64_ext_hint): Declare.
|
||
* aarch64-opc-2.c: Regenerate.
|
||
* aarch64-opc.c (aarch64_hint_options): New.
|
||
* aarch64-tbl.h (AARCH64_OPERANDS): Fix typos.
|
||
|
||
2015-12-11 Matthew Wahab <matthew.wahab@arm.com>
|
||
|
||
* aarch64-gen.c (find_alias_opcode): Set max_num_aliases to 16.
|
||
|
||
2015-12-11 Matthew Wahab <matthew.wahab@arm.com>
|
||
|
||
* aarch64-opc.c (aarch64_sys_reg): Add pbmlimitr_el1, pmbptr_el1,
|
||
pmbsr_el1, pmbidr_el1, pmscr_el1, pmsicr_el1, pmsirr_el1,
|
||
pmsfcr_el1, pmsevfr_el1, pmslatfr_el1, pmsidr_el1, pmscr_el2 and
|
||
pmscr_el2.
|
||
(aarch64_sys_reg_supported_p): Add architecture feature tests for
|
||
the new registers.
|
||
|
||
2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
|
||
|
||
* aarch64-opc.c (aarch64_sys_regs_at): Add "s1e1rp" and "s1e1wp".
|
||
(aarch64_sys_ins_reg_supported_p): Add ARMv8.2 system register
|
||
feature test for "s1e1rp" and "s1e1wp".
|
||
|
||
2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
|
||
|
||
* aarch64-opc.c (aarch64_sys_regs_dc): Add "cvap".
|
||
(aarch64_sys_ins_reg_supported_p): New.
|
||
|
||
2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
|
||
|
||
* aarch64-dis.c (aarch64_ext_regrt_sysins): Replace use of has_xt
|
||
with aarch64_sys_ins_reg_has_xt.
|
||
(aarch64_ext_sysins_op): Likewise.
|
||
* aarch64-opc.c (operand_general_constraint_met_p): Likewise.
|
||
(F_HASXT): New.
|
||
(aarch64_sys_regs_ic): Update for changes to aarch64_sys_ins_reg.
|
||
(aarch64_sys_regs_dc): Likewise.
|
||
(aarch64_sys_regs_at): Likewise.
|
||
(aarch64_sys_regs_tlbi): Likewise.
|
||
(aarch64_sys_ins_reg_has_xt): New.
|
||
|
||
2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
|
||
|
||
* aarch64-opc.c (aarch64_sys_regs): Add "uao".
|
||
(aarch64_sys_reg_supported_p): Add comment. Add checks for "uao".
|
||
(aarch64_pstatefields): Add "uao".
|
||
(aarch64_pstatefield_supported_p): Add checks for "uao".
|
||
|
||
2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
|
||
|
||
* aarch64-opc.c (aarch64_sys_regs): Add "vsesr_el2", "erridr_el1",
|
||
"errselr_el1", "erxfr_el1", "erxctlr", "erxaddr_el1",
|
||
"erxmisc0_el1", "erxmisc1_el1", "disr_el1" and "vdisr_el2".
|
||
(aarch64_sys_reg_supported_p): Add architecture feature tests for
|
||
new registers.
|
||
|
||
2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
|
||
|
||
* aarch64-asm-2.c: Regenerate.
|
||
* aarch64-dis-2.c: Regenerate.
|
||
* aarch64-tbl.h (aarch64_feature_ras): New.
|
||
(RAS): New.
|
||
(aarch64_opcode_table): Add "esb".
|
||
|
||
2015-12-09 H.J. Lu <hongjiu.lu@intel.com>
|
||
|
||
* i386-dis.c (MOD_0F01_REG_5): New.
|
||
(RM_0F01_REG_5): Likewise.
|
||
(reg_table): Use MOD_0F01_REG_5.
|
||
(mod_table): Add MOD_0F01_REG_5.
|
||
(rm_table): Add RM_0F01_REG_5.
|
||
* i386-gen.c (cpu_flag_init): Add CPU_OSPKE_FLAGS.
|
||
(cpu_flags): Add CpuOSPKE.
|
||
* i386-opc.h (CpuOSPKE): New.
|
||
(i386_cpu_flags): Add cpuospke.
|
||
* i386-opc.tbl: Add rdpkru and wrpkru instructions.
|
||
* i386-init.h: Regenerated.
|
||
* i386-tbl.h: Likewise.
|
||
|
||
2015-12-07 DJ Delorie <dj@redhat.com>
|
||
|
||
* rl78-decode.opc: Enable MULU for all ISAs.
|
||
* rl78-decode.c: Regenerate.
|
||
|
||
2015-12-07 Alan Modra <amodra@gmail.com>
|
||
|
||
* opcodes/ppc-opc.c (powerpc_opcodes): Sort power9 insns by
|
||
major opcode/xop.
|
||
|
||
2015-12-04 Claudiu Zissulescu <claziss@synopsys.com>
|
||
|
||
* arc-dis.c (special_flag_p): Match full mnemonic.
|
||
* arc-opc.c (print_insn_arc): Check section size to read
|
||
appropriate number of bytes. Fix printing.
|
||
* arc-tbl.h: Fix instruction table. Allow clri/seti instruction without
|
||
arguments.
|
||
|
||
2015-12-02 Andre Vieira <andre.simoesdiasvieira@arm.com>
|
||
|
||
* arm-dis.c (arm_opcodes): <ldaexh>: Fix typo...
|
||
<ldah>: ... to this.
|
||
|
||
2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
|
||
|
||
* aarch64-asm-2.c: Regenerate.
|
||
* aarch64-dis-2.c: Regenerate.
|
||
* aarch64-opc-2.c: Regenerate.
|
||
* aarch64-tbl.h (QL_FIX2FP_H, QL_FP2FIX_H): New.
|
||
(QL_INT2FP_H, QL_FP2INT_H): New.
|
||
(QL_FP2_H, QL_FP3_H, QL_FP4_H): New
|
||
(QL_DST_H): New.
|
||
(QL_FCCMP_H): New.
|
||
(aarch64_opcode_table): Add 16-bit variants of scvt, ucvtf,
|
||
fcvtzs, fcvtzu, fcvtns, fcvtnu, scvtf, ucvtf, fcvtas, fcvtau,
|
||
fmov, fcvtpos, fcvtpu, fcvtms, fcvtmu, fcvtzs, fcvtzu, fccmp,
|
||
fccmpe, fcmp, fcmpe, fabs, fneg, fsqrt, frintn, frintp, frintm,
|
||
frintz, frinta, frintx, frinti, fmul, fdiv, fadd, fsub, fmax,
|
||
fmin, fmaxnm, fminnm, fnmul, fmadd, fmsub, fnmadd, fnmsub and
|
||
fcsel.
|
||
|
||
2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
|
||
|
||
* aarch64-opc.c (half_conv_t): New.
|
||
(expand_fp_imm): Replace is_dp flag with the parameter size to
|
||
specify the number of bytes for the required expansion. Treat
|
||
a 16-bit expansion like a 32-bit expansion. Add check for an
|
||
unsupported size request. Update comment.
|
||
(aarch64_print_operand): Update to support 16-bit floating point
|
||
values. Update for changes to expand_fp_imm.
|
||
|
||
2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
|
||
|
||
* aarch64-tbl.h (aarch64_feature_fp_f16): New.
|
||
(FP_F16): New.
|
||
|
||
2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
|
||
|
||
* aarch64-asm-2.c: Regenerate.
|
||
* aarch64-dis-2.c: Regenerate.
|
||
* aarch64-opc-2.c: Regenerate.
|
||
* aarch64-tbl.h (aarchr64_opcode_table): Update "rev", add
|
||
"rev64".
|
||
|
||
2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
|
||
|
||
* aarch64-asm-2.c: Regenerate.
|
||
* aarch64-asm.c (convert_bfc_to_bfm): New.
|
||
(convert_to_real): Add case for OP_BFC.
|
||
* aarch64-dis-2.c: Regenerate.
|
||
* aarch64-dis.c: (convert_bfm_to_bfc): New.
|
||
(convert_to_alias): Add case for OP_BFC.
|
||
* aarch64-opc-2.c: Regenerate.
|
||
* aarch64-opc.c (operand_general_constraint_met_p): Weaken assert
|
||
to allow width operand in three-operand instructions.
|
||
* aarch64-tbl.h (QL_BF1): New.
|
||
(aarch64_feature_v8_2): New.
|
||
(ARMV8_2): New.
|
||
(aarch64_opcode_table): Add "bfc".
|
||
|
||
2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
|
||
|
||
* aarch64-asm-2.c: Regenerate.
|
||
* aarch64-dis-2.c: Regenerate.
|
||
* aarch64-dis.c: Weaken assert.
|
||
* aarch64-gen.c: Include the instruction in the list of its
|
||
possible aliases.
|
||
|
||
2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
|
||
|
||
* aarch64-opc.c (aarch64_sys_regs): Add "id_aa64mmfr2_el1".
|
||
(aarch64_sys_reg_supported_p): Add ARMv8.2 system register
|
||
feature test.
|
||
|
||
2015-11-23 Tristan Gingold <gingold@adacore.com>
|
||
|
||
* arm-dis.c (print_insn): Also set is_thumb for Mach-O.
|
||
|
||
2015-11-20 Matthew Wahab <matthew.wahab@arm.com>
|
||
|
||
* aarch64-opc.c (aarch64_sys_regs): Add spsr_el12, elr_el12,
|
||
sctlr_el12, cpacr_el12, ttbr1_el2, ttbr0_el12, ttbr1_el12,
|
||
tcr_el12, afsr0_el12, afsr1_el12, esr_el12, far_el12, mair_el12,
|
||
amair_el12, vbar_el12, contextidr_el2, contextidr_el12,
|
||
cntkctl_el12, cntp_tval_el02, cntp_ctl_el02, cntp_cval_el02,
|
||
cntv_tval_el02, cntv_ctl_el02, cntv_cval_el02, cnthv_tval_el2,
|
||
cnthv_ctl_el2, cnthv_cval_el2.
|
||
(aarch64_sys_reg_supported_p): Update for the new system
|
||
registers.
|
||
|
||
2015-11-20 Nick Clifton <nickc@redhat.com>
|
||
|
||
PR binutils/19224
|
||
* h8300-dis.c (bfd_h8_disassemble): Remove redundant if clause.
|
||
|
||
2015-11-20 Nick Clifton <nickc@redhat.com>
|
||
|
||
* po/zh_CN.po: Updated simplified Chinese translation.
|
||
|
||
2015-11-19 Matthew Wahab <matthew.wahab@arm.com>
|
||
|
||
* aarch64-opc.c (operand_general_constraint_met_p): Check validity
|
||
of MSR PAN immediate operand.
|
||
|
||
2015-11-16 Nick Clifton <nickc@redhat.com>
|
||
|
||
* rx-dis.c (condition_names): Replace always and never with
|
||
invalid, since the always/never conditions can never be legal.
|
||
|
||
2015-11-13 Tristan Gingold <gingold@adacore.com>
|
||
|
||
* configure: Regenerate.
|
||
|
||
2015-11-11 Alan Modra <amodra@gmail.com>
|
||
Peter Bergner <bergner@vnet.ibm.com>
|
||
|
||
* ppc-dis.c (ppc_opts): Add "power9" and "pwr9" entries.
|
||
Add PPC_OPCODE_VSX3 to the vsx entry.
|
||
(powerpc_init_dialect): Set default dialect to power9.
|
||
* ppc-opc.c (insert_dcmxs, extract_dcmxs, insert_dxd, extract_dxd,
|
||
insert_dxdn, extract_dxdn, insert_l0, extract_l0, insert_l1,
|
||
extract_l1 insert_xtq6, extract_xtq6): New static functions.
|
||
(insert_esync): Test for illegal L operand value.
|
||
(DCMX, DCMXS, DXD, NDXD, L0, L1, RC, FC, UIM6, X_R, RIC, PRS, XSQ6,
|
||
XTQ6, LRAND, IMM8, DQX, DQX_MASK, DX, DX_MASK, VXVAPS_MASK, VXVA,XVA,
|
||
XX2VA, XVARC, XBF_MASK, XX2UIM4_MASK, XX2BFD_MASK, XX2DCMXS_MASK,
|
||
XVA_MASK, XRLA_MASK, XBFRARB_MASK, XLRAND_MASK, POWER9, PPCVEC3,
|
||
PPCVSX3): New defines.
|
||
(powerpc_opcodes) <ps_cmpu0, ps_cmpo0, ps_cmpu1, ps_cmpo1, fcmpu,
|
||
fcmpo, ftdiv, ftsqrt>: Use XBF_MASK.
|
||
<mcrxr>: Use XBFRARB_MASK.
|
||
<addpcis, bcdcfn., bcdcfsq., bcdcfz., bcdcpsgn., bcdctn., bcdctsq.,
|
||
bcdctz., bcds., bcdsetsgn., bcdsr., bcdtrunc., bcdus., bcdutrunc.,
|
||
cmpeqb, cmprb, cnttzd, cnttzd., cnttzw, cnttzw., copy, copy_first,
|
||
cp_abort, darn, dtstsfi, dtstsfiq, extswsli, extswsli., ldat, ldmx,
|
||
lwat, lxsd, lxsibzx, lxsihzx, lxssp, lxv, lxvb16x, lxvh8x, lxvl, lxvll,
|
||
lxvwsx, lxvx, maddhd, maddhdu, maddld, mcrxrx, mfvsrld, modsd, modsw,
|
||
modud, moduw, msgsync, mtvsrdd, mtvsrws, paste, paste., paste_last,
|
||
rmieg, setb, slbieg, slbsync, stdat, stop, stwat, stxsd, stxsibx,
|
||
stxsihx, stxssp, stxv, stxvb16x, stxvh8x, stxvl, stxvll, stxvx,
|
||
subpcis, urfid, vbpermd, vclzlsbb, vcmpneb, vcmpneb., vcmpneh,
|
||
vcmpneh., vcmpnew, vcmpnew., vcmpnezb, vcmpnezb., vcmpnezh, vcmpnezh.,
|
||
vcmpnezw, vcmpnezw., vctzb, vctzd, vctzh, vctzlsbb, vctzw, vextractd,
|
||
vextractub, vextractuh, vextractuw, vextsb2d, vextsb2w, vextsh2d,
|
||
vextsh2w, vextsw2d, vextublx, vextubrx, vextuhlx, vextuhrx, vextuwlx,
|
||
vextuwrx, vinsertb, vinsertd, vinserth, vinsertw, vmul10cuq,
|
||
vmul10ecuq, vmul10euq, vmul10uq, vnegd, vnegw, vpermr, vprtybd,
|
||
vprtybq, vprtybw, vrldmi, vrldnm, vrlwmi, vrlwnm, vslv, vsrv, wait,
|
||
xsabsqp, xsaddqp, xsaddqpo, xscmpeqdp, xscmpexpdp, xscmpexpqp,
|
||
xscmpgedp, xscmpgtdp, xscmpnedp, xscmpoqp, xscmpuqp, xscpsgnqp,
|
||
xscvdphp, xscvdpqp, xscvhpdp, xscvqpdp, xscvqpdpo, xscvqpsdz,
|
||
xscvqpswz, xscvqpudz, xscvqpuwz, xscvsdqp, xscvudqp, xsdivqp,
|
||
xsdivqpo, xsiexpdp, xsiexpqp, xsmaddqp, xsmaddqpo, xsmaxcdp,
|
||
xsmaxjdp, xsmincdp, xsminjdp, xsmsubqp, xsmsubqpo, xsmulqp, xsmulqpo,
|
||
xsnabsqp, xsnegqp, xsnmaddqp, xsnmaddqpo, xsnmsubqp, xsnmsubqpo,
|
||
xsrqpi, xsrqpix, xsrqpxp, xssqrtqp, xssqrtqpo, xssubqp, xssubqpo,
|
||
xststdcdp, xststdcqp, xststdcsp, xsxexpdp, xsxexpqp, xsxsigdp,
|
||
xsxsigqp, xvcmpnedp, xvcmpnedp., xvcmpnesp, xvcmpnesp., xvcvhpsp,
|
||
xvcvsphp, xviexpdp, xviexpsp, xvtstdcdp, xvtstdcsp, xvxexpdp,
|
||
xvxexpsp, xvxsigdp, xvxsigsp, xxbrd, xxbrh, xxbrq, xxbrw, xxextractuw,
|
||
xxinsertw, xxperm, xxpermr, xxspltib>: New instructions.
|
||
<doze, nap, sleep, rvwinkle, waitasec, lxvx, stxvx>: Disable on POWER9.
|
||
<tlbiel, tlbie, sync, slbmfev, slbmfee>: Add additional operands.
|
||
|
||
2015-11-02 Nick Clifton <nickc@redhat.com>
|
||
|
||
* rx-decode.opc (rx_decode_opcode): Decode extra NOP
|
||
instructions.
|
||
* rx-decode.c: Regenerate.
|
||
|
||
2015-11-02 Nick Clifton <nickc@redhat.com>
|
||
|
||
* rx-decode.opc (rx_disp): If the displacement is zero, set the
|
||
type to RX_Operand_Zero_Indirect.
|
||
* rx-decode.c: Regenerate.
|
||
* rx-dis (print_insn): Handle RX_Operand_Zero_Indirect.
|
||
|
||
2015-10-28 Yao Qi <yao.qi@linaro.org>
|
||
|
||
* aarch64-dis.c (aarch64_decode_insn): Add one argument
|
||
noaliases_p. Update comments. Pass noaliases_p rather than
|
||
no_aliases to aarch64_opcode_decode.
|
||
(print_insn_aarch64_word): Pass no_aliases to
|
||
aarch64_decode_insn.
|
||
|
||
2015-10-27 Vinay <Vinay.G@kpit.com>
|
||
|
||
PR binutils/19159
|
||
* rl78-decode.opc (MOV): Added offset to DE register in index
|
||
addressing mode.
|
||
* rl78-decode.c: Regenerate.
|
||
|
||
2015-10-27 Vinay Kumar <vinay.g@kpit.com>
|
||
|
||
PR binutils/19158
|
||
* rl78-decode.opc: Add 's' print operator to instructions that
|
||
access system registers.
|
||
* rl78-decode.c: Regenerate.
|
||
* rl78-dis.c (print_insn_rl78_common): Decode all system
|
||
registers.
|
||
|
||
2015-10-27 Vinay Kumar <vinay.g@kpit.com>
|
||
|
||
PR binutils/19157
|
||
* rl78-decode.opc: Add 'a' print operator to mov instructions
|
||
using stack pointer plus index addressing.
|
||
* rl78-decode.c: Regenerate.
|
||
|
||
2015-10-14 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
|
||
|
||
* s390-opc.c: Fix comment.
|
||
* s390-opc.txt: Change instruction type for troo, trot, trto, and
|
||
trtt to RRF_U0RER since the second parameter does not need to be a
|
||
register pair.
|
||
|
||
2015-10-08 Nick Clifton <nickc@redhat.com>
|
||
|
||
* arc-dis.c (print_insn_arc): Initiallise insn array.
|
||
|
||
2015-10-07 Yao Qi <yao.qi@linaro.org>
|
||
|
||
* aarch64-dis.c (aarch64_ext_sysins_op): Access field
|
||
'name' rather than 'template'.
|
||
* aarch64-opc.c (aarch64_print_operand): Likewise.
|
||
|
||
2015-10-07 Claudiu Zissulescu <claziss@synopsys.com>
|
||
|
||
* arc-dis.c: Revamped file for ARC support
|
||
* arc-dis.h: Likewise.
|
||
* arc-ext.c: Likewise.
|
||
* arc-ext.h: Likewise.
|
||
* arc-opc.c: Likewise.
|
||
* arc-fxi.h: New file.
|
||
* arc-regs.h: Likewise.
|
||
* arc-tbl.h: Likewise.
|
||
|
||
2015-10-02 Yao Qi <yao.qi@linaro.org>
|
||
|
||
* aarch64-dis.c (disas_aarch64_insn): Remove static. Change
|
||
argument insn type to aarch64_insn. Rename to ...
|
||
(aarch64_decode_insn): ... it.
|
||
(print_insn_aarch64_word): Caller updated.
|
||
|
||
2015-10-02 Yao Qi <yao.qi@linaro.org>
|
||
|
||
* aarch64-dis.c (disas_aarch64_insn): Remove argument PC.
|
||
(print_insn_aarch64_word): Caller updated.
|
||
|
||
2015-09-29 Dominik Vogt <vogt@linux.vnet.ibm.com>
|
||
|
||
* s390-mkopc.c (main): Parse htm and vx flag.
|
||
* s390-opc.txt: Mark instructions from the hardware transactional
|
||
memory and vector facilities with the "htm"/"vx" flag.
|
||
|
||
2015-09-28 Nick Clifton <nickc@redhat.com>
|
||
|
||
* po/de.po: Updated German translation.
|
||
|
||
2015-09-28 Tom Rix <tom@bumblecow.com>
|
||
|
||
* ppc-opc.c (PPC500): Mark some opcodes as invalid
|
||
|
||
2015-09-23 Nick Clifton <nickc@redhat.com>
|
||
|
||
* bfin-dis.c (fmtconst): Remove unnecessary call to the abs
|
||
function.
|
||
* tic30-dis.c (print_branch): Likewise.
|
||
* cgen-asm.c (cgen_parse_signed_integer): Cast integer to signed
|
||
value before left shifting.
|
||
* fr30-ibld.c (fr30_cgen_extract_operand): Likewise.
|
||
* hppa-dis.c (print_insn_hppa): Likewise.
|
||
* mips-dis.c (mips_cp0sel_names_mipsr5900): Delete unused static
|
||
array.
|
||
* msp430-dis.c (msp430_singleoperand): Likewise.
|
||
(msp430_doubleoperand): Likewise.
|
||
(print_insn_msp430): Likewise.
|
||
* nds32-asm.c (parse_operand): Likewise.
|
||
* sh-opc.h (MASK): Likewise.
|
||
* v850-dis.c (get_operand_value): Likewise.
|
||
|
||
2015-09-22 Nick Clifton <nickc@redhat.com>
|
||
|
||
* rx-decode.opc (bwl): Use RX_Bad_Size.
|
||
(sbwl): Likewise.
|
||
(ubwl): Likewise. Rename to ubw.
|
||
(uBWL): Rename to uBW.
|
||
Replace all references to uBWL with uBW.
|
||
* rx-decode.c: Regenerate.
|
||
* rx-dis.c (size_names): Add entry for RX_Bad_Size.
|
||
(opsize_names): Likewise.
|
||
(print_insn_rx): Detect and report RX_Bad_Size.
|
||
|
||
2015-09-22 Anton Blanchard <anton@samba.org>
|
||
|
||
* ppc-opc.c (powerpc_opcodes): Add mfdscr, mfctrl, mtdscr and mtctrl.
|
||
|
||
2015-08-25 Jose E. Marchesi <jose.marchesi@oracle.com>
|
||
|
||
* sparc-dis.c (print_insn_sparc): Handle the privileged register
|
||
%pmcdper.
|
||
|
||
2015-08-24 Jan Stancek <jstancek@redhat.com>
|
||
|
||
* i386-dis.c (print_insn): Fix decoding of three byte operands.
|
||
|
||
2015-08-21 Alexander Fomin <alexander.fomin@intel.com>
|
||
|
||
PR binutils/18257
|
||
* i386-dis.c: Use MOD_TABLE for most of mask instructions.
|
||
(MOD enum): Add MOD_VEX_W_0_0F41_P_0_LEN_1,
|
||
MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
|
||
MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
|
||
MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
|
||
MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
|
||
MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
|
||
MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
|
||
MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
|
||
MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
|
||
MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
|
||
MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
|
||
MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
|
||
MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
|
||
MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
|
||
MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
|
||
MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
|
||
MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
|
||
MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
|
||
MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
|
||
MOD_VEX_W_0_0F92_P_3_LEN_0, MOD_VEX_W_1_0F92_P_3_LEN_0,
|
||
MOD_VEX_W_0_0F93_P_0_LEN_0, MOD_VEX_W_0_0F93_P_2_LEN_0,
|
||
MOD_VEX_W_0_0F93_P_3_LEN_0, MOD_VEX_W_1_0F93_P_3_LEN_0,
|
||
MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
|
||
MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
|
||
MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
|
||
MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
|
||
MOD_VEX_W_0_0F3A30_P_2_LEN_0, MOD_VEX_W_1_0F3A30_P_2_LEN_0,
|
||
MOD_VEX_W_0_0F3A31_P_2_LEN_0, MOD_VEX_W_1_0F3A31_P_2_LEN_0,
|
||
MOD_VEX_W_0_0F3A32_P_2_LEN_0, MOD_VEX_W_1_0F3A32_P_2_LEN_0,
|
||
MOD_VEX_W_0_0F3A33_P_2_LEN_0, MOD_VEX_W_1_0F3A33_P_2_LEN_0.
|
||
(vex_w_table): Replace terminals with MOD_TABLE entries for
|
||
most of mask instructions.
|
||
|
||
2015-08-17 Alan Modra <amodra@gmail.com>
|
||
|
||
* cgen.sh: Trim trailing space from cgen output.
|
||
* ia64-gen.c (print_dependency_table): Don't generate trailing space.
|
||
(print_dis_table): Likewise.
|
||
* opc2c.c (dump_lines): Likewise.
|
||
(orig_filename): Warning fix.
|
||
* ia64-asmtab.c: Regenerate.
|
||
|
||
2015-08-13 Andre Vieira <andre.simoesdiasvieira@arm.com>
|
||
|
||
* arm-dis.c (print_insn_arm): Disassembling for all targets V6
|
||
and higher with ARM instruction set will now mark the 26-bit
|
||
versions of teq,tst,cmn and cmp as UNPREDICTABLE.
|
||
(arm_opcodes): Fix for unpredictable nop being recognized as a
|
||
teq.
|
||
|
||
2015-08-12 Simon Dardis <simon.dardis@imgtec.com>
|
||
|
||
* micromips-opc.c (micromips_opcodes): Re-order table so that move
|
||
based on 'or' is first.
|
||
* mips-opc.c (mips_builtin_opcodes): Ditto.
|
||
|
||
2015-08-11 Nick Clifton <nickc@redhat.com>
|
||
|
||
PR 18800
|
||
* aarch64-tbl.h (aarch64_opcode_table): Fix mask for SIMD EXT
|
||
instruction.
|
||
|
||
2015-08-10 Robert Suchanek <robert.suchanek@imgtec.com>
|
||
|
||
* mips-opc.c (mips_builtin_opcodes): Add "sigrie".
|
||
|
||
2015-08-07 Amit Pawar <Amit.Pawar@amd.com>
|
||
|
||
* i386-gen.c: Remove CpuFMA4 from CPU_ZNVER1_FLAGS.
|
||
* i386-init.h: Regenerated.
|
||
|
||
2015-07-30 H.J. Lu <hongjiu.lu@intel.com>
|
||
|
||
PR binutils/13571
|
||
* i386-dis.c (MOD_0FC3): New.
|
||
(PREFIX_0FC3): Renamed to ...
|
||
(PREFIX_MOD_0_0FC3): This.
|
||
(dis386_twobyte): Replace PREFIX_0FC3 with MOD_0FC3.
|
||
(prefix_table): Replace Ma with Ev on movntiS.
|
||
(mod_table): Add MOD_0FC3.
|
||
|
||
2015-07-27 H.J. Lu <hongjiu.lu@intel.com>
|
||
|
||
* configure: Regenerated.
|
||
|
||
2015-07-23 Alan Modra <amodra@gmail.com>
|
||
|
||
PR 18708
|
||
* i386-dis.c (get64): Avoid signed integer overflow.
|
||
|
||
2015-07-22 Alexander Fomin <alexander.fomin@intel.com>
|
||
|
||
PR binutils/18631
|
||
* i386-dis-evex.h (EVEX_W_0F78_P_2): Replace "EXxmmq" with
|
||
"EXEvexHalfBcstXmmq" for the second operand.
|
||
(EVEX_W_0F79_P_2): Likewise.
|
||
(EVEX_W_0F7A_P_2): Likewise.
|
||
(EVEX_W_0F7B_P_2): Likewise.
|
||
|
||
2015-07-16 Alessandro Marzocchi <alessandro.marzocchi@gmail.com>
|
||
|
||
* arm-dis.c (print_insn_coprocessor): Added support for quarter
|
||
float bitfield format.
|
||
(coprocessor_opcodes): Changed VFP vmov reg,immediate to use new
|
||
quarter float bitfield format.
|
||
|
||
2015-07-14 H.J. Lu <hongjiu.lu@intel.com>
|
||
|
||
* configure: Regenerated.
|
||
|
||
2015-07-03 Alan Modra <amodra@gmail.com>
|
||
|
||
* ppc-opc.c (PPC750, PPC7450, PPC860): Define using PPC_OPCODE_*.
|
||
* ppc-dis.c (ppc_opts): Add 821, 850 and 860 entries. Add
|
||
PPC_OPCODE_7450 to 7450 entry. Add PPC_OPCODE_750 to 750cl entry.
|
||
|
||
2015-07-01 Sandra Loosemore <sandra@codesourcery.com>
|
||
Cesar Philippidis <cesar@codesourcery.com>
|
||
|
||
* nios2-dis.c (nios2_extract_opcode): New.
|
||
(nios2_disassembler_state): New.
|
||
(nios2_find_opcode_hash): Use mach parameter to select correct
|
||
disassembler state.
|
||
(nios2_print_insn_arg): Extend to support new R2 argument letters
|
||
and formats.
|
||
(print_insn_nios2): Check for 16-bit instruction at end of memory.
|
||
* nios2-opc.c (nios2_builtin_regs): Add R2 register attributes.
|
||
(NIOS2_NUM_OPCODES): Rename to...
|
||
(NIOS2_NUM_R1_OPCODES): This.
|
||
(nios2_r2_opcodes): New.
|
||
(NIOS2_NUM_R2_OPCODES): New.
|
||
(nios2_num_r2_opcodes): New.
|
||
(nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): New.
|
||
(nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): New.
|
||
(nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): New.
|
||
(nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): New.
|
||
(nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings): New.
|
||
|
||
2015-06-30 Amit Pawar <Amit.Pawar@amd.com>
|
||
|
||
* i386-dis.c (OP_Mwaitx): New.
|
||
(rm_table): Add monitorx/mwaitx.
|
||
* i386-gen.c (cpu_flag_init): Add CpuMWAITX to CPU_BDVER4_FLAGS
|
||
and CPU_ZNVER1_FLAGS. Add CPU_MWAITX_FLAGS.
|
||
(operand_type_init): Add CpuMWAITX.
|
||
* i386-opc.h (CpuMWAITX): New.
|
||
(i386_cpu_flags): Add cpumwaitx.
|
||
* i386-opc.tbl: Add monitorx and mwaitx.
|
||
* i386-init.h: Regenerated.
|
||
* i386-tbl.h: Likewise.
|
||
|
||
2015-06-22 Peter Bergner <bergner@vnet.ibm.com>
|
||
|
||
* ppc-opc.c (insert_ls): Test for invalid LS operands.
|
||
(insert_esync): New function.
|
||
(LS, WC): Use insert_ls.
|
||
(ESYNC): Use insert_esync.
|
||
|
||
2015-06-22 Nick Clifton <nickc@redhat.com>
|
||
|
||
* dis-buf.c (buffer_read_memory): Fail is stop_vma is set and the
|
||
requested region lies beyond it.
|
||
* bfin-dis.c (print_insn_bfin): Ignore sysop instructions when
|
||
looking for 32-bit insns.
|
||
* mcore-dis.c (print_insn_mcore): Disable stop_vma when reading
|
||
data.
|
||
* sh-dis.c (print_insn_sh): Likewise.
|
||
* tic6x-dis.c (print_insn_tic6x): Disable stop_vma when reading
|
||
blocks of instructions.
|
||
* vax-dis.c (print_insn_vax): Check that the requested address
|
||
does not clash with the stop_vma.
|
||
|
||
2015-06-19 Peter Bergner <bergner@vnet.ibm.com>
|
||
|
||
* ppc-dis.h (skip_optional_operands): Use ppc_optional_operand_value.
|
||
* ppc-opc.c (FXM4): Add non-zero optional value.
|
||
(TBR): Likewise.
|
||
(SXL): Likewise.
|
||
(insert_fxm): Handle new default operand value.
|
||
(extract_fxm): Likewise.
|
||
(insert_tbr): Likewise.
|
||
(extract_tbr): Likewise.
|
||
|
||
2015-06-16 Matthew Wahab <matthew.wahab@arm.com>
|
||
|
||
* arch64-opc.c (aarch64_sys_regs): Add "id_mmfr4_el1".
|
||
|
||
2015-06-16 Szabolcs Nagy <szabolcs.nagy@arm.com>
|
||
|
||
* arm-dis.c (print_insn_coprocessor): Avoid negative shift.
|
||
|
||
2015-06-12 Peter Bergner <bergner@vnet.ibm.com>
|
||
|
||
* ppc-opc.c: Add comment accidentally removed by old commit.
|
||
(MTMSRD_L): Delete.
|
||
|
||
2015-06-04 Peter Bergner <bergner@vnet.ibm.com>
|
||
|
||
* ppc-opc.c: (powerpc_opcodes) <hwsync>: New extended mnemonic.
|
||
|
||
2015-06-04 Nick Clifton <nickc@redhat.com>
|
||
|
||
PR 18474
|
||
* msp430-dis.c (msp430_nooperands): Fix check for emulated insns.
|
||
|
||
2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
|
||
|
||
* arm-dis.c (arm_opcodes): Add "setpan".
|
||
(thumb_opcodes): Add "setpan".
|
||
|
||
2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
|
||
|
||
* arm-dis.c (select_arm_features): Rework to avoid used of redefined
|
||
macros.
|
||
|
||
2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
|
||
|
||
* aarch64-tbl.h (aarch64_feature_rdma): New.
|
||
(RDMA): New.
|
||
(aarch64_opcode_table): Add "sqrmlah" and "sqrdmlsh" instructions.
|
||
* aarch64-asm-2.c: Regenerate.
|
||
* aarch64-dis-2.c: Regenerate.
|
||
* aarch64-opc-2.c: Regenerate.
|
||
|
||
2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
|
||
|
||
* aarch64-tbl.h (aarch64_feature_lor): New.
|
||
(LOR): New.
|
||
(aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr",
|
||
"stllrb", "stllrh".
|
||
* aarch64-asm-2.c: Regenerate.
|
||
* aarch64-dis-2.c: Regenerate.
|
||
* aarch64-opc-2.c: Regenerate.
|
||
|
||
2015-06-01 Matthew Wahab <matthew.wahab@arm.com>
|
||
|
||
* aarch64-opc.c (F_ARCHEXT): New.
|
||
(aarch64_sys_regs): Add "pan".
|
||
(aarch64_sys_reg_supported_p): New.
|
||
(aarch64_pstatefields): Add "pan".
|
||
(aarch64_pstatefield_supported_p): New.
|
||
|
||
2015-06-01 Jan Beulich <jbeulich@suse.com>
|
||
|
||
* i386-tbl.h: Regenerate.
|
||
|
||
2015-06-01 Jan Beulich <jbeulich@suse.com>
|
||
|
||
* i386-dis.c (print_insn): Swap rounding mode specifier and
|
||
general purpose register in Intel mode.
|
||
|
||
2015-06-01 Jan Beulich <jbeulich@suse.com>
|
||
|
||
* i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}.
|
||
* i386-tbl.h: Regenerate.
|
||
|
||
2015-05-18 H.J. Lu <hongjiu.lu@intel.com>
|
||
|
||
* i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp.
|
||
* i386-init.h: Regenerated.
|
||
|
||
2015-05-15 H.J. Lu <hongjiu.lu@intel.com>
|
||
|
||
PR binutis/18386
|
||
* i386-dis.c: Add comments for '@'.
|
||
(x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9.
|
||
(enum x86_64_isa): New.
|
||
(isa64): Likewise.
|
||
(print_i386_disassembler_options): Add amd64 and intel64.
|
||
(print_insn): Handle amd64 and intel64.
|
||
(putop): Handle '@'.
|
||
(OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit.
|
||
* i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64.
|
||
* i386-opc.h (AMD64): New.
|
||
(CpuIntel64): Likewise.
|
||
(i386_cpu_flags): Add cpuamd64 and cpuintel64.
|
||
* i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64.
|
||
Mark direct call/jmp without Disp16|Disp32 as Intel64.
|
||
* i386-init.h: Regenerated.
|
||
* i386-tbl.h: Likewise.
|
||
|
||
2015-05-14 Peter Bergner <bergner@vnet.ibm.com>
|
||
|
||
* ppc-opc.c (IH) New define.
|
||
(powerpc_opcodes) <wait>: Do not enable for POWER7.
|
||
<tlbie>: Add RS operand for POWER7.
|
||
<slbia>: Add IH operand for POWER6.
|
||
|
||
2015-05-11 H.J. Lu <hongjiu.lu@intel.com>
|
||
|
||
* opcodes/i386-opc.tbl (call): Remove Disp16|Disp32 from 64-bit
|
||
direct branch.
|
||
(jmp): Likewise.
|
||
* i386-tbl.h: Regenerated.
|
||
|
||
2015-05-11 H.J. Lu <hongjiu.lu@intel.com>
|
||
|
||
* configure.ac: Support bfd_iamcu_arch.
|
||
* disassemble.c (disassembler): Support bfd_iamcu_arch.
|
||
* i386-gen.c (cpu_flag_init): Add CPU_IAMCU_FLAGS and
|
||
CPU_IAMCU_COMPAT_FLAGS.
|
||
(cpu_flags): Add CpuIAMCU.
|
||
* i386-opc.h (CpuIAMCU): New.
|
||
(i386_cpu_flags): Add cpuiamcu.
|
||
* configure: Regenerated.
|
||
* i386-init.h: Likewise.
|
||
* i386-tbl.h: Likewise.
|
||
|
||
2015-05-08 H.J. Lu <hongjiu.lu@intel.com>
|
||
|
||
PR binutis/18386
|
||
* i386-dis.c (X86_64_E8): New.
|
||
(X86_64_E9): Likewise.
|
||
Update comments on 'T', 'U', 'V'. Add comments for '^'.
|
||
(dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9.
|
||
(x86_64_table): Add X86_64_E8 and X86_64_E9.
|
||
(mod_table): Replace {T|} with ^ on Jcall/Jmp.
|
||
(putop): Handle '^'.
|
||
(OP_J): Ignore the operand size prefix in 64-bit. Don't check
|
||
REX_W.
|
||
|
||
2015-04-30 DJ Delorie <dj@redhat.com>
|
||
|
||
* disassemble.c (disassembler): Choose suitable disassembler based
|
||
on E_ABI.
|
||
* rl78-decode.opc (rl78_decode_opcode): Take ISA parameter. Use
|
||
it to decode mul/div insns.
|
||
* rl78-decode.c: Regenerate.
|
||
* rl78-dis.c (print_insn_rl78): Rename to...
|
||
(print_insn_rl78_common): ...this, take ISA parameter.
|
||
(print_insn_rl78): New.
|
||
(print_insn_rl78_g10): New.
|
||
(print_insn_rl78_g13): New.
|
||
(print_insn_rl78_g14): New.
|
||
(rl78_get_disassembler): New.
|
||
|
||
2015-04-29 Nick Clifton <nickc@redhat.com>
|
||
|
||
* po/fr.po: Updated French translation.
|
||
|
||
2015-04-27 Peter Bergner <bergner@vnet.ibm.com>
|
||
|
||
* ppc-opc.c (DCBT_EO): New define.
|
||
(powerpc_opcodes) <lbarx>: Enable for POWER8 and later.
|
||
<lharx>: Likewise.
|
||
<stbcx.>: Likewise.
|
||
<sthcx.>: Likewise.
|
||
<waitrsv>: Do not enable for POWER7 and later.
|
||
<waitimpl>: Likewise.
|
||
<dcbt>: Default to the two operand form of the instruction for all
|
||
"old" cpus. For "new" cpus, use the operand ordering that matches
|
||
whether the cpu is server or embedded.
|
||
<dcbtst>: Likewise.
|
||
|
||
2015-04-27 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
|
||
|
||
* s390-opc.c: New instruction type VV0UU2.
|
||
* s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK,
|
||
and WFC.
|
||
|
||
2015-04-23 Jan Beulich <jbeulich@suse.com>
|
||
|
||
* i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
|
||
* i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq,
|
||
vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY.
|
||
(vfpclasspd, vfpclassps): Add %XZ.
|
||
|
||
2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
|
||
|
||
* i386-dis.c (PREFIX_UD_SHIFT): Removed.
|
||
(PREFIX_UD_REPZ): Likewise.
|
||
(PREFIX_UD_REPNZ): Likewise.
|
||
(PREFIX_UD_DATA): Likewise.
|
||
(PREFIX_UD_ADDR): Likewise.
|
||
(PREFIX_UD_LOCK): Likewise.
|
||
|
||
2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
|
||
|
||
* i386-dis.c (prefix_requirement): Removed.
|
||
(print_insn): Don't set prefix_requirement. Check
|
||
dp->prefix_requirement instead of prefix_requirement.
|
||
|
||
2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
|
||
|
||
PR binutils/17898
|
||
* i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ...
|
||
(PREFIX_MOD_0_0FC7_REG_6): This.
|
||
(PREFIX_MOD_3_0FC7_REG_6): New.
|
||
(PREFIX_MOD_3_0FC7_REG_7): Likewise.
|
||
(prefix_table): Replace PREFIX_0FC7_REG_6 with
|
||
PREFIX_MOD_0_0FC7_REG_6. Add PREFIX_MOD_3_0FC7_REG_6 and
|
||
PREFIX_MOD_3_0FC7_REG_7.
|
||
(mod_table): Replace PREFIX_0FC7_REG_6 with
|
||
PREFIX_MOD_0_0FC7_REG_6. Use PREFIX_MOD_3_0FC7_REG_6 and
|
||
PREFIX_MOD_3_0FC7_REG_7.
|
||
|
||
2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
|
||
|
||
* i386-dis.c (PREFIX_MANDATORY_REPZ): Removed.
|
||
(PREFIX_MANDATORY_REPNZ): Likewise.
|
||
(PREFIX_MANDATORY_DATA): Likewise.
|
||
(PREFIX_MANDATORY_ADDR): Likewise.
|
||
(PREFIX_MANDATORY_LOCK): Likewise.
|
||
(PREFIX_MANDATORY): Likewise.
|
||
(PREFIX_UD_SHIFT): Set to 8
|
||
(PREFIX_UD_REPZ): Updated.
|
||
(PREFIX_UD_REPNZ): Likewise.
|
||
(PREFIX_UD_DATA): Likewise.
|
||
(PREFIX_UD_ADDR): Likewise.
|
||
(PREFIX_UD_LOCK): Likewise.
|
||
(PREFIX_IGNORED_SHIFT): New.
|
||
(PREFIX_IGNORED_REPZ): Likewise.
|
||
(PREFIX_IGNORED_REPNZ): Likewise.
|
||
(PREFIX_IGNORED_DATA): Likewise.
|
||
(PREFIX_IGNORED_ADDR): Likewise.
|
||
(PREFIX_IGNORED_LOCK): Likewise.
|
||
(PREFIX_OPCODE): Likewise.
|
||
(PREFIX_IGNORED): Likewise.
|
||
(Bad_Opcode): Replace PREFIX_MANDATORY with 0.
|
||
(dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
|
||
(three_byte_table): Likewise.
|
||
(mod_table): Likewise.
|
||
(mandatory_prefix): Renamed to ...
|
||
(prefix_requirement): This.
|
||
(prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
|
||
Update PREFIX_90 entry.
|
||
(get_valid_dis386): Check prefix_requirement to see if a prefix
|
||
should be ignored.
|
||
(print_insn): Replace mandatory_prefix with prefix_requirement.
|
||
|
||
2015-04-15 Renlin Li <renlin.li@arm.com>
|
||
|
||
* arm-dis.c (thumb32_opcodes): Define 'D' format control code,
|
||
use it for ssat and ssat16.
|
||
(print_insn_thumb32): Add handle case for 'D' control code.
|
||
|
||
2015-04-06 Ilya Tocar <ilya.tocar@intel.com>
|
||
H.J. Lu <hongjiu.lu@intel.com>
|
||
|
||
* i386-dis-evex.h (evex_table): Fill prefix_requirement field.
|
||
* i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ,
|
||
PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK,
|
||
PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA,
|
||
PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define.
|
||
(Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX):
|
||
Fill prefix_requirement field.
|
||
(struct dis386): Add prefix_requirement field.
|
||
(dis386): Fill prefix_requirement field.
|
||
(dis386_twobyte): Ditto.
|
||
(twobyte_has_mandatory_prefix_: Remove.
|
||
(reg_table): Fill prefix_requirement field.
|
||
(prefix_table): Ditto.
|
||
(x86_64_table): Ditto.
|
||
(three_byte_table): Ditto.
|
||
(xop_table): Ditto.
|
||
(vex_table): Ditto.
|
||
(vex_len_table): Ditto.
|
||
(vex_w_table): Ditto.
|
||
(mod_table): Ditto.
|
||
(bad_opcode): Ditto.
|
||
(print_insn): Use prefix_requirement.
|
||
(FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4,
|
||
FGRPde_3, FGRPdf_4): Fill prefix_requirement field.
|
||
(float_reg): Ditto.
|
||
|
||
2015-03-30 Mike Frysinger <vapier@gentoo.org>
|
||
|
||
* d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype.
|
||
|
||
2015-03-29 H.J. Lu <hongjiu.lu@intel.com>
|
||
|
||
* Makefile.in: Regenerated.
|
||
|
||
2015-03-25 Anton Blanchard <anton@samba.org>
|
||
|
||
* ppc-dis.c (disassemble_init_powerpc): Only initialise
|
||
powerpc_opcd_indices and vle_opcd_indices once.
|
||
|
||
2015-03-25 Anton Blanchard <anton@samba.org>
|
||
|
||
* ppc-opc.c (powerpc_opcodes): Add slbfee.
|
||
|
||
2015-03-24 Terry Guo <terry.guo@arm.com>
|
||
|
||
* arm-dis.c (opcode32): Updated to use new arm feature struct.
|
||
(opcode16): Likewise.
|
||
(coprocessor_opcodes): Replace bit with feature struct.
|
||
(neon_opcodes): Likewise.
|
||
(arm_opcodes): Likewise.
|
||
(thumb_opcodes): Likewise.
|
||
(thumb32_opcodes): Likewise.
|
||
(print_insn_coprocessor): Likewise.
|
||
(print_insn_arm): Likewise.
|
||
(select_arm_features): Follow new feature struct.
|
||
|
||
2015-03-17 Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com>
|
||
|
||
* i386-dis.c (rm_table): Add clzero.
|
||
* i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS.
|
||
Add CPU_CLZERO_FLAGS.
|
||
(cpu_flags): Add CpuCLZERO.
|
||
* i386-opc.h: Add CpuCLZERO.
|
||
* i386-opc.tbl: Add clzero.
|
||
* i386-init.h: Re-generated.
|
||
* i386-tbl.h: Re-generated.
|
||
|
||
2015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
|
||
|
||
* mips-opc.c (decode_mips_operand): Fix constraint issues
|
||
with u and y operands.
|
||
|
||
2015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
|
||
|
||
* mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.
|
||
|
||
2015-03-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
|
||
|
||
* s390-opc.c: Add new IBM z13 instructions.
|
||
* s390-opc.txt: Likewise.
|
||
|
||
2015-03-10 Renlin Li <renlin.li@arm.com>
|
||
|
||
* aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb,
|
||
stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and
|
||
related alias.
|
||
* aarch64-asm-2.c: Regenerate.
|
||
* aarch64-dis-2.c: Likewise.
|
||
* aarch64-opc-2.c: Likewise.
|
||
|
||
2015-03-03 Jiong Wang <jiong.wang@arm.com>
|
||
|
||
* arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols.
|
||
|
||
2015-02-25 Oleg Endo <olegendo@gcc.gnu.org>
|
||
|
||
* sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of
|
||
arch_sh_up.
|
||
(pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of
|
||
arch_sh2a_nofpu_or_sh4_nommu_nofpu_up.
|
||
|
||
2015-02-23 Vinay <Vinay.G@kpit.com>
|
||
|
||
* rl78-decode.opc (MOV): Added space between two operands for
|
||
'mov' instruction in index addressing mode.
|
||
* rl78-decode.c: Regenerate.
|
||
|
||
2015-02-19 Pedro Alves <palves@redhat.com>
|
||
|
||
* microblaze-dis.h [__cplusplus]: Wrap in extern "C".
|
||
|
||
2015-02-10 Pedro Alves <palves@redhat.com>
|
||
Tom Tromey <tromey@redhat.com>
|
||
|
||
* microblaze-opcm.h (or, and, xor): Rename to microblaze_or,
|
||
microblaze_and, microblaze_xor.
|
||
* microblaze-opc.h (opcodes): Adjust.
|
||
|
||
2015-01-28 James Bowman <james.bowman@ftdichip.com>
|
||
|
||
* Makefile.am: Add FT32 files.
|
||
* configure.ac: Handle FT32.
|
||
* disassemble.c (disassembler): Call print_insn_ft32.
|
||
* ft32-dis.c: New file.
|
||
* ft32-opc.c: New file.
|
||
* Makefile.in: Regenerate.
|
||
* configure: Regenerate.
|
||
* po/POTFILES.in: Regenerate.
|
||
|
||
2015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com>
|
||
|
||
* nds32-asm.c (keyword_sr): Add new system registers.
|
||
|
||
2015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
|
||
|
||
* s390-dis.c (s390_extract_operand): Support vector register
|
||
operands.
|
||
(s390_print_insn_with_opcode): Support new operands types and add
|
||
new handling of optional operands.
|
||
* s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
|
||
and include opcode/s390.h instead.
|
||
(struct op_struct): New field `flags'.
|
||
(insertOpcode, insertExpandedMnemonic): New parameter `flags'.
|
||
(dumpTable): Dump flags.
|
||
(main): Parse flags from the s390-opc.txt file. Add z13 as cpu
|
||
string.
|
||
* s390-opc.c: Add new operands types, instruction formats, and
|
||
instruction masks.
|
||
(s390_opformats): Add new formats for .insn.
|
||
* s390-opc.txt: Add new instructions.
|
||
|
||
2015-01-01 Alan Modra <amodra@gmail.com>
|
||
|
||
Update year range in copyright notice of all files.
|
||
|
||
For older changes see ChangeLog-2014
|
||
|
||
Copyright (C) 2015 Free Software Foundation, Inc.
|
||
|
||
Copying and distribution of this file, with or without modification,
|
||
are permitted in any medium without royalty provided the copyright
|
||
notice and this notice are preserved.
|
||
|
||
Local Variables:
|
||
mode: change-log
|
||
left-margin: 8
|
||
fill-column: 74
|
||
version-control: never
|
||
End:
|