4f7eddc4d1
* Makefile.am (CPU_DOCS): Add c-riscv.texi. * Makefile.in: Regenerate. * doc/all.texi: Set RISCV. * doc/as.texinfo: Add RISCV options. Add RISC-V-Dependent node. Include c-riscv.texi. * doc/c-riscv.texi: Rename RISC-V Options to RISC-V-Opts.
49 lines
1.1 KiB
Plaintext
49 lines
1.1 KiB
Plaintext
@c Copyright (C) 2016 Free Software Foundation, Inc.
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@c This is part of the GAS anual.
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@c For copying conditions, see the file as.texinfo
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@c man end
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@ifset GENERIC
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@page
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@node RISC-V-Dependent
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@chapter RISC-V Dependent Features
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@end ifset
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@ifclear GENERIC
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@node Machine Dependencies
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@chapter RISC-V Dependent Features
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@end ifclear
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@cindex RISC-V support
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@menu
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* RISC-V-Opts:: RISC-V Options
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@end menu
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@node RISC-V-Opts
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@section Options
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The following table lists all availiable RISC-V specific options
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@c man begin OPTIONS
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@table @gcctabopt
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@cindex @samp{-m32} option, RISC-V
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@cindex @samp{-m64} option, RISC-V
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@item -m32 | -m64
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Select the base ISA, either RV32 or RV64.
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@cindex @samp{-mrvc} option, RISC-V
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@item -mrvc
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Enables the C ISA subset for compressed instructions.
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@cindex @samp{-msoft-float} option, RISC-V
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@cindex @samp{-mhard-float} option, RISC-V
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@item -msoft-float | -mhard-float
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Select the floating-point ABI, hard-float has F registers while soft-float
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doesn't.
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@cindex @samp{-march=ISA} option, RISC-V
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@item -march=ISA
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Select the base isa, as specified by ISA. For example -march=RV32IMA.
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@end table
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@c man end
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