5287ad6231
(fpu_arch_vfp_v3, fpu_vfp_ext_v3, fpu_neon_ext_v1)
(fpu_vfp_v3_or_neon_ext): Declare constants.
(neon_el_type): New enumeration of types for Neon vector elements.
(neon_type_el): New struct. Define type and size of a vector element.
(NEON_MAX_TYPE_ELS): Define constant. The maximum number of types per
instruction.
(neon_type): Define struct. The type of an instruction.
(arm_it): Add 'vectype' for the current instruction.
(isscalar, immisalign, regisimm, isquad): New predicates for operands.
(vfp_sp_reg_pos): Rename to...
(vfp_reg_pos): ...this, and add VFP_REG_Dd, VFP_REG_Dm, VFP_REG_Dn
tags.
(arm_reg_type): Add REG_TYPE_NQ (Neon Q register) and REG_TYPE_NDQ
(Neon D or Q register).
(reg_expected_msgs): Sync with above. Allow VFD to mean VFP or Neon D
register.
(GE_OPT_PREFIX_BIG): Define constant, for use in...
(my_get_expression): Allow above constant as argument to accept
64-bit constants with optional prefix.
(arm_reg_parse): Add extra argument to return the specific type of
register in when either a D or Q register (REG_TYPE_NDQ) is
requested. Can be NULL.
(parse_scalar): New function. Parse Neon scalar (vector reg and index).
(parse_reg_list): Update for new arm_reg_parse args.
(parse_vfp_reg_list): Allow parsing of Neon D/Q register lists.
(parse_neon_el_struct_list): New function. Parse element/structure
register lists for VLD<n>/VST<n> instructions.
(s_arm_unwind_save_vfp): Update for new parse_vfp_reg_list args.
(s_arm_unwind_save_mmxwr): Likewise.
(s_arm_unwind_save_mmxwcg): Likewise.
(s_arm_unwind_movsp): Likewise.
(s_arm_unwind_setfp): Likewise.
(parse_big_immediate): New function. Parse an immediate, which may be
64 bits wide. Put results in inst.operands[i].
(parse_shift): Update for new arm_reg_parse args.
(parse_address): Likewise. Add parsing of alignment specifiers.
(parse_neon_mov): Parse the operands of a VMOV instruction.
(operand_parse_code): Add OP_RND, OP_RNQ, OP_RNDQ, OP_RNSC, OP_NRDLST,
OP_NSTRLST, OP_NILO, OP_RNDQ_I0, OP_RR_RNSC, OP_RNDQ_RNSC, OP_RND_RNSC,
OP_VMOV, OP_RNDQ_IMVNb, OP_RNDQ_I63b, OP_I0, OP_I16z, OP_I32z, OP_I64,
OP_I64z, OP_oI32b, OP_oRND, OP_oRNQ, OP_oRNDQ.
(parse_operands): Handle new codes above.
(encode_arm_vfp_sp_reg): Rename to...
(encode_arm_vfp_reg): ...this. Handle D regs (0-31) too. Complain if
selected VFP version only supports D0-D15.
(do_vfp_sp_monadic, do_vfp_sp_dyadic, do_vfp_sp_compare_z)
(do_vfp_dp_sp_cvt, do_vfp_reg_from_sp, do_vfp_reg2_from_sp2)
(do_vfp_sp_from_reg, do_vfp_sp2_from_reg2, do_vfp_sp_ldst)
(do_vfp_dp_ldst, vfp_sp_ldstm, vfp_dp_ldstm): Update for new
encode_arm_vfp_reg name, and allow 32 D regs.
(do_vfp_dp_rd_rm, do_vfp_dp_rn_rd, do_vfp_dp_rd_rn, do_vfp_dp_rd_rn_rm)
(do_vfp_rm_rd_rn): New functions to encode VFP insns allowing 32 D
regs.
(do_vfp_sp_const, do_vfp_dp_const, vfp_conv, do_vfp_sp_conv_16)
(do_vfp_dp_conv_16, do_vfp_sp_conv_32, do_vfp_dp_conv_32): Handle
constant-load and conversion insns introduced with VFPv3.
(neon_tab_entry): New struct.
(NEON_ENC_TAB): Bit patterns for overloaded Neon instructions, and
those which are the targets of pseudo-instructions.
(neon_opc): Enumerate opcodes, use as indices into...
(neon_enc_tab): ...this. Hold data from NEON_ENC_TAB.
(NEON_ENC_INTEGER, NEON_ENC_ARMREG, NEON_ENC_POLY, NEON_ENC_FLOAT)
(NEON_ENC_SCALAR, NEON_ENC_IMMED, NEON_ENC_INTERLV, NEON_ENC_LANE)
(NEON_ENC_DUP): Define meaningful helper macros to look up values in
neon_enc_tab.
(neon_shape): Enumerate shapes (permitted register widths, etc.) for
Neon instructions.
(neon_type_mask): New. Compact type representation for type checking.
(N_SU_ALL, N_SU_32, N_SU_16_64, N_SUF_32, N_I_ALL, N_IF_32): Common
permitted type combinations.
(N_IGNORE_TYPE): New macro.
(neon_check_shape): New function. Check an instruction shape for
multiple alternatives. Return the specific shape for the current
instruction.
(neon_modify_type_size): New function. Modify a vector type and size,
depending on the bit mask in argument 1.
(neon_type_promote): New function. Convert a given "key" type (of an
operand) into the correct type for a different operand, based on a bit
mask.
(type_chk_of_el_type): New function. Convert a type and size into the
compact representation used for type checking.
(el_type_of_type_ckh): New function. Reverse of above (only when a
single bit is set in the bit mask).
(modify_types_allowed): New function. Alter a mask of allowed types
based on a bit mask of modifications.
(neon_check_type): New function. Check the type of the current
instruction against the variable argument list. The "key" type of the
instruction is returned.
(neon_dp_fixup): New function. Fill in and modify instruction bits for
a Neon data-processing instruction depending on whether we're in ARM
mode or Thumb-2 mode.
(neon_logbits): New function.
(neon_three_same, neon_two_same, do_neon_dyadic_i_su)
(do_neon_dyadic_i64_su, neon_imm_shift, do_neon_shl_imm)
(do_neon_qshl_imm, neon_cmode_for_logic_imm, neon_bits_same_in_bytes)
(neon_squash_bits, neon_is_quarter_float, neon_qfloat_bits)
(neon_cmode_for_move_imm, neon_write_immbits, neon_invert_size)
(do_neon_logic, do_neon_bitfield, neon_dyadic, do_neon_dyadic_if_su)
(do_neon_dyadic_if_su_d, do_neon_dyadic_if_i, do_neon_dyadic_if_i_d)
(do_neon_addsub_if_i, neon_exchange_operands, neon_compare)
(do_neon_cmp, do_neon_cmp_inv, do_neon_ceq, neon_scalar_for_mul)
(neon_mul_mac, do_neon_mac_maybe_scalar, do_neon_tst, do_neon_mul)
(do_neon_qdmulh, do_neon_fcmp_absolute, do_neon_fcmp_absolute_inv)
(do_neon_step, do_neon_abs_neg, do_neon_sli, do_neon_sri)
(do_neon_qshlu_imm, do_neon_qmovn, do_neon_qmovun)
(do_neon_rshift_sat_narrow, do_neon_rshift_sat_narrow_u, do_neon_movn)
(do_neon_rshift_narrow, do_neon_shll, neon_cvt_flavour, do_neon_cvt)
(neon_move_immediate, do_neon_mvn, neon_mixed_length)
(do_neon_dyadic_long, do_neon_abal, neon_mac_reg_scalar_long)
(do_neon_mac_maybe_scalar_long, do_neon_dyadic_wide, do_neon_vmull)
(do_neon_ext, do_neon_rev, do_neon_dup, do_neon_mov)
(do_neon_rshift_round_imm, do_neon_movl, do_neon_trn, do_neon_zip_uzp)
(do_neon_sat_abs_neg, do_neon_pair_long, do_neon_recip_est)
(do_neon_cls, do_neon_clz, do_neon_cnt, do_neon_swp, do_neon_tbl_tbx)
(do_neon_ldm_stm, do_neon_ldr_str, do_neon_ld_st_interleave)
(neon_alignment_bit, do_neon_ld_st_lane, do_neon_ld_dup)
(do_neon_ldx_stx): New functions. Neon bit encoding and encoding
helpers.
(parse_neon_type): New function. Parse Neon type specifier.
(opcode_lookup): Allow parsing of Neon type specifiers.
(REGNUM2, REGSETH, REGSET2): New macros.
(reg_names): Add new VFPv3 and Neon registers.
(NUF, nUF, NCE, nCE): New macros for opcode table.
(insns): More VFP registers allowed in fcpyd, fmdhr, fmdlr, fmrdh,
fmrdl, fabsd, fnegd, fsqrtd, faddd, fsubd, fmuld, fdivd, fmacd, fmscd,
fnmuld, fnmacd, fnmscd, fcmpd, fcmpzd, fcmped, fcmpezd, fmdrr, fmrrd.
Add Neon instructions vaba, vhadd, vrhadd, vhsub, vqadd, vqsub, vrshl,
vqrshl, vshl, vqshl{u}, vand, vbic, vorr, vorn, veor, vbsl, vbit, vbif,
vabd, vmax, vmin, vcge, vcgt, vclt, vcle, vceq, vpmax, vpmin, vmla,
vmls, vpadd, vadd, vsub, vtst, vmul, vqdmulh, vqrdmulh, vacge, vacgt,
vaclt, vacle, vrecps, vrsqrts, vabs, vneg, v{r}shr, v{r}sra, vsli,
vsri, vqshrn, vq{r}shr{u}n, v{r}shrn, vshll, vcvt, vmov, vmvn, vabal,
vabdl, vaddl, vsubl, vmlal, vmlsl, vaddw, vsubw, v{r}addhn, v{r}subhn,
vqdmlal, vqdmlsl, vqdmull, vmull, vext, vrev64, vrev32, vrev16, vdup,
vmovl, v{q}movn, vzip, vuzp, vqabs, vqneg, vpadal, vpaddl, vrecpe,
vrsqrte, vcls, vclz, vcnt, vswp, vtrn, vtbl, vtbx, vldm, vstm, vldr,
vstr, vld[1234], vst[1234], fconst[sd], f[us][lh]to[sd],
fto[us][lh][sd].
(tc_arm_regname_to_dw2regnum): Update for arm_reg_parse args.
(arm_cpu_option_table): Add Neon and VFPv3 to Cortex-A8.
(arm_option_cpu_value): Add vfp3 and neon.
(aeabi_set_public_attributes): Support VFPv3 and NEON attributes. Fix
VFPv1 attribute.
896 lines
34 KiB
Plaintext
896 lines
34 KiB
Plaintext
2006-04-26 Julian Brown <julian@codesourcery.com>
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* config/tc-arm.c (limits.h): Include.
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(fpu_arch_vfp_v3, fpu_vfp_ext_v3, fpu_neon_ext_v1)
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(fpu_vfp_v3_or_neon_ext): Declare constants.
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(neon_el_type): New enumeration of types for Neon vector elements.
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(neon_type_el): New struct. Define type and size of a vector element.
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(NEON_MAX_TYPE_ELS): Define constant. The maximum number of types per
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instruction.
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(neon_type): Define struct. The type of an instruction.
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(arm_it): Add 'vectype' for the current instruction.
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(isscalar, immisalign, regisimm, isquad): New predicates for operands.
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(vfp_sp_reg_pos): Rename to...
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(vfp_reg_pos): ...this, and add VFP_REG_Dd, VFP_REG_Dm, VFP_REG_Dn
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tags.
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(arm_reg_type): Add REG_TYPE_NQ (Neon Q register) and REG_TYPE_NDQ
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(Neon D or Q register).
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(reg_expected_msgs): Sync with above. Allow VFD to mean VFP or Neon D
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register.
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(GE_OPT_PREFIX_BIG): Define constant, for use in...
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(my_get_expression): Allow above constant as argument to accept
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64-bit constants with optional prefix.
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(arm_reg_parse): Add extra argument to return the specific type of
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register in when either a D or Q register (REG_TYPE_NDQ) is
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requested. Can be NULL.
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(parse_scalar): New function. Parse Neon scalar (vector reg and index).
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(parse_reg_list): Update for new arm_reg_parse args.
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(parse_vfp_reg_list): Allow parsing of Neon D/Q register lists.
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(parse_neon_el_struct_list): New function. Parse element/structure
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register lists for VLD<n>/VST<n> instructions.
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(s_arm_unwind_save_vfp): Update for new parse_vfp_reg_list args.
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(s_arm_unwind_save_mmxwr): Likewise.
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(s_arm_unwind_save_mmxwcg): Likewise.
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(s_arm_unwind_movsp): Likewise.
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(s_arm_unwind_setfp): Likewise.
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(parse_big_immediate): New function. Parse an immediate, which may be
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64 bits wide. Put results in inst.operands[i].
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(parse_shift): Update for new arm_reg_parse args.
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(parse_address): Likewise. Add parsing of alignment specifiers.
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(parse_neon_mov): Parse the operands of a VMOV instruction.
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(operand_parse_code): Add OP_RND, OP_RNQ, OP_RNDQ, OP_RNSC, OP_NRDLST,
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OP_NSTRLST, OP_NILO, OP_RNDQ_I0, OP_RR_RNSC, OP_RNDQ_RNSC, OP_RND_RNSC,
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OP_VMOV, OP_RNDQ_IMVNb, OP_RNDQ_I63b, OP_I0, OP_I16z, OP_I32z, OP_I64,
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OP_I64z, OP_oI32b, OP_oRND, OP_oRNQ, OP_oRNDQ.
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(parse_operands): Handle new codes above.
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(encode_arm_vfp_sp_reg): Rename to...
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(encode_arm_vfp_reg): ...this. Handle D regs (0-31) too. Complain if
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selected VFP version only supports D0-D15.
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(do_vfp_sp_monadic, do_vfp_sp_dyadic, do_vfp_sp_compare_z)
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(do_vfp_dp_sp_cvt, do_vfp_reg_from_sp, do_vfp_reg2_from_sp2)
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(do_vfp_sp_from_reg, do_vfp_sp2_from_reg2, do_vfp_sp_ldst)
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(do_vfp_dp_ldst, vfp_sp_ldstm, vfp_dp_ldstm): Update for new
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encode_arm_vfp_reg name, and allow 32 D regs.
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(do_vfp_dp_rd_rm, do_vfp_dp_rn_rd, do_vfp_dp_rd_rn, do_vfp_dp_rd_rn_rm)
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(do_vfp_rm_rd_rn): New functions to encode VFP insns allowing 32 D
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regs.
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(do_vfp_sp_const, do_vfp_dp_const, vfp_conv, do_vfp_sp_conv_16)
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(do_vfp_dp_conv_16, do_vfp_sp_conv_32, do_vfp_dp_conv_32): Handle
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constant-load and conversion insns introduced with VFPv3.
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(neon_tab_entry): New struct.
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(NEON_ENC_TAB): Bit patterns for overloaded Neon instructions, and
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those which are the targets of pseudo-instructions.
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(neon_opc): Enumerate opcodes, use as indices into...
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(neon_enc_tab): ...this. Hold data from NEON_ENC_TAB.
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(NEON_ENC_INTEGER, NEON_ENC_ARMREG, NEON_ENC_POLY, NEON_ENC_FLOAT)
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(NEON_ENC_SCALAR, NEON_ENC_IMMED, NEON_ENC_INTERLV, NEON_ENC_LANE)
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(NEON_ENC_DUP): Define meaningful helper macros to look up values in
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neon_enc_tab.
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(neon_shape): Enumerate shapes (permitted register widths, etc.) for
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Neon instructions.
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(neon_type_mask): New. Compact type representation for type checking.
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(N_SU_ALL, N_SU_32, N_SU_16_64, N_SUF_32, N_I_ALL, N_IF_32): Common
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permitted type combinations.
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(N_IGNORE_TYPE): New macro.
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(neon_check_shape): New function. Check an instruction shape for
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multiple alternatives. Return the specific shape for the current
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instruction.
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(neon_modify_type_size): New function. Modify a vector type and size,
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depending on the bit mask in argument 1.
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(neon_type_promote): New function. Convert a given "key" type (of an
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operand) into the correct type for a different operand, based on a bit
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mask.
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(type_chk_of_el_type): New function. Convert a type and size into the
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compact representation used for type checking.
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(el_type_of_type_ckh): New function. Reverse of above (only when a
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single bit is set in the bit mask).
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(modify_types_allowed): New function. Alter a mask of allowed types
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based on a bit mask of modifications.
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(neon_check_type): New function. Check the type of the current
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instruction against the variable argument list. The "key" type of the
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instruction is returned.
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(neon_dp_fixup): New function. Fill in and modify instruction bits for
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a Neon data-processing instruction depending on whether we're in ARM
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mode or Thumb-2 mode.
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(neon_logbits): New function.
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(neon_three_same, neon_two_same, do_neon_dyadic_i_su)
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(do_neon_dyadic_i64_su, neon_imm_shift, do_neon_shl_imm)
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(do_neon_qshl_imm, neon_cmode_for_logic_imm, neon_bits_same_in_bytes)
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(neon_squash_bits, neon_is_quarter_float, neon_qfloat_bits)
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(neon_cmode_for_move_imm, neon_write_immbits, neon_invert_size)
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(do_neon_logic, do_neon_bitfield, neon_dyadic, do_neon_dyadic_if_su)
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(do_neon_dyadic_if_su_d, do_neon_dyadic_if_i, do_neon_dyadic_if_i_d)
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(do_neon_addsub_if_i, neon_exchange_operands, neon_compare)
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(do_neon_cmp, do_neon_cmp_inv, do_neon_ceq, neon_scalar_for_mul)
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(neon_mul_mac, do_neon_mac_maybe_scalar, do_neon_tst, do_neon_mul)
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(do_neon_qdmulh, do_neon_fcmp_absolute, do_neon_fcmp_absolute_inv)
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(do_neon_step, do_neon_abs_neg, do_neon_sli, do_neon_sri)
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(do_neon_qshlu_imm, do_neon_qmovn, do_neon_qmovun)
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(do_neon_rshift_sat_narrow, do_neon_rshift_sat_narrow_u, do_neon_movn)
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(do_neon_rshift_narrow, do_neon_shll, neon_cvt_flavour, do_neon_cvt)
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(neon_move_immediate, do_neon_mvn, neon_mixed_length)
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(do_neon_dyadic_long, do_neon_abal, neon_mac_reg_scalar_long)
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(do_neon_mac_maybe_scalar_long, do_neon_dyadic_wide, do_neon_vmull)
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(do_neon_ext, do_neon_rev, do_neon_dup, do_neon_mov)
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(do_neon_rshift_round_imm, do_neon_movl, do_neon_trn, do_neon_zip_uzp)
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(do_neon_sat_abs_neg, do_neon_pair_long, do_neon_recip_est)
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(do_neon_cls, do_neon_clz, do_neon_cnt, do_neon_swp, do_neon_tbl_tbx)
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(do_neon_ldm_stm, do_neon_ldr_str, do_neon_ld_st_interleave)
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(neon_alignment_bit, do_neon_ld_st_lane, do_neon_ld_dup)
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(do_neon_ldx_stx): New functions. Neon bit encoding and encoding
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helpers.
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(parse_neon_type): New function. Parse Neon type specifier.
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(opcode_lookup): Allow parsing of Neon type specifiers.
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(REGNUM2, REGSETH, REGSET2): New macros.
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(reg_names): Add new VFPv3 and Neon registers.
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(NUF, nUF, NCE, nCE): New macros for opcode table.
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(insns): More VFP registers allowed in fcpyd, fmdhr, fmdlr, fmrdh,
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fmrdl, fabsd, fnegd, fsqrtd, faddd, fsubd, fmuld, fdivd, fmacd, fmscd,
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fnmuld, fnmacd, fnmscd, fcmpd, fcmpzd, fcmped, fcmpezd, fmdrr, fmrrd.
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Add Neon instructions vaba, vhadd, vrhadd, vhsub, vqadd, vqsub, vrshl,
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vqrshl, vshl, vqshl{u}, vand, vbic, vorr, vorn, veor, vbsl, vbit, vbif,
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vabd, vmax, vmin, vcge, vcgt, vclt, vcle, vceq, vpmax, vpmin, vmla,
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vmls, vpadd, vadd, vsub, vtst, vmul, vqdmulh, vqrdmulh, vacge, vacgt,
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vaclt, vacle, vrecps, vrsqrts, vabs, vneg, v{r}shr, v{r}sra, vsli,
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vsri, vqshrn, vq{r}shr{u}n, v{r}shrn, vshll, vcvt, vmov, vmvn, vabal,
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vabdl, vaddl, vsubl, vmlal, vmlsl, vaddw, vsubw, v{r}addhn, v{r}subhn,
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vqdmlal, vqdmlsl, vqdmull, vmull, vext, vrev64, vrev32, vrev16, vdup,
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vmovl, v{q}movn, vzip, vuzp, vqabs, vqneg, vpadal, vpaddl, vrecpe,
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vrsqrte, vcls, vclz, vcnt, vswp, vtrn, vtbl, vtbx, vldm, vstm, vldr,
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vstr, vld[1234], vst[1234], fconst[sd], f[us][lh]to[sd],
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fto[us][lh][sd].
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(tc_arm_regname_to_dw2regnum): Update for arm_reg_parse args.
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(arm_cpu_option_table): Add Neon and VFPv3 to Cortex-A8.
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(arm_option_cpu_value): Add vfp3 and neon.
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(aeabi_set_public_attributes): Support VFPv3 and NEON attributes. Fix
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VFPv1 attribute.
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2006-04-25 Bob Wilson <bob.wilson@acm.org>
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* config/xtensa-relax.c (widen_spec_list): Use new "WIDE.<opcode>"
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syntax instead of hardcoded opcodes with ".w18" suffixes.
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(wide_branch_opcode): New.
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(build_transition): Use it to check for wide branch opcodes with
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either ".w18" or ".w15" suffixes.
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2006-04-25 Bob Wilson <bob.wilson@acm.org>
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* config/tc-xtensa.c (xtensa_create_literal_symbol,
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xg_assemble_literal, xg_assemble_literal_space): Do not set the
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frag's is_literal flag.
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2006-04-25 Bob Wilson <bob.wilson@acm.org>
|
||
|
||
* config/xtensa-relax.c (XCHAL_HAVE_WIDE_BRANCHES): Provide default.
|
||
|
||
2006-04-23 Kazu Hirata <kazu@codesourcery.com>
|
||
|
||
* config/obj-coff.c, config/tc-arm.c, config/tc-bfin.c,
|
||
config/tc-cris.c, config/tc-crx.c, config/tc-i386.c,
|
||
config/tc-ia64.c, config/tc-maxq.c, config/tc-maxq.h,
|
||
config/tc-mips.c, config/tc-msp430.c, config/tc-sh.c,
|
||
config/tc-tic4x.c, config/tc-xtensa.c: Fix comment typos.
|
||
|
||
2005-04-20 Paul Brook <paul@codesourcery.com>
|
||
|
||
* config/tc-arm.c (s_arm_arch, s_arm_cpu, s_arm_fpu): Enable for
|
||
all targets.
|
||
(md_pseudo_table): Enable .arch, .cpu and .fpu for all targets.
|
||
|
||
2006-04-19 Alan Modra <amodra@bigpond.net.au>
|
||
|
||
* Makefile.am (CPU_TYPES): Add maxq and mt. Sort.
|
||
(CPU_OBJ_VALID): Change sense of COFF test to default to invalid.
|
||
Make some cpus unsupported on ELF. Run "make dep-am".
|
||
* Makefile.in: Regenerate.
|
||
|
||
2006-04-19 Alan Modra <amodra@bigpond.net.au>
|
||
|
||
* configure.in (--enable-targets): Indent help message.
|
||
* configure: Regenerate.
|
||
|
||
2006-04-18 H.J. Lu <hongjiu.lu@intel.com>
|
||
|
||
PR gas/2533
|
||
* config/tc-i386.c (i386_immediate): Check illegal immediate
|
||
register operand.
|
||
|
||
2006-04-18 Alan Modra <amodra@bigpond.net.au>
|
||
|
||
* config/tc-i386.c: Formatting.
|
||
(output_disp, output_imm): ISO C90 params.
|
||
|
||
* frags.c (frag_offset_fixed_p): Constify args.
|
||
* frags.h (frag_offset_fixed_p): Ditto.
|
||
|
||
* config/tc-dlx.h (tc_coff_symbol_emit_hook): Delete.
|
||
(COFF_MAGIC): Delete.
|
||
|
||
* config/tc-xc16x.h (TC_LINKRELAX_FIXUP): Delete.
|
||
|
||
2006-04-16 Daniel Jacobowitz <dan@codesourcery.com>
|
||
|
||
* po/POTFILES.in: Regenerated.
|
||
|
||
2006-04-16 Mark Mitchell <mark@codesourcery.com>
|
||
|
||
* doc/as.texinfo: Mention that some .type syntaxes are not
|
||
supported on all architectures.
|
||
|
||
2006-04-14 Sterling Augustine <sterling@tensilica.com>
|
||
|
||
* config/tc-xtensa.c (emit_single_op): Do not relax MOVI
|
||
instructions when such transformations have been disabled.
|
||
|
||
2006-04-10 Sterling Augustine <sterling@tensilica.com>
|
||
|
||
* config/tc-xtensa.c (xg_assemble_vliw_tokens): Record loop target
|
||
symbols in RELAX[_CHECK]_ALIGN_NEXT_OPCODE frags.
|
||
(xtensa_fix_close_loop_end_frags): Use the recorded values instead of
|
||
decoding the loop instructions. Remove current_offset variable.
|
||
(xtensa_fix_short_loop_frags): Likewise.
|
||
(min_bytes_to_other_loop_end): Remove current_offset argument.
|
||
|
||
2006-04-09 Arnold Metselaar <arnold.metselaar@planet.nl>
|
||
|
||
* config/tc-z80.c (z80_optimize_expr): Removed.
|
||
* config/tc-z80.h (z80_optimize_expr, md_optimize_expr): Removed.
|
||
|
||
2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
|
||
|
||
* gas/config/tc-avr.c (mcu_types): Add support for attiny261,
|
||
attiny461, attiny861, attiny25, attiny45, attiny85,attiny24,
|
||
attiny44, attiny84, at90pwm2, at90pwm3, atmega164, atmega324,
|
||
atmega644, atmega329, atmega3290, atmega649, atmega6490,
|
||
atmega406, atmega640, atmega1280, atmega1281, at90can32,
|
||
at90can64, at90usb646, at90usb647, at90usb1286 and
|
||
at90usb1287.
|
||
Move atmega48 and atmega88 from AVR_ISA_M8 to AVR_ISA_PWMx.
|
||
|
||
2006-04-07 Paul Brook <paul@codesourcery.com>
|
||
|
||
* config/tc-arm.c (parse_operands): Set default error message.
|
||
|
||
2006-04-07 Paul Brook <paul@codesourcery.com>
|
||
|
||
* config/tc-arm.c (parse_tb): Set inst.error before returning FAIL.
|
||
|
||
2006-04-07 Paul Brook <paul@codesourcery.com>
|
||
|
||
* config/tc-arm.c (md_apply_fix): Set H bit on blx instruction.
|
||
|
||
2006-04-07 Paul Brook <paul@codesourcery.com>
|
||
|
||
* config/tc-arm.c (THUMB2_LOAD_BIT): Define.
|
||
(move_or_literal_pool): Handle Thumb-2 instructions.
|
||
(do_t_ldst): Call move_or_literal_pool for =N addressing modes.
|
||
|
||
2006-04-07 Alan Modra <amodra@bigpond.net.au>
|
||
|
||
PR 2512.
|
||
* config/tc-i386.c (match_template): Move 64-bit operand tests
|
||
inside loop.
|
||
|
||
2006-04-06 Carlos O'Donell <carlos@codesourcery.com>
|
||
|
||
* po/Make-in: Add install-html target.
|
||
* Makefile.am: Add install-html and install-html-recursive targets.
|
||
* Makefile.in: Regenerate.
|
||
* configure.in: AC_SUBST datarootdir, docdir, htmldir.
|
||
* configure: Regenerate.
|
||
* doc/Makefile.am: Add install-html and install-html-am targets.
|
||
* doc/Makefile.in: Regenerate.
|
||
|
||
2006-04-06 Alan Modra <amodra@bigpond.net.au>
|
||
|
||
* frags.c (frag_offset_fixed_p): Reinitialise offset before
|
||
second scan.
|
||
|
||
2006-04-05 Richard Sandiford <richard@codesourcery.com>
|
||
Daniel Jacobowitz <dan@codesourcery.com>
|
||
|
||
* config/tc-sparc.c (sparc_target_format): Handle TE_VXWORKS.
|
||
(GOTT_BASE, GOTT_INDEX): New.
|
||
(tc_gen_reloc): Don't alter relocations against GOTT_BASE and
|
||
GOTT_INDEX when generating VxWorks PIC.
|
||
* configure.tgt (sparc*-*-vxworks*): Remove this special case;
|
||
use the generic *-*-vxworks* stanza instead.
|
||
|
||
2006-04-04 Alan Modra <amodra@bigpond.net.au>
|
||
|
||
PR 997
|
||
* frags.c (frag_offset_fixed_p): New function.
|
||
* frags.h (frag_offset_fixed_p): Declare.
|
||
* expr.c (expr): Use frag_offset_fixed_p when simplifying subtraction.
|
||
(resolve_expression): Likewise.
|
||
|
||
2006-04-03 Sterling Augustine <sterling@tensilica.com>
|
||
|
||
* config/tc-xtensa.c (init_op_placement_info_table): Check for formats
|
||
of the same length but different numbers of slots.
|
||
|
||
2006-03-30 Andreas Schwab <schwab@suse.de>
|
||
|
||
* configure.in: Fix help string for --enable-targets option.
|
||
* configure: Regenerate.
|
||
|
||
2006-03-28 Nathan Sidwell <nathan@codesourcery.com>
|
||
|
||
* gas/config/tc-m68k.c (find_cf_chip): Merge into ...
|
||
(m68k_ip): ... here. Use for all chips. Protect against buffer
|
||
overrun and avoid excessive copying.
|
||
|
||
* config/tc-m68k.c (m68000_control_regs, m68010_control_regs,
|
||
m68020_control_regs, m68040_control_regs, m68060_control_regs,
|
||
mcf_control_regs, mcf5208_control_regs, mcf5213_control_regs,
|
||
mcf5329_control_regs, mcf5249_control_regs, mcf528x_control_regs,
|
||
mcfv4e_control_regs, m68010_control_regs): Rename and reorder to ...
|
||
(m68000_ctrl, m68010_ctrl, m68020_ctrl, m68040_ctrl, m68060_ctrl,
|
||
mcf_ctrl, mcf5208_ctrl, mcf5213_ctrl, mcf5235_ctrl, mcf5249_ctrl,
|
||
mcf5216_ctrl, mcf5250_ctrl, mcf5271_ctrl, mcf5272_ctrl,
|
||
mcf5282_ctrl, mcfv4e_ctrl): ... these.
|
||
(mcf5275_ctrl, mcf5329_ctrl, mcf5373_ctrl): New.
|
||
(struct m68k_cpu): Change chip field to control_regs.
|
||
(current_chip): Remove.
|
||
(control_regs): New.
|
||
(m68k_archs, m68k_extensions): Adjust.
|
||
(m68k_cpus): Reorder to be in cpu number order. Adjust.
|
||
(CPU_ALLOW_MC, CPU_ALLOW_NEGATION): Remove.
|
||
(find_cf_chip): Reimplement for new organization of cpu table.
|
||
(select_control_regs): Remove.
|
||
(mri_chip): Adjust.
|
||
(struct save_opts): Save control regs, not chip.
|
||
(s_save, s_restore): Adjust.
|
||
(m68k_lookup_cpu): Give deprecated warning when necessary.
|
||
(m68k_init_arch): Adjust.
|
||
(md_show_usage): Adjust for new cpu table organization.
|
||
|
||
2006-03-25 Bernd Schmidt <bernd.schmidt@analog.com>
|
||
|
||
* config/bfin-defs.h (Expr_Node_Type enum): Add Expr_Node_GOT_Reloc.
|
||
* config/bfin-lex.l: Recognize GOT17M4 and FUNCDESC_GOT17M4.
|
||
* config/bfin-parse.y: Include "libbfd.h", "elf/common.h" and
|
||
"elf/bfin.h".
|
||
(GOT17M4, FUNCDESC_GOT17M4): New tokens of type <value>.
|
||
(any_gotrel): New rule.
|
||
(got): Use it, and create Expr_Node_GOT_Reloc nodes.
|
||
* config/tc-bfin.c: Include "libbfd.h", "elf/common.h" and
|
||
"elf/bfin.h".
|
||
(DEFAULT_FLAGS, bfin_flags, bfin_pic_flag): New.
|
||
(bfin_pic_ptr): New function.
|
||
(md_pseudo_table): Add it for ".picptr".
|
||
(OPTION_FDPIC): New macro.
|
||
(md_longopts): Add -mfdpic.
|
||
(md_parse_option): Handle it.
|
||
(md_begin): Set BFD flags.
|
||
(md_apply_fix3, bfin_fix_adjustable): Handle new relocs.
|
||
(bfin_gen_ldstidxi): Adjust to match the trees that the parser gives
|
||
us for GOT relocs.
|
||
* Makefile.am (bfin-parse.o): Update dependencies.
|
||
(DEPTC_bfin_elf): Likewise.
|
||
* Makefile.in: Regenerate.
|
||
|
||
2006-03-25 Richard Sandiford <richard@codesourcery.com>
|
||
|
||
* config/tc-m68k.c (m68k_cpus): Change cpu_cf5208 entries to use
|
||
mcfemac instead of mcfmac.
|
||
|
||
2006-03-23 Michael Matz <matz@suse.de>
|
||
|
||
* config/tc-i386.c (type_names): Correct placement of 'static'.
|
||
(reloc): Map some more relocs to their 64 bit counterpart when
|
||
size is 8.
|
||
(output_insn): Work around breakage if DEBUG386 is defined.
|
||
(output_disp): A BFD_RELOC_64 with GOT_symbol as operand also
|
||
needs to be mapped to BFD_RELOC_X86_64_GOTPC64 or
|
||
BFD_RELOC_X86_64_GOTPC32. Also x86-64 handles pcrel addressing
|
||
different from i386.
|
||
(output_imm): Ditto.
|
||
(lex_got): Recognize @PLTOFF and @GOTPLT. Make @GOT accept also
|
||
Imm64.
|
||
(md_convert_frag): Jumps can now be larger than 2GB away, error
|
||
out in that case.
|
||
(tc_gen_reloc): New relocs are passed through. BFD_RELOC_64
|
||
and BFD_RELOC_64_PCREL are mapped to BFD_RELOC_X86_64_GOTPC64.
|
||
|
||
2006-03-22 Richard Sandiford <richard@codesourcery.com>
|
||
Daniel Jacobowitz <dan@codesourcery.com>
|
||
Phil Edwards <phil@codesourcery.com>
|
||
Zack Weinberg <zack@codesourcery.com>
|
||
Mark Mitchell <mark@codesourcery.com>
|
||
Nathan Sidwell <nathan@codesourcery.com>
|
||
|
||
* config/tc-mips.c (mips_target_format): Handle vxworks targets.
|
||
(md_begin): Complain about -G being used for PIC. Don't change
|
||
the text, data and bss alignments on VxWorks.
|
||
(reloc_needs_lo_p): Don't return true for R_MIPS_GOT16 when
|
||
generating VxWorks PIC.
|
||
(load_address): Extend SVR4_PIC handling to VXWORKS_PIC.
|
||
(macro): Likewise, but do not treat la $25 specially for
|
||
VxWorks PIC, and do not handle jal.
|
||
(OPTION_MVXWORKS_PIC): New macro.
|
||
(md_longopts): Add -mvxworks-pic.
|
||
(md_parse_option): Don't complain about using PIC and -G together here.
|
||
Handle OPTION_MVXWORKS_PIC.
|
||
(md_estimate_size_before_relax): Always use the first relaxation
|
||
sequence on VxWorks.
|
||
* config/tc-mips.h (VXWORKS_PIC): New.
|
||
|
||
2006-03-21 Paul Brook <paul@codesourcery.com>
|
||
|
||
* config/tc-arm.c (md_apply_fix): Fix typo in offset mask.
|
||
|
||
2006-03-21 Sterling Augustine <sterling@tensilica.com>
|
||
|
||
* config/tc-xtensa.c (enforce_three_byte_loop_align): New flag.
|
||
(xtensa_setup_hw_workarounds): Set this new flag for older hardware.
|
||
(get_loop_align_size): New.
|
||
(xtensa_end): Skip xtensa_mark_narrow_branches when not aligning.
|
||
(xtensa_mark_zcl_first_insns): Prevent widening of first loop frag.
|
||
(get_text_align_power): Rewrite to handle inputs in the range 2-8.
|
||
(get_noop_aligned_address): Use get_loop_align_size.
|
||
(get_aligned_diff): Likewise.
|
||
|
||
2006-03-21 Paul Brook <paul@codesourcery.com>
|
||
|
||
* config/tc-arm.c (insns): Correct opcodes for ldrbt and strbt.
|
||
|
||
2006-03-20 Paul Brook <paul@codesourcery.com>
|
||
|
||
* config/tc-arm.c (BAD_BRANCH, BAD_NOT_IT): Define.
|
||
(do_t_branch): Encode branches inside IT blocks as unconditional.
|
||
(do_t_cps): New function.
|
||
(do_t_blx, do_t_bkpt, do_t_branch23, do_t_bx, do_t_bxj, do_t_cpsi,
|
||
do_t_czb, do_t_it, do_t_setend, do_t_tb): Add IT constaints.
|
||
(opcode_lookup): Allow conditional suffixes on all instructions in
|
||
Thumb mode.
|
||
(md_assemble): Advance condexec state before checking for errors.
|
||
(insns): Use do_t_cps.
|
||
|
||
2006-03-20 Paul Brook <paul@codesourcery.com>
|
||
|
||
* config/tc-arm.c (output_relax_insn): Call dwarf2_emit_insn before
|
||
outputting the insn.
|
||
|
||
2006-03-18 Jan-Benedict Glaw <jbglaw@lug-owl.de>
|
||
|
||
* config/tc-vax.c: Update copyright year.
|
||
* config/tc-vax.h: Likewise.
|
||
|
||
2006-03-18 Jan-Benedict Glaw <jbglaw@lug-owl.de>
|
||
|
||
* config/tc-vax.c (md_chars_to_number): Used only locally, so
|
||
make it static.
|
||
* config/tc-vax.h (md_chars_to_number): Remove obsolete declaration.
|
||
|
||
2006-03-17 Paul Brook <paul@codesourcery.com>
|
||
|
||
* config/tc-arm.c (insns): Add ldm and stm.
|
||
|
||
2006-03-17 Ben Elliston <bje@au.ibm.com>
|
||
|
||
PR gas/2446
|
||
* doc/as.texinfo (Ident): Document this directive more thoroughly.
|
||
|
||
2006-03-16 Paul Brook <paul@codesourcery.com>
|
||
|
||
* config/tc-arm.c (insns): Add "svc".
|
||
|
||
2006-03-13 Bob Wilson <bob.wilson@acm.org>
|
||
|
||
* config/tc-xtensa.c (xg_translate_sysreg_op): Remove has_underbar
|
||
flag and avoid double underscore prefixes.
|
||
|
||
2006-03-10 Paul Brook <paul@codesourcery.com>
|
||
|
||
* config/tc-arm.c (md_begin): Handle EABIv5.
|
||
(arm_eabis): Add EF_ARM_EABI_VER5.
|
||
* doc/c-arm.texi: Document -meabi=5.
|
||
|
||
2006-03-10 Ben Elliston <bje@au.ibm.com>
|
||
|
||
* app.c (do_scrub_chars): Simplify string handling.
|
||
|
||
2006-03-07 Richard Sandiford <richard@codesourcery.com>
|
||
Daniel Jacobowitz <dan@codesourcery.com>
|
||
Zack Weinberg <zack@codesourcery.com>
|
||
Nathan Sidwell <nathan@codesourcery.com>
|
||
Paul Brook <paul@codesourcery.com>
|
||
Ricardo Anguiano <anguiano@codesourcery.com>
|
||
Phil Edwards <phil@codesourcery.com>
|
||
|
||
* config/tc-arm.c (md_apply_fix): Install a value of zero into a
|
||
BFD_RELOC_ARM_OFFSET_IMM field if we're going to generate a RELA
|
||
R_ARM_ABS12 reloc.
|
||
(tc_gen_reloc): Keep the original fx_offset for RELA pc-relative
|
||
relocs, but adjust by md_pcrel_from_section. Create R_ARM_ABS12
|
||
relocations for BFD_RELOC_ARM_OFFSET_IMM on RELA targets.
|
||
|
||
2006-03-06 Bob Wilson <bob.wilson@acm.org>
|
||
|
||
* config/tc-xtensa.c (xtensa_post_relax_hook): Generate literal tables
|
||
even when using the text-section-literals option.
|
||
|
||
2006-03-06 Nathan Sidwell <nathan@codesourcery.com>
|
||
|
||
* config/tc-m68k.c (m68k_extensions): Allow 'float' on both m68k
|
||
and cf.
|
||
(m68k_ip): <case 'J'> Check we have some control regs.
|
||
(md_parse_option): Allow raw arch switch.
|
||
(m68k_init_arch): Better detection of arch/cpu mismatch. Detect
|
||
whether 68881 or cfloat was meant by -mfloat.
|
||
(md_show_usage): Adjust extension display.
|
||
(m68k_elf_final_processing): Adjust.
|
||
|
||
2006-03-03 Bjoern Haase <bjoern.m.haase@web.de>
|
||
|
||
* config/tc-avr.c (avr_mod_hash_value): New function.
|
||
(md_apply_fix, exp_mod): Use BFD_RELOC_HH8_LDI and
|
||
BFD_RELOC_MS8_LDI for hlo8() and hhi8()
|
||
(md_begin): Set linkrelax variable to 1, use avr_mod_hash_value
|
||
instead of int avr_ldi_expression: use avr_mod_hash_value instead
|
||
of (int).
|
||
(tc_gen_reloc): Handle substractions of symbols, if possible do
|
||
fixups, abort otherwise.
|
||
* config/tc-avr.h (TC_LINKRELAX_FIXUP, TC_VALIDATE_FIX,
|
||
tc_fix_adjustable): Define.
|
||
|
||
2006-03-02 James E Wilson <wilson@specifix.com>
|
||
|
||
* config/tc-ia64.c (emit_one_bundle): For IA64_OPCODE_LAST, if we
|
||
change the template, then clear md.slot[curr].end_of_insn_group.
|
||
|
||
2006-02-28 Jan Beulich <jbeulich@novell.com>
|
||
|
||
* macro.c (get_any_string): Don't insert quotes for <>-quoted input.
|
||
|
||
2006-02-28 Jan Beulich <jbeulich@novell.com>
|
||
|
||
PR/1070
|
||
* macro.c (getstring): Don't treat parentheses special anymore.
|
||
(get_any_string): Don't consider '(' and ')' as quoting anymore.
|
||
Special-case '(', ')', '[', and ']' when dealing with non-quoting
|
||
characters.
|
||
|
||
2006-02-28 Mat <mat@csail.mit.edu>
|
||
|
||
* dwarf2dbg.c (get_filenum): Don't inadvertently decrease files_in_use.
|
||
|
||
2006-02-27 Jakub Jelinek <jakub@redhat.com>
|
||
|
||
* dw2gencfi.c (struct fde_entry, struct cie_entry): Add signal_frame
|
||
field.
|
||
(CFI_signal_frame): Define.
|
||
(cfi_pseudo_table): Add .cfi_signal_frame.
|
||
(dot_cfi): Handle CFI_signal_frame.
|
||
(output_cie): Handle cie->signal_frame.
|
||
(select_cie_for_fde): Don't share CIE if signal_frame flag is
|
||
different. Copy signal_frame from FDE to newly created CIE.
|
||
* doc/as.texinfo: Document .cfi_signal_frame.
|
||
|
||
2006-02-27 Carlos O'Donell <carlos@codesourcery.com>
|
||
|
||
* doc/Makefile.am: Add html target.
|
||
* doc/Makefile.in: Regenerate.
|
||
* po/Make-in: Add html target.
|
||
|
||
2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
|
||
|
||
* config/tc-i386.c (output_insn): Support Intel Merom New
|
||
Instructions.
|
||
|
||
* config/tc-i386.h (CpuMNI): New.
|
||
(CpuUnknownFlags): Add CpuMNI.
|
||
|
||
2006-02-24 David S. Miller <davem@sunset.davemloft.net>
|
||
|
||
* config/tc-sparc.c (priv_reg_table): Add entry for "gl".
|
||
(hpriv_reg_table): New table for hyperprivileged registers.
|
||
(sparc_ip): New cases '$' and '%' for wrhpr/rdhpr hyperprivileged
|
||
register encoding.
|
||
|
||
2006-02-24 DJ Delorie <dj@redhat.com>
|
||
|
||
* config/tc-m32c.h (md_apply_fix): Define to m32c_apply_fix.
|
||
(tc_gen_reloc): Don't define.
|
||
* config/tc-m32c.c (rl_for, relaxable): New convenience macros.
|
||
(OPTION_LINKRELAX): New.
|
||
(md_longopts): Add it.
|
||
(m32c_relax): New.
|
||
(md_parse_options): Set it.
|
||
(md_assemble): Emit relaxation relocs as needed.
|
||
(md_convert_frag): Emit relaxation relocs as needed.
|
||
(md_cgen_lookup_reloc): Add LAB_8_8 and LAB_8_16.
|
||
(m32c_apply_fix): New.
|
||
(tc_gen_reloc): New.
|
||
(m32c_force_relocation): Force out jump relocs when relaxing.
|
||
(m32c_fix_adjustable): Return false if relaxing.
|
||
|
||
2006-02-24 Paul Brook <paul@codesourcery.com>
|
||
|
||
* config/arm/tc-arm.c (arm_ext_v6_notm, arm_ext_div, arm_ext_v7,
|
||
arm_ext_v7a, arm_ext_v7r, arm_ext_v7m): New variables.
|
||
(struct asm_barrier_opt): Define.
|
||
(arm_v7m_psr_hsh, arm_barrier_opt_hsh): New variables.
|
||
(parse_psr): Accept V7M psr names.
|
||
(parse_barrier): New function.
|
||
(enum operand_parse_code): Add OP_oBARRIER.
|
||
(parse_operands): Implement OP_oBARRIER.
|
||
(do_barrier): New function.
|
||
(do_dbg, do_pli, do_t_barrier, do_t_dbg, do_t_div): New functions.
|
||
(do_t_cpsi): Add V7M restrictions.
|
||
(do_t_mrs, do_t_msr): Validate V7M variants.
|
||
(md_assemble): Check for NULL variants.
|
||
(v7m_psrs, barrier_opt_names): New tables.
|
||
(insns): Add V7 instructions. Mark V6 instructions absent from V7M.
|
||
(md_begin): Initialize arm_v7m_psr_hsh and arm_barrier_opt_hsh.
|
||
(arm_cpu_option_table): Add Cortex-M3, R4 and A8.
|
||
(arm_arch_option_table): Add armv7, armv7a, armv7r and armv7m.
|
||
(struct cpu_arch_ver_table): Define.
|
||
(cpu_arch_ver): New.
|
||
(aeabi_set_public_attributes): Use cpu_arch_ver. Set
|
||
Tag_CPU_arch_profile.
|
||
* doc/c-arm.texi: Document new cpu and arch options.
|
||
|
||
2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
|
||
|
||
* config/tc-ia64.c (operand_match): Handle IA64_OPND_IMMU5b.
|
||
|
||
2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
|
||
|
||
* config/tc-ia64.c: Update copyright years.
|
||
|
||
2006-02-22 H.J. Lu <hongjiu.lu@intel.com>
|
||
|
||
* config/tc-ia64.c (specify_resource): Add the rule 17 from
|
||
SDM 2.2.
|
||
|
||
2005-02-22 Paul Brook <paul@codesourcery.com>
|
||
|
||
* config/tc-arm.c (do_pld): Remove incorrect write to
|
||
inst.instruction.
|
||
(encode_thumb32_addr_mode): Use correct operand.
|
||
|
||
2006-02-21 Paul Brook <paul@codesourcery.com>
|
||
|
||
* config/tc-arm.c (md_apply_fix): Fix off-by-one errors.
|
||
|
||
2006-02-17 Shrirang Khisti <shrirangk@kpitcummins.com>
|
||
Anil Paranjape <anilp1@kpitcummins.com>
|
||
Shilin Shakti <shilins@kpitcummins.com>
|
||
|
||
* Makefile.am: Add xc16x related entry.
|
||
* Makefile.in: Regenerate.
|
||
* configure.in: Added xc16x related entry.
|
||
* configure: Regenerate.
|
||
* config/tc-xc16x.h: New file
|
||
* config/tc-xc16x.c: New file
|
||
* doc/c-xc16x.texi: New file for xc16x
|
||
* doc/all.texi: Entry for xc16x
|
||
* doc/Makefile.texi: Added c-xc16x.texi
|
||
* NEWS: Announce the support for the new target.
|
||
|
||
2006-02-16 Nick Hudson <nick.hudson@dsl.pipex.com>
|
||
|
||
* configure.tgt: set emulation for mips-*-netbsd*
|
||
|
||
2006-02-14 Jakub Jelinek <jakub@redhat.com>
|
||
|
||
* config.in: Rebuilt.
|
||
|
||
2006-02-13 Bob Wilson <bob.wilson@acm.org>
|
||
|
||
* config/tc-xtensa.c (xg_add_opcode_fix): Number operands starting
|
||
from 1, not 0, in error messages.
|
||
(md_assemble): Simplify special-case check for ENTRY instructions.
|
||
(tinsn_has_invalid_symbolic_operands): Do not include opcode and
|
||
operand in error message.
|
||
|
||
2006-02-13 Joseph S. Myers <joseph@codesourcery.com>
|
||
|
||
* configure.tgt (arm-*-linux-gnueabi*): Change to
|
||
arm-*-linux-*eabi*.
|
||
|
||
2006-02-10 Nick Clifton <nickc@redhat.com>
|
||
|
||
* config/tc-crx.c (check_range): Ensure that the sign bit of a
|
||
32-bit value is propagated into the upper bits of a 64-bit long.
|
||
|
||
* config/tc-arc.c (init_opcode_tables): Fix cast.
|
||
(arc_extoper, md_operand): Likewise.
|
||
|
||
2006-02-09 David Heine <dlheine@tensilica.com>
|
||
|
||
* config/tc-xtensa.c (xg_assembly_relax): Increment steps_taken for
|
||
each relaxation step.
|
||
|
||
2006-02-09 Eric Botcazou <ebotcazou@libertysurf.fr>
|
||
|
||
* configure.in (CHECK_DECLS): Add vsnprintf.
|
||
* configure: Regenerate.
|
||
* messages.c (errno.h, stdarg.h, varargs.h, va_list): Do not
|
||
include/declare here, but...
|
||
* as.h: Move code detecting VARARGS idiom to the top.
|
||
(errno.h, stdarg.h, varargs.h, va_list): ...here.
|
||
(vsnprintf): Declare if not already declared.
|
||
|
||
2006-02-08 H.J. Lu <hongjiu.lu@intel.com>
|
||
|
||
* as.c (close_output_file): New.
|
||
(main): Register close_output_file with xatexit before
|
||
dump_statistics. Don't call output_file_close.
|
||
|
||
2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
|
||
|
||
* config/tc-m68k.c (mcf5208_control_regs, mcf5213_control_regs,
|
||
mcf5329_control_regs): New.
|
||
(not_current_architecture, selected_arch, selected_cpu): New.
|
||
(m68k_archs, m68k_extensions): New.
|
||
(archs): Renamed to ...
|
||
(m68k_cpus): ... here. Adjust.
|
||
(n_arches): Remove.
|
||
(md_pseudo_table): Add arch and cpu directives.
|
||
(find_cf_chip, m68k_ip): Adjust table scanning.
|
||
(no_68851, no_68881): Remove.
|
||
(md_assemble): Lazily initialize.
|
||
(select_control_regs): Adjust cpu names. Add 5208, 5213, 5329.
|
||
(md_init_after_args): Move functionality to m68k_init_arch.
|
||
(mri_chip): Adjust table scanning.
|
||
(md_parse_option): Reimplement 'm' processing to add -march & -mcpu
|
||
options with saner parsing.
|
||
(m68k_lookup_cpu, m68k_set_arch, m68k_set_cpu, m68k_set_extension,
|
||
m68k_init_arch): New.
|
||
(s_m68k_cpu, s_m68k_arch): New.
|
||
(md_show_usage): Adjust.
|
||
(m68k_elf_final_processing): Set CF EF flags.
|
||
* config/tc-m68k.h (m68k_init_after_args): Remove.
|
||
(tc_init_after_args): Remove.
|
||
* doc/c-m68k.texi (M68K-Opts): Document -march, -mcpu options.
|
||
(M68k-Directives): Document .arch and .cpu directives.
|
||
|
||
2006-02-05 Arnold Metselaar <arnold.metselaar@planet.nl>
|
||
|
||
* config/tc-z80.c (z80_start_line_hook): allow .equ and .defl as
|
||
synonyms for equ and defl.
|
||
(z80_cons_fix_new): New function.
|
||
(emit_byte): Disallow relative jumps to absolute locations.
|
||
(emit_data): Only handle defb, prototype changed, because defb is
|
||
now handled as pseudo-op rather than an instruction.
|
||
(instab): Entries for defb,defw,db,dw moved from here...
|
||
(md_pseudo_table): ... to here, use generic cons() for defw,dw.
|
||
Add entries for def24,def32,d24,d32.
|
||
(md_assemble): Improved error handling.
|
||
(md_apply_fix): New case BFD_RELOC_24, set fixP->fx_no_overflow to one.
|
||
* config/tc-z80.h (TC_CONS_FIX_NEW): Define.
|
||
(z80_cons_fix_new): Declare.
|
||
* doc/c-z80.texi (defb, db): Mention warning on overflow.
|
||
(def24,d24,def32,d32): New pseudo-ops.
|
||
|
||
2006-02-02 Paul Brook <paul@codesourcery.com>
|
||
|
||
* config/tc-arm.c (do_shift): Remove Thumb-1 constraint.
|
||
|
||
2005-02-02 Paul Brook <paul@codesourcery.com>
|
||
|
||
* config/tc-arm.c (T2_OPCODE_MASK, T2_DATA_OP_SHIFT, T2_OPCODE_AND,
|
||
T2_OPCODE_BIC, T2_OPCODE_ORR, T2_OPCODE_ORN, T2_OPCODE_EOR,
|
||
T2_OPCODE_ADD, T2_OPCODE_ADC, T2_OPCODE_SBC, T2_OPCODE_SUB,
|
||
T2_OPCODE_RSB): Define.
|
||
(thumb32_negate_data_op): New function.
|
||
(md_apply_fix): Use it.
|
||
|
||
2006-01-31 Bob Wilson <bob.wilson@acm.org>
|
||
|
||
* config/xtensa-istack.h (TInsn): Remove record_fix and sub_symbol
|
||
fields.
|
||
* config/tc-xtensa.h (xtensa_frag_type): Remove slot_sub_symbols field.
|
||
* config/tc-xtensa.c (md_apply_fix): Check for unexpected uses of
|
||
subtracted symbols.
|
||
(relaxation_requirements): Add pfinish_frag argument and use it to
|
||
replace setting tinsn->record_fix fields.
|
||
(xg_assemble_vliw_tokens): Adjust calls to relaxation_requirements
|
||
and vinsn_to_insnbuf. Remove references to record_fix and
|
||
slot_sub_symbols fields.
|
||
(xtensa_mark_narrow_branches): Delete unused code.
|
||
(is_narrow_branch_guaranteed_in_range): Handle expr that is not just
|
||
a symbol.
|
||
(convert_frag_immed): Adjust vinsn_to_insnbuf call and do not set
|
||
record_fix fields.
|
||
(tinsn_immed_from_frag): Remove code for handling slot_sub_symbols.
|
||
(vinsn_to_insnbuf): Change use of record_fixup argument, replacing use
|
||
of the record_fix field. Simplify error messages for unexpected
|
||
symbolic operands.
|
||
(set_expr_symbol_offset_diff): Delete.
|
||
|
||
2006-01-31 Paul Brook <paul@codesourcery.com>
|
||
|
||
* config/tc-arm.c (arm_reg_parse): Check if reg is non-NULL.
|
||
|
||
2006-01-31 Paul Brook <paul@codesourcery.com>
|
||
Richard Earnshaw <rearnsha@arm.com>
|
||
|
||
* config/tc-arm.c: Use arm_feature_set.
|
||
(arm_ext_*, arm_arch_full, arm_arch_t2, arm_arch_none,
|
||
arm_cext_iwmmxt, arm_cext_xscale, arm_cext_maverick, fpu_fpa_ext_v1,
|
||
fpu_fpa_ext_v2, fpu_vfp_ext_v1xd, fpu_vfp_ext_v1, fpu_vfp_ext_v2):
|
||
New variables.
|
||
(insns): Use them.
|
||
(md_atof, opcode_select, opcode_select, md_assemble, md_assemble,
|
||
md_begin, arm_parse_extension, arm_parse_cpu, arm_parse_arch,
|
||
arm_parse_fpu, arm_parse_float_abi, aeabi_set_public_attributes,
|
||
s_arm_cpu, s_arm_arch, s_arm_fpu): Use macros for accessing CPU
|
||
feature flags.
|
||
(arm_legacy_option_table, arm_option_cpu_value_table): New types.
|
||
(arm_opts): Move old cpu/arch options from here...
|
||
(arm_legacy_opts): ... to here.
|
||
(md_parse_option): Search arm_legacy_opts.
|
||
(arm_cpus, arm_archs, arm_extensions, arm_fpus)
|
||
(arm_float_abis, arm_eabis): Make const.
|
||
|
||
2006-01-25 Bob Wilson <bob.wilson@acm.org>
|
||
|
||
* config/tc-xtensa.c (md_apply_fix): Set value to zero for PLT relocs.
|
||
|
||
2006-01-21 Jie Zhang <jie.zhang@analog.com>
|
||
|
||
* config/bfin-parse.y (asm_1): Check value range for 16 bit immediate
|
||
in load immediate intruction.
|
||
|
||
2006-01-21 Jie Zhang <jie.zhang@analog.com>
|
||
|
||
* config/bfin-parse.y (value_match): Use correct conversion
|
||
specifications in template string for __FILE__ and __LINE__.
|
||
(binary): Ditto.
|
||
(unary): Ditto.
|
||
|
||
2006-01-18 Alexandre Oliva <aoliva@redhat.com>
|
||
|
||
Introduce TLS descriptors for i386 and x86_64.
|
||
* config/tc-i386.c (tc_i386_fix_adjustable): Handle
|
||
BFD_RELOC_386_TLS_GOTDESC, BFD_RELOC_386_TLS_DESC_CALL,
|
||
BFD_RELOC_X86_64_GOTPC32_TLSDESC, BFD_RELOC_X86_64_TLSDESC_CALL.
|
||
(optimize_disp): Emit fix up for BFD_RELOC_386_TLS_DESC_CALL and
|
||
BFD_RELOC_X86_64_TLSDESC_CALL immediately, and clear the
|
||
displacement bits.
|
||
(build_modrm_byte): Set up zero modrm for TLS desc calls.
|
||
(lex_got): Handle @tlsdesc and @tlscall.
|
||
(md_apply_fix, tc_gen_reloc): Handle the new relocations.
|
||
|
||
2006-01-11 Nick Clifton <nickc@redhat.com>
|
||
|
||
Fixes for building on 64-bit hosts:
|
||
* config/tc-avr.c (mod_index): New union to allow conversion
|
||
between pointers and integers.
|
||
(md_begin, avr_ldi_expression): Use it.
|
||
* config/tc-i370.c (md_assemble): Add cast for argument to print
|
||
statement.
|
||
* config/tc-tic54x.c (subsym_substitute): Likewise.
|
||
* config/tc-mn10200.c (md_assemble): Use a union to convert the
|
||
opindex field of fr_cgen structure into a pointer so that it can
|
||
be stored in a frag.
|
||
* config/tc-mn10300.c (md_assemble): Likewise.
|
||
* config/tc-frv.c (frv_debug_tomcat): Use %p to print pointer
|
||
types.
|
||
* config/tc-v850.c: Replace uses of (int) casts with correct
|
||
types.
|
||
|
||
2006-01-09 H.J. Lu <hongjiu.lu@intel.com>
|
||
|
||
PR gas/2117
|
||
* symbols.c (snapshot_symbol): Don't change a defined symbol.
|
||
|
||
2006-01-03 Hans-Peter Nilsson <hp@bitrange.com>
|
||
|
||
PR gas/2101
|
||
* config/tc-mmix.c (mmix_handle_mmixal): Don't treat #[0-9][FB] as
|
||
a local-label reference.
|
||
|
||
For older changes see ChangeLog-2005
|
||
|
||
Local Variables:
|
||
mode: change-log
|
||
left-margin: 8
|
||
fill-column: 74
|
||
version-control: never
|
||
End:
|