869 lines
24 KiB
C
869 lines
24 KiB
C
/* This file is part of the program psim.
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Copyright (C) 1996, Andrew Cagney <cagney@highland.com.au>
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef _HW_IDE_C_
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#define _HW_IDE_C_
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#include "device_table.h"
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/* DEVICE
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ide - Integrated Disk Electronics
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DESCRIPTION
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This device models the primary/secondary <<ide>> controller
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described in the [CHRPIO] document.
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The controller has separate independant interrupt outputs for each
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<<ide>> bus.
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PROPERTIES
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reg = ... (required)
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The <<reg>> property is described in the document [CHRPIO].
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ready-delay = <integer> (optional)
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If present, this specifies the time that the <<ide>> device takes
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to complete an I/O operation.
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disk@?/ide-byte-count = <integer> (optional)
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disk@?/ide-sector-count = <integer> (optional)
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disk@?/ide-head-count = <integer> (optional)
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The <<ide>> device checks each child (disk device) node to see if
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it has the above properties. If present, these values will be used
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to compute the <<LBA>> address in <<CHS>> addressing mode.
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EXAMPLES
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Enable tracing:
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| -t ide-device \
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Attach the <<ide>> device to the <<pci>> bus at slot one. Specify
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legacy I/O addresses:
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| -o '/phb/ide@1/assigned-addresses \
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| ni0,0,10,1f0 8 \
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| ni0,0,14,3f8 8 \
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| ni0,0,18,170 8 \
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| ni0,0,1c,378 8 \
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| ni0,0,20,200 8' \
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| -o '/phb@0x80000000/ide@1/reg \
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| 1 0 \
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| i0,0,10,0 8 \
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| i0,0,18,0 8 \
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| i0,0,14,6 1 \
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| i0,0,1c,6 1 \
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| i0,0,20,0 8' \
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Note: the fouth and fifth reg entries specify that the register is
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at an offset into the address specified by the base register
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(<<assigned-addresses>>); Apart from restrictions placed by the
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<<pci>> specification, no restrictions are placed on the number of
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base registers specified by the <<assigned-addresses>> property.
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Attach a <<disk>> to the primary and a <<cdrom>> to the secondary
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<<ide>> controller.
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| -o '/phb@0x80000000/ide@1/disk@0/file "zero' \
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| -o '/phb@0x80000000/ide@1/cdrom@2/file "/dev/cdrom"' \
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Connect the two interrupt outputs (a and b) to a <<glue>> device to
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allow testing of the interrupt port. In a real simulation they
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would be wired to the interrupt controller.
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| -o '/phb@0x80000000/glue@2/reg 2 0 ni0,0,0,0 8' \
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| -o '/phb@0x80000000/ide@1 > a 0 /phb@0x80000000/glue@2' \
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| -o '/phb@0x80000000/ide@1 > b 1 /phb@0x80000000/glue@2'
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BUGS
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While the DMA registers are present, DMA support has not yet been
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implemented.
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The number of supported commands is very limited.
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The standards documents appear to be vague on how to specify the
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<<unit-address>> of disk devices devices being attached to the
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<<ide>> controller. I've chosen to use integers with devices zero
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and one going to the primary controller while two and three are
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connected to the secondary controller.
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REFERENCES
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[CHRPIO] PowerPC(tm) Microprocessor Common Hardware Reference
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Platform: I/O Device Reference. http://chrp.apple.com/???.
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[SCHMIDT] The SCSI Bus and IDE Interface - Protocols, Applications
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and Programming. Friedhelm Schmidt (translated by Michael
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Schultz). ISBN 0-201-42284-0. Addison-Wesley Publishing Company.
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*/
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typedef enum _io_direction {
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is_read,
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is_write,
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} io_direction;
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enum {
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nr_ide_controllers = 2,
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nr_ide_drives_per_controller = 2,
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nr_fifo_entries = 8192,
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};
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enum {
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/* command register block - read */
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ide_data_reg,
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ide_error_reg, /*ide_feature_reg*/
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ide_sector_count_reg,
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ide_sector_number_reg,
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ide_cylinder_reg0,
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ide_cylinder_reg1,
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ide_drive_head_reg,
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ide_status_reg, /*ide_command_reg*/
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/* command register block - write */
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ide_feature_reg, /*ide_error_reg*/
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ide_command_reg, /*ide_status_reg*/
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/* control register block - read */
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ide_alternate_status_reg, /*ide_control_reg*/
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ide_control_reg, /*ide_alternate_status_reg*/
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/* dma register block */
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ide_dma_command_reg,
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ide_dma_unused_1_reg,
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ide_dma_status_reg,
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ide_dma_unused_3_reg,
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ide_dma_prd_table_address_reg0,
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ide_dma_prd_table_address_reg1,
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ide_dma_prd_table_address_reg2,
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ide_dma_prd_table_address_reg3,
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nr_ide_registers,
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};
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typedef enum _ide_states {
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idle_state,
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busy_loaded_state,
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busy_drained_state,
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busy_dma_state,
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busy_command_state,
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loading_state,
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draining_state,
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} ide_states;
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static const char *
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ide_state_name(ide_states state)
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{
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switch (state) {
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case idle_state: return "idle";
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case busy_loaded_state: return "busy_loaded_state";
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case busy_drained_state: return "busy_drained_state";
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case busy_dma_state: return "busy_dma_state";
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case busy_command_state: return "busy_command_state";
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case loading_state: return "loading_state";
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case draining_state: return "draining_state";
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default: return "illegal-state";
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}
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}
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typedef struct _ide_geometry {
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int head;
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int sector;
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int byte;
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} ide_geometry;
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typedef struct _ide_drive {
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int nr;
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device *device;
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ide_geometry geometry;
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ide_geometry default_geometry;
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} ide_drive;
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typedef struct _ide_controller {
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int nr;
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ide_states state;
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unsigned8 reg[nr_ide_registers];
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unsigned8 fifo[nr_fifo_entries];
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int fifo_pos;
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int fifo_size;
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ide_drive *current_drive;
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int current_byte;
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int current_transfer;
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ide_drive drive[nr_ide_drives_per_controller];
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device *me;
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event_entry_tag event_tag;
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int is_interrupting;
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signed64 ready_delay;
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} ide_controller;
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static void
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set_interrupt(device *me,
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ide_controller *controller)
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{
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if ((controller->reg[ide_control_reg] & 0x2) == 0) {
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DTRACE(ide, ("controller %d - interrupt set\n", controller->nr));
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device_interrupt_event(me, controller->nr, 1, NULL, 0);
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controller->is_interrupting = 1;
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}
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}
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static void
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clear_interrupt(device *me,
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ide_controller *controller)
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{
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if (controller->is_interrupting) {
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DTRACE(ide, ("controller %d - interrupt clear\n", controller->nr));
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device_interrupt_event(me, controller->nr, 0, NULL, 0);
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controller->is_interrupting = 0;
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}
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}
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static void
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do_event(void *data)
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{
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ide_controller *controller = data;
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device *me = controller->me;
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controller->event_tag = 0;
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switch (controller->state) {
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case busy_loaded_state:
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case busy_drained_state:
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if (controller->current_transfer > 0) {
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controller->state = (controller->state == busy_loaded_state
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? loading_state : draining_state);
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}
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else {
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controller->state = idle_state;
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}
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set_interrupt(me, controller);
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break;
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default:
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device_error(me, "controller %d - unexpected event", controller->nr);
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break;
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}
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}
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static void
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schedule_ready_event(device *me,
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ide_controller *controller)
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{
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if (controller->event_tag != 0)
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device_error(me, "controller %d - attempting to schedule multiple events",
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controller->nr);
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controller->event_tag =
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device_event_queue_schedule(me, controller->ready_delay,
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do_event, controller);
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}
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static void
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do_fifo_read(device *me,
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ide_controller *controller,
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void *dest,
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int nr_bytes)
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{
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if (controller->state != draining_state)
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device_error(me, "controller %d - reading fifo when not ready (%s)",
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controller->nr,
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ide_state_name(controller->state));
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if (controller->fifo_pos + nr_bytes > controller->fifo_size)
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device_error(me, "controller %d - fifo underflow", controller->nr);
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if (nr_bytes > 0) {
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memcpy(dest, &controller->fifo[controller->fifo_pos], nr_bytes);
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controller->fifo_pos += nr_bytes;
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}
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if (controller->fifo_pos == controller->fifo_size) {
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controller->current_transfer -= 1;
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if (controller->current_transfer > 0
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&& controller->current_drive != NULL) {
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DTRACE(ide, ("controller %d:%d - reading %d byte block at 0x%x\n",
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controller->nr,
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controller->current_drive->nr,
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controller->fifo_size,
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controller->current_byte));
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if (device_io_read_buffer(controller->current_drive->device,
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controller->fifo,
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0, controller->current_byte,
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controller->fifo_size,
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NULL, 0)
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!= controller->fifo_size)
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device_error(me, "controller %d - disk %s io read error",
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controller->nr,
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device_path(controller->current_drive->device));
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}
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controller->state = busy_drained_state;
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controller->fifo_pos = 0;
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controller->current_byte += controller->fifo_size;
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schedule_ready_event(me, controller);
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}
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}
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static void
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do_fifo_write(device *me,
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ide_controller *controller,
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const void *source,
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int nr_bytes)
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{
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if (controller->state != loading_state)
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device_error(me, "controller %d - writing fifo when not ready (%s)",
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controller->nr,
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ide_state_name(controller->state));
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if (controller->fifo_pos + nr_bytes > controller->fifo_size)
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device_error(me, "controller %d - fifo overflow", controller->nr);
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if (nr_bytes > 0) {
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memcpy(&controller->fifo[controller->fifo_pos], source, nr_bytes);
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controller->fifo_pos += nr_bytes;
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}
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if (controller->fifo_pos == controller->fifo_size) {
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if (controller->current_transfer > 0
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&& controller->current_drive != NULL) {
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DTRACE(ide, ("controller %d:%d - writing %d byte block at 0x%x\n",
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controller->nr,
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controller->current_drive->nr,
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controller->fifo_size,
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controller->current_byte));
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if (device_io_write_buffer(controller->current_drive->device,
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controller->fifo,
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0, controller->current_byte,
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controller->fifo_size,
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NULL, 0)
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!= controller->fifo_size)
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device_error(me, "controller %d - disk %s io write error",
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controller->nr,
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device_path(controller->current_drive->device));
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}
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controller->current_transfer -= 1;
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controller->fifo_pos = 0;
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controller->current_byte += controller->fifo_size;
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controller->state = busy_loaded_state;
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schedule_ready_event(me, controller);
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}
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}
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static void
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setup_fifo(device *me,
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ide_controller *controller,
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int is_simple,
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int is_with_disk,
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io_direction direction)
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{
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/* find the disk */
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if (is_with_disk) {
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int drive_nr = (controller->reg[ide_drive_head_reg] & 0x10) != 0;
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controller->current_drive = &controller->drive[drive_nr];
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}
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else {
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controller->current_drive = NULL;
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}
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/* number of transfers */
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if (is_simple)
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controller->current_transfer = 1;
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else {
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int sector_count = controller->reg[ide_sector_count_reg];
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if (sector_count == 0)
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controller->current_transfer = 256;
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else
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controller->current_transfer = sector_count;
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}
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/* the transfer size */
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if (controller->current_drive == NULL)
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controller->fifo_size = 512;
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else
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controller->fifo_size = controller->current_drive->geometry.byte;
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/* empty the fifo */
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controller->fifo_pos = 0;
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/* the starting address */
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if (controller->current_drive == NULL)
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controller->current_byte = 0;
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else if (controller->reg[ide_drive_head_reg] & 0x40) {
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/* LBA addressing mode */
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controller->current_byte = controller->fifo_size
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* (((controller->reg[ide_drive_head_reg] & 0xf) << 24)
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| (controller->reg[ide_cylinder_reg1] << 16)
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| (controller->reg[ide_cylinder_reg0] << 8)
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| (controller->reg[ide_sector_number_reg]));
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}
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else if (controller->current_drive->geometry.head != 0
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&& controller->current_drive->geometry.sector != 0) {
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/* CHS addressing mode */
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int head_nr = controller->reg[ide_drive_head_reg] & 0xf;
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int cylinder_nr = ((controller->reg[ide_cylinder_reg1] << 8)
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| controller->reg[ide_cylinder_reg0]);
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int sector_nr = controller->reg[ide_sector_number_reg];
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controller->current_byte = controller->fifo_size
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* ((cylinder_nr * controller->current_drive->geometry.head + head_nr)
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* controller->current_drive->geometry.sector + sector_nr - 1);
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}
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else
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device_error(me, "controller %d:%d - CHS addressing disabled",
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controller->nr, controller->current_drive->nr);
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DTRACE(ide, ("controller %ld:%ld - transfer (%s) %ld blocks of %ld bytes from 0x%lx\n",
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(long)controller->nr,
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controller->current_drive == NULL ? -1L : (long)controller->current_drive->nr,
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direction == is_read ? "read" : "write",
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(long)controller->current_transfer,
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(long)controller->fifo_size,
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(unsigned long)controller->current_byte));
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switch (direction) {
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case is_read:
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/* force a primeing read */
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controller->current_transfer += 1;
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controller->state = draining_state;
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controller->fifo_pos = controller->fifo_size;
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do_fifo_read(me, controller, NULL, 0);
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break;
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case is_write:
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controller->state = loading_state;
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break;
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}
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}
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static void
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do_command(device *me,
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ide_controller *controller,
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int command)
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{
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if (controller->state != idle_state)
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device_error(me, "controller %d - command when not idle", controller->nr);
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switch (command) {
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case 0x20: case 0x21: /* read-sectors */
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setup_fifo(me, controller, 0/*is_simple*/, 1/*is_with_disk*/, is_read);
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break;
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case 0x30: case 0x31: /* write */
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setup_fifo(me, controller, 0/*is_simple*/, 1/*is_with_disk*/, is_write);
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break;
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}
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}
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static unsigned8
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get_status(device *me,
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ide_controller *controller)
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{
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switch (controller->state) {
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case loading_state:
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case draining_state:
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return 0x08; /* data req */
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case busy_loaded_state:
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case busy_drained_state:
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return 0x80; /* busy */
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case idle_state:
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return 0x40; /* drive ready */
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default:
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device_error(me, "internal error");
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return 0;
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}
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}
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/* The address presented to the IDE controler is decoded and then
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mapped onto a controller:reg pair */
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enum {
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nr_address_blocks = 6,
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};
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typedef struct _address_block {
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int space;
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unsigned_word base_addr;
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unsigned_word bound_addr;
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int controller;
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int base_reg;
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} address_block;
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typedef struct _address_decoder {
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address_block block[nr_address_blocks];
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} address_decoder;
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static void
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decode_address(device *me,
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address_decoder *decoder,
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int space,
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unsigned_word address,
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int *controller,
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int *reg,
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io_direction direction)
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{
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int i;
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for (i = 0; i < nr_address_blocks; i++) {
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if (space == decoder->block[i].space
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&& address >= decoder->block[i].base_addr
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&& address <= decoder->block[i].bound_addr) {
|
|
*controller = decoder->block[i].controller;
|
|
*reg = (address
|
|
- decoder->block[i].base_addr
|
|
+ decoder->block[i].base_reg);
|
|
if (direction == is_write) {
|
|
switch (*reg) {
|
|
case ide_error_reg: *reg = ide_feature_reg; break;
|
|
case ide_status_reg: *reg = ide_command_reg; break;
|
|
case ide_alternate_status_reg: *reg = ide_control_reg; break;
|
|
default: break;
|
|
}
|
|
}
|
|
return;
|
|
}
|
|
}
|
|
device_error(me, "address %d:0x%lx invalid",
|
|
space, (unsigned long)address);
|
|
}
|
|
|
|
|
|
static void
|
|
build_address_decoder(device *me,
|
|
address_decoder *decoder)
|
|
{
|
|
int reg;
|
|
for (reg = 1; reg < 6; reg++) {
|
|
reg_property_spec unit;
|
|
int space;
|
|
unsigned_word address;
|
|
unsigned size;
|
|
/* find and decode the reg property */
|
|
if (!device_find_reg_array_property(me, "reg", reg, &unit))
|
|
device_error(me, "missing or invalid reg entry %d", reg);
|
|
device_address_to_attach_address(device_parent(me), &unit.address,
|
|
&space, &address, me);
|
|
device_size_to_attach_size(device_parent(me), &unit.size, &size, me);
|
|
/* insert it into the address decoder */
|
|
switch (reg) {
|
|
case 1:
|
|
case 2:
|
|
/* command register block */
|
|
if (size != 8)
|
|
device_error(me, "reg entry %d must have a size of 8", reg);
|
|
decoder->block[reg-1].space = space;
|
|
decoder->block[reg-1].base_addr = address;
|
|
decoder->block[reg-1].bound_addr = address + size - 1;
|
|
decoder->block[reg-1].controller = (reg + 1) % nr_ide_controllers;
|
|
decoder->block[reg-1].base_reg = ide_data_reg;
|
|
DTRACE(ide, ("controller %d command register block at %d:0x%lx..0x%lx\n",
|
|
decoder->block[reg-1].controller,
|
|
decoder->block[reg-1].space,
|
|
(unsigned long)decoder->block[reg-1].base_addr,
|
|
(unsigned long)decoder->block[reg-1].bound_addr));
|
|
break;
|
|
case 3:
|
|
case 4:
|
|
/* control register block */
|
|
if (size != 1)
|
|
device_error(me, "reg entry %d must have a size of 1", reg);
|
|
decoder->block[reg-1].space = space;
|
|
decoder->block[reg-1].base_addr = address;
|
|
decoder->block[reg-1].bound_addr = address + size - 1;
|
|
decoder->block[reg-1].controller = (reg + 1) % nr_ide_controllers;
|
|
decoder->block[reg-1].base_reg = ide_alternate_status_reg;
|
|
DTRACE(ide, ("controller %d control register block at %d:0x%lx..0x%lx\n",
|
|
decoder->block[reg-1].controller,
|
|
decoder->block[reg-1].space,
|
|
(unsigned long)decoder->block[reg-1].base_addr,
|
|
(unsigned long)decoder->block[reg-1].bound_addr));
|
|
break;
|
|
case 5:
|
|
/* dma register block */
|
|
if (size != 8)
|
|
device_error(me, "reg entry %d must have a size of 8", reg);
|
|
decoder->block[reg-1].space = space;
|
|
decoder->block[reg-1].base_addr = address;
|
|
decoder->block[reg-1].bound_addr = address + 4 - 1;
|
|
decoder->block[reg-1].base_reg = ide_dma_command_reg;
|
|
decoder->block[reg-1].controller = 0;
|
|
DTRACE(ide, ("controller %d dma register block at %d:0x%lx..0x%lx\n",
|
|
decoder->block[reg-1].controller,
|
|
decoder->block[reg-1].space,
|
|
(unsigned long)decoder->block[reg-1].base_addr,
|
|
(unsigned long)decoder->block[reg-1].bound_addr));
|
|
decoder->block[reg].space = space;
|
|
decoder->block[reg].base_addr = address + 4;
|
|
decoder->block[reg].bound_addr = address + 8 - 1;
|
|
decoder->block[reg].controller = 1;
|
|
decoder->block[reg].base_reg = ide_dma_command_reg;
|
|
DTRACE(ide, ("controller %d dma register block at %d:0x%lx..0x%lx\n",
|
|
decoder->block[reg].controller,
|
|
decoder->block[reg-1].space,
|
|
(unsigned long)decoder->block[reg].base_addr,
|
|
(unsigned long)decoder->block[reg].bound_addr));
|
|
break;
|
|
default:
|
|
device_error(me, "internal error - bad switch");
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
|
|
typedef struct _hw_ide_device {
|
|
ide_controller controller[nr_ide_controllers];
|
|
address_decoder decoder;
|
|
} hw_ide_device;
|
|
|
|
|
|
static void
|
|
hw_ide_init_address(device *me)
|
|
{
|
|
hw_ide_device *ide = device_data(me);
|
|
int controller;
|
|
int drive;
|
|
|
|
/* zero some things */
|
|
for (controller = 0; controller < nr_ide_controllers; controller++) {
|
|
memset(&ide->controller[controller], 0, sizeof(ide_controller));
|
|
for (drive = 0; drive < nr_ide_drives_per_controller; drive++) {
|
|
ide->controller[controller].drive[drive].nr = drive;
|
|
}
|
|
ide->controller[controller].me = me;
|
|
if (device_find_property(me, "ready-delay") != NULL)
|
|
ide->controller[controller].ready_delay =
|
|
device_find_integer_property(me, "ready-delay");
|
|
}
|
|
|
|
/* attach this device to its parent */
|
|
generic_device_init_address(me);
|
|
|
|
/* determine our own address map */
|
|
build_address_decoder(me, &ide->decoder);
|
|
|
|
}
|
|
|
|
|
|
static void
|
|
hw_ide_attach_address(device *me,
|
|
attach_type type,
|
|
int space,
|
|
unsigned_word addr,
|
|
unsigned nr_bytes,
|
|
access_type access,
|
|
device *client) /*callback/default*/
|
|
{
|
|
hw_ide_device *ide = (hw_ide_device*)device_data(me);
|
|
int controller_nr = addr / nr_ide_drives_per_controller;
|
|
int drive_nr = addr % nr_ide_drives_per_controller;
|
|
ide_controller *controller;
|
|
ide_drive *drive;
|
|
if (controller_nr >= nr_ide_controllers)
|
|
device_error(me, "no controller for disk %s",
|
|
device_path(client));
|
|
|
|
controller = &ide->controller[controller_nr];
|
|
drive = &controller->drive[drive_nr];
|
|
drive->device = client;
|
|
if (device_find_property(client, "ide-byte-count") != NULL)
|
|
drive->geometry.byte = device_find_integer_property(client, "ide-byte-count");
|
|
else
|
|
drive->geometry.byte = 512;
|
|
if (device_find_property(client, "ide-sector-count") != NULL)
|
|
drive->geometry.sector = device_find_integer_property(client, "ide-sector-count");
|
|
if (device_find_property(client, "ide-head-count") != NULL)
|
|
drive->geometry.head = device_find_integer_property(client, "ide-head-count");
|
|
drive->default_geometry = drive->geometry;
|
|
DTRACE(ide, ("controller %d:%d %s byte-count %d, sector-count %d, head-count %d\n",
|
|
controller_nr,
|
|
drive->nr,
|
|
device_path(client),
|
|
drive->geometry.byte,
|
|
drive->geometry.sector,
|
|
drive->geometry.head));
|
|
}
|
|
|
|
|
|
static unsigned
|
|
hw_ide_io_read_buffer(device *me,
|
|
void *dest,
|
|
int space,
|
|
unsigned_word addr,
|
|
unsigned nr_bytes,
|
|
cpu *processor,
|
|
unsigned_word cia)
|
|
{
|
|
hw_ide_device *ide = (hw_ide_device *)device_data(me);
|
|
int control_nr;
|
|
int reg;
|
|
ide_controller *controller;
|
|
|
|
/* find the interface */
|
|
decode_address(me, &ide->decoder, space, addr, &control_nr, ®, is_read);
|
|
controller = & ide->controller[control_nr];
|
|
|
|
/* process the transfer */
|
|
memset(dest, 0, nr_bytes);
|
|
switch (reg) {
|
|
case ide_data_reg:
|
|
do_fifo_read(me, controller, dest, nr_bytes);
|
|
break;
|
|
case ide_status_reg:
|
|
*(unsigned8*)dest = get_status(me, controller);
|
|
clear_interrupt(me, controller);
|
|
break;
|
|
case ide_alternate_status_reg:
|
|
*(unsigned8*)dest = get_status(me, controller);
|
|
break;
|
|
case ide_error_reg:
|
|
case ide_sector_count_reg:
|
|
case ide_sector_number_reg:
|
|
case ide_cylinder_reg0:
|
|
case ide_cylinder_reg1:
|
|
case ide_drive_head_reg:
|
|
case ide_control_reg:
|
|
case ide_dma_command_reg:
|
|
case ide_dma_status_reg:
|
|
case ide_dma_prd_table_address_reg0:
|
|
case ide_dma_prd_table_address_reg1:
|
|
case ide_dma_prd_table_address_reg2:
|
|
case ide_dma_prd_table_address_reg3:
|
|
*(unsigned8*)dest = controller->reg[reg];
|
|
break;
|
|
default:
|
|
device_error(me, "bus-error at address 0x%lx", addr);
|
|
break;
|
|
}
|
|
return nr_bytes;
|
|
}
|
|
|
|
|
|
static unsigned
|
|
hw_ide_io_write_buffer(device *me,
|
|
const void *source,
|
|
int space,
|
|
unsigned_word addr,
|
|
unsigned nr_bytes,
|
|
cpu *processor,
|
|
unsigned_word cia)
|
|
{
|
|
hw_ide_device *ide = (hw_ide_device *)device_data(me);
|
|
int control_nr;
|
|
int reg;
|
|
ide_controller *controller;
|
|
|
|
/* find the interface */
|
|
decode_address(me, &ide->decoder, space, addr, &control_nr, ®, is_write);
|
|
controller = &ide->controller[control_nr];
|
|
|
|
/* process the access */
|
|
switch (reg) {
|
|
case ide_data_reg:
|
|
do_fifo_write(me, controller, source, nr_bytes);
|
|
break;
|
|
case ide_command_reg:
|
|
do_command(me, controller, *(unsigned8*)source);
|
|
break;
|
|
case ide_control_reg:
|
|
controller->reg[reg] = *(unsigned8*)source;
|
|
/* possibly cancel interrupts */
|
|
if ((controller->reg[reg] & 0x02) == 0x02)
|
|
clear_interrupt(me, controller);
|
|
break;
|
|
case ide_feature_reg:
|
|
case ide_sector_count_reg:
|
|
case ide_sector_number_reg:
|
|
case ide_cylinder_reg0:
|
|
case ide_cylinder_reg1:
|
|
case ide_drive_head_reg:
|
|
case ide_dma_command_reg:
|
|
case ide_dma_status_reg:
|
|
case ide_dma_prd_table_address_reg0:
|
|
case ide_dma_prd_table_address_reg1:
|
|
case ide_dma_prd_table_address_reg2:
|
|
case ide_dma_prd_table_address_reg3:
|
|
controller->reg[reg] = *(unsigned8*)source;
|
|
break;
|
|
default:
|
|
device_error(me, "bus-error at 0x%lx", addr);
|
|
break;
|
|
}
|
|
return nr_bytes;
|
|
}
|
|
|
|
|
|
static const device_interrupt_port_descriptor hw_ide_interrupt_ports[] = {
|
|
{ "a", 0, 0 },
|
|
{ "b", 1, 0 },
|
|
{ "c", 2, 0 },
|
|
{ "d", 3, 0 },
|
|
{ NULL }
|
|
};
|
|
|
|
|
|
|
|
static device_callbacks const hw_ide_callbacks = {
|
|
{ hw_ide_init_address, },
|
|
{ hw_ide_attach_address, }, /* attach */
|
|
{ hw_ide_io_read_buffer, hw_ide_io_write_buffer, },
|
|
{ NULL, }, /* DMA */
|
|
{ NULL, NULL, hw_ide_interrupt_ports }, /* interrupt */
|
|
{ generic_device_unit_decode,
|
|
generic_device_unit_encode,
|
|
generic_device_address_to_attach_address,
|
|
generic_device_size_to_attach_size },
|
|
};
|
|
|
|
|
|
static void *
|
|
hw_ide_create(const char *name,
|
|
const device_unit *unit_address,
|
|
const char *args)
|
|
{
|
|
hw_ide_device *ide = ZALLOC(hw_ide_device);
|
|
return ide;
|
|
}
|
|
|
|
|
|
const device_descriptor hw_ide_device_descriptor[] = {
|
|
{ "ide", hw_ide_create, &hw_ide_callbacks },
|
|
{ NULL, },
|
|
};
|
|
|
|
#endif /* _HW_IDE_ */
|