560 lines
17 KiB
C
560 lines
17 KiB
C
/* Copyright (C) 2009-2015 Free Software Foundation, Inc.
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Contributed by ARM Ltd.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#include "common-defs.h"
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#include "break-common.h"
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#include "aarch64-linux-hw-point.h"
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#include <sys/uio.h>
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#include <asm/ptrace.h>
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#include <sys/ptrace.h>
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#include <elf.h>
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/* Number of hardware breakpoints/watchpoints the target supports.
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They are initialized with values obtained via the ptrace calls
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with NT_ARM_HW_BREAK and NT_ARM_HW_WATCH respectively. */
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int aarch64_num_bp_regs;
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int aarch64_num_wp_regs;
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/* Utility function that returns the length in bytes of a watchpoint
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according to the content of a hardware debug control register CTRL.
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Note that the kernel currently only supports the following Byte
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Address Select (BAS) values: 0x1, 0x3, 0xf and 0xff, which means
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that for a hardware watchpoint, its valid length can only be 1
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byte, 2 bytes, 4 bytes or 8 bytes. */
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unsigned int
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aarch64_watchpoint_length (unsigned int ctrl)
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{
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switch (DR_CONTROL_LENGTH (ctrl))
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{
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case 0x01:
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return 1;
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case 0x03:
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return 2;
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case 0x0f:
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return 4;
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case 0xff:
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return 8;
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default:
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return 0;
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}
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}
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/* Given the hardware breakpoint or watchpoint type TYPE and its
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length LEN, return the expected encoding for a hardware
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breakpoint/watchpoint control register. */
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static unsigned int
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aarch64_point_encode_ctrl_reg (enum target_hw_bp_type type, int len)
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{
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unsigned int ctrl, ttype;
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/* type */
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switch (type)
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{
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case hw_write:
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ttype = 2;
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break;
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case hw_read:
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ttype = 1;
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break;
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case hw_access:
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ttype = 3;
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break;
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case hw_execute:
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ttype = 0;
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break;
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default:
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perror_with_name (_("Unrecognized breakpoint/watchpoint type"));
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}
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ctrl = ttype << 3;
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/* length bitmask */
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ctrl |= ((1 << len) - 1) << 5;
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/* enabled at el0 */
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ctrl |= (2 << 1) | 1;
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return ctrl;
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}
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/* Addresses to be written to the hardware breakpoint and watchpoint
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value registers need to be aligned; the alignment is 4-byte and
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8-type respectively. Linux kernel rejects any non-aligned address
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it receives from the related ptrace call. Furthermore, the kernel
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currently only supports the following Byte Address Select (BAS)
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values: 0x1, 0x3, 0xf and 0xff, which means that for a hardware
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watchpoint to be accepted by the kernel (via ptrace call), its
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valid length can only be 1 byte, 2 bytes, 4 bytes or 8 bytes.
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Despite these limitations, the unaligned watchpoint is supported in
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this port.
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Return 0 for any non-compliant ADDR and/or LEN; return 1 otherwise. */
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static int
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aarch64_point_is_aligned (int is_watchpoint, CORE_ADDR addr, int len)
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{
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unsigned int alignment = is_watchpoint ? AARCH64_HWP_ALIGNMENT
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: AARCH64_HBP_ALIGNMENT;
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if (addr & (alignment - 1))
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return 0;
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if (len != 8 && len != 4 && len != 2 && len != 1)
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return 0;
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return 1;
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}
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/* Given the (potentially unaligned) watchpoint address in ADDR and
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length in LEN, return the aligned address and aligned length in
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*ALIGNED_ADDR_P and *ALIGNED_LEN_P, respectively. The returned
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aligned address and length will be valid values to write to the
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hardware watchpoint value and control registers.
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The given watchpoint may get truncated if more than one hardware
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register is needed to cover the watched region. *NEXT_ADDR_P
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and *NEXT_LEN_P, if non-NULL, will return the address and length
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of the remaining part of the watchpoint (which can be processed
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by calling this routine again to generate another aligned address
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and length pair.
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Essentially, unaligned watchpoint is achieved by minimally
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enlarging the watched area to meet the alignment requirement, and
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if necessary, splitting the watchpoint over several hardware
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watchpoint registers. The trade-off is that there will be
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false-positive hits for the read-type or the access-type hardware
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watchpoints; for the write type, which is more commonly used, there
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will be no such issues, as the higher-level breakpoint management
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in gdb always examines the exact watched region for any content
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change, and transparently resumes a thread from a watchpoint trap
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if there is no change to the watched region.
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Another limitation is that because the watched region is enlarged,
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the watchpoint fault address returned by
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aarch64_stopped_data_address may be outside of the original watched
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region, especially when the triggering instruction is accessing a
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larger region. When the fault address is not within any known
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range, watchpoints_triggered in gdb will get confused, as the
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higher-level watchpoint management is only aware of original
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watched regions, and will think that some unknown watchpoint has
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been triggered. In such a case, gdb may stop without displaying
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any detailed information.
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Once the kernel provides the full support for Byte Address Select
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(BAS) in the hardware watchpoint control register, these
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limitations can be largely relaxed with some further work. */
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static void
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aarch64_align_watchpoint (CORE_ADDR addr, int len, CORE_ADDR *aligned_addr_p,
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int *aligned_len_p, CORE_ADDR *next_addr_p,
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int *next_len_p)
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{
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int aligned_len;
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unsigned int offset;
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CORE_ADDR aligned_addr;
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const unsigned int alignment = AARCH64_HWP_ALIGNMENT;
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const unsigned int max_wp_len = AARCH64_HWP_MAX_LEN_PER_REG;
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/* As assumed by the algorithm. */
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gdb_assert (alignment == max_wp_len);
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if (len <= 0)
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return;
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/* Address to be put into the hardware watchpoint value register
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must be aligned. */
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offset = addr & (alignment - 1);
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aligned_addr = addr - offset;
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gdb_assert (offset >= 0 && offset < alignment);
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gdb_assert (aligned_addr >= 0 && aligned_addr <= addr);
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gdb_assert (offset + len > 0);
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if (offset + len >= max_wp_len)
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{
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/* Need more than one watchpoint registers; truncate it at the
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alignment boundary. */
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aligned_len = max_wp_len;
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len -= (max_wp_len - offset);
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addr += (max_wp_len - offset);
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gdb_assert ((addr & (alignment - 1)) == 0);
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}
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else
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{
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/* Find the smallest valid length that is large enough to
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accommodate this watchpoint. */
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static const unsigned char
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aligned_len_array[AARCH64_HWP_MAX_LEN_PER_REG] =
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{ 1, 2, 4, 4, 8, 8, 8, 8 };
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aligned_len = aligned_len_array[offset + len - 1];
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addr += len;
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len = 0;
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}
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if (aligned_addr_p)
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*aligned_addr_p = aligned_addr;
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if (aligned_len_p)
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*aligned_len_p = aligned_len;
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if (next_addr_p)
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*next_addr_p = addr;
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if (next_len_p)
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*next_len_p = len;
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}
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/* Record the insertion of one breakpoint/watchpoint, as represented
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by ADDR and CTRL, in the process' arch-specific data area *STATE. */
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static int
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aarch64_dr_state_insert_one_point (struct aarch64_debug_reg_state *state,
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enum target_hw_bp_type type,
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CORE_ADDR addr, int len)
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{
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int i, idx, num_regs, is_watchpoint;
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unsigned int ctrl, *dr_ctrl_p, *dr_ref_count;
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CORE_ADDR *dr_addr_p;
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/* Set up state pointers. */
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is_watchpoint = (type != hw_execute);
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gdb_assert (aarch64_point_is_aligned (is_watchpoint, addr, len));
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if (is_watchpoint)
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{
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num_regs = aarch64_num_wp_regs;
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dr_addr_p = state->dr_addr_wp;
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dr_ctrl_p = state->dr_ctrl_wp;
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dr_ref_count = state->dr_ref_count_wp;
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}
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else
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{
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num_regs = aarch64_num_bp_regs;
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dr_addr_p = state->dr_addr_bp;
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dr_ctrl_p = state->dr_ctrl_bp;
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dr_ref_count = state->dr_ref_count_bp;
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}
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ctrl = aarch64_point_encode_ctrl_reg (type, len);
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/* Find an existing or free register in our cache. */
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idx = -1;
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for (i = 0; i < num_regs; ++i)
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{
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if ((dr_ctrl_p[i] & 1) == 0)
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{
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gdb_assert (dr_ref_count[i] == 0);
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idx = i;
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/* no break; continue hunting for an exising one. */
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}
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else if (dr_addr_p[i] == addr && dr_ctrl_p[i] == ctrl)
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{
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gdb_assert (dr_ref_count[i] != 0);
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idx = i;
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break;
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}
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}
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/* No space. */
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if (idx == -1)
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return -1;
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/* Update our cache. */
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if ((dr_ctrl_p[idx] & 1) == 0)
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{
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/* new entry */
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dr_addr_p[idx] = addr;
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dr_ctrl_p[idx] = ctrl;
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dr_ref_count[idx] = 1;
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/* Notify the change. */
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aarch64_notify_debug_reg_change (state, is_watchpoint, idx);
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}
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else
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{
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/* existing entry */
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dr_ref_count[idx]++;
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}
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return 0;
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}
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/* Record the removal of one breakpoint/watchpoint, as represented by
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ADDR and CTRL, in the process' arch-specific data area *STATE. */
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static int
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aarch64_dr_state_remove_one_point (struct aarch64_debug_reg_state *state,
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enum target_hw_bp_type type,
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CORE_ADDR addr, int len)
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{
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int i, num_regs, is_watchpoint;
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unsigned int ctrl, *dr_ctrl_p, *dr_ref_count;
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CORE_ADDR *dr_addr_p;
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/* Set up state pointers. */
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is_watchpoint = (type != hw_execute);
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gdb_assert (aarch64_point_is_aligned (is_watchpoint, addr, len));
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if (is_watchpoint)
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{
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num_regs = aarch64_num_wp_regs;
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dr_addr_p = state->dr_addr_wp;
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dr_ctrl_p = state->dr_ctrl_wp;
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dr_ref_count = state->dr_ref_count_wp;
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}
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else
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{
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num_regs = aarch64_num_bp_regs;
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dr_addr_p = state->dr_addr_bp;
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dr_ctrl_p = state->dr_ctrl_bp;
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dr_ref_count = state->dr_ref_count_bp;
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}
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ctrl = aarch64_point_encode_ctrl_reg (type, len);
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/* Find the entry that matches the ADDR and CTRL. */
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for (i = 0; i < num_regs; ++i)
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if (dr_addr_p[i] == addr && dr_ctrl_p[i] == ctrl)
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{
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gdb_assert (dr_ref_count[i] != 0);
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break;
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}
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/* Not found. */
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if (i == num_regs)
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return -1;
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/* Clear our cache. */
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if (--dr_ref_count[i] == 0)
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{
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/* Clear the enable bit. */
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ctrl &= ~1;
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dr_addr_p[i] = 0;
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dr_ctrl_p[i] = ctrl;
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/* Notify the change. */
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aarch64_notify_debug_reg_change (state, is_watchpoint, i);
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}
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return 0;
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}
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int
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aarch64_handle_breakpoint (enum target_hw_bp_type type, CORE_ADDR addr,
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int len, int is_insert,
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struct aarch64_debug_reg_state *state)
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{
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/* The hardware breakpoint on AArch64 should always be 4-byte
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aligned. */
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if (!aarch64_point_is_aligned (0 /* is_watchpoint */ , addr, len))
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return -1;
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if (is_insert)
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return aarch64_dr_state_insert_one_point (state, type, addr, len);
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else
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return aarch64_dr_state_remove_one_point (state, type, addr, len);
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}
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/* This is essentially the same as aarch64_handle_breakpoint, apart
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from that it is an aligned watchpoint to be handled. */
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static int
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aarch64_handle_aligned_watchpoint (enum target_hw_bp_type type,
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CORE_ADDR addr, int len, int is_insert,
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struct aarch64_debug_reg_state *state)
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{
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if (is_insert)
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return aarch64_dr_state_insert_one_point (state, type, addr, len);
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else
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return aarch64_dr_state_remove_one_point (state, type, addr, len);
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}
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/* Insert/remove unaligned watchpoint by calling
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aarch64_align_watchpoint repeatedly until the whole watched region,
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as represented by ADDR and LEN, has been properly aligned and ready
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to be written to one or more hardware watchpoint registers.
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IS_INSERT indicates whether this is an insertion or a deletion.
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Return 0 if succeed. */
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static int
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aarch64_handle_unaligned_watchpoint (enum target_hw_bp_type type,
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CORE_ADDR addr, int len, int is_insert,
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struct aarch64_debug_reg_state *state)
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{
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while (len > 0)
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{
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CORE_ADDR aligned_addr;
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int aligned_len, ret;
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aarch64_align_watchpoint (addr, len, &aligned_addr, &aligned_len,
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&addr, &len);
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if (is_insert)
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ret = aarch64_dr_state_insert_one_point (state, type, aligned_addr,
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aligned_len);
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else
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ret = aarch64_dr_state_remove_one_point (state, type, aligned_addr,
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aligned_len);
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if (show_debug_regs)
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debug_printf ("handle_unaligned_watchpoint: is_insert: %d\n"
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" "
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"aligned_addr: %s, aligned_len: %d\n"
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" "
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"next_addr: %s, next_len: %d\n",
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is_insert, core_addr_to_string_nz (aligned_addr),
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aligned_len, core_addr_to_string_nz (addr), len);
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if (ret != 0)
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return ret;
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}
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return 0;
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}
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int
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aarch64_handle_watchpoint (enum target_hw_bp_type type, CORE_ADDR addr,
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int len, int is_insert,
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struct aarch64_debug_reg_state *state)
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{
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if (aarch64_point_is_aligned (1 /* is_watchpoint */ , addr, len))
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return aarch64_handle_aligned_watchpoint (type, addr, len, is_insert,
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state);
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else
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return aarch64_handle_unaligned_watchpoint (type, addr, len, is_insert,
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state);
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}
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/* Call ptrace to set the thread TID's hardware breakpoint/watchpoint
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registers with data from *STATE. */
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void
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aarch64_linux_set_debug_regs (const struct aarch64_debug_reg_state *state,
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int tid, int watchpoint)
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{
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int i, count;
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struct iovec iov;
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struct user_hwdebug_state regs;
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const CORE_ADDR *addr;
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const unsigned int *ctrl;
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memset (®s, 0, sizeof (regs));
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iov.iov_base = ®s;
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count = watchpoint ? aarch64_num_wp_regs : aarch64_num_bp_regs;
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addr = watchpoint ? state->dr_addr_wp : state->dr_addr_bp;
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ctrl = watchpoint ? state->dr_ctrl_wp : state->dr_ctrl_bp;
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if (count == 0)
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return;
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iov.iov_len = (offsetof (struct user_hwdebug_state, dbg_regs[count - 1])
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+ sizeof (regs.dbg_regs [count - 1]));
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for (i = 0; i < count; i++)
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{
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regs.dbg_regs[i].addr = addr[i];
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regs.dbg_regs[i].ctrl = ctrl[i];
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}
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if (ptrace (PTRACE_SETREGSET, tid,
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watchpoint ? NT_ARM_HW_WATCH : NT_ARM_HW_BREAK,
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(void *) &iov))
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error (_("Unexpected error setting hardware debug registers"));
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}
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/* Print the values of the cached breakpoint/watchpoint registers. */
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void
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aarch64_show_debug_reg_state (struct aarch64_debug_reg_state *state,
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const char *func, CORE_ADDR addr,
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int len, enum target_hw_bp_type type)
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{
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int i;
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debug_printf ("%s", func);
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if (addr || len)
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debug_printf (" (addr=0x%08lx, len=%d, type=%s)",
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(unsigned long) addr, len,
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type == hw_write ? "hw-write-watchpoint"
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: (type == hw_read ? "hw-read-watchpoint"
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: (type == hw_access ? "hw-access-watchpoint"
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: (type == hw_execute ? "hw-breakpoint"
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: "??unknown??"))));
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debug_printf (":\n");
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debug_printf ("\tBREAKPOINTs:\n");
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for (i = 0; i < aarch64_num_bp_regs; i++)
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debug_printf ("\tBP%d: addr=%s, ctrl=0x%08x, ref.count=%d\n",
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i, core_addr_to_string_nz (state->dr_addr_bp[i]),
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state->dr_ctrl_bp[i], state->dr_ref_count_bp[i]);
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debug_printf ("\tWATCHPOINTs:\n");
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for (i = 0; i < aarch64_num_wp_regs; i++)
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debug_printf ("\tWP%d: addr=%s, ctrl=0x%08x, ref.count=%d\n",
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i, core_addr_to_string_nz (state->dr_addr_wp[i]),
|
|
state->dr_ctrl_wp[i], state->dr_ref_count_wp[i]);
|
|
}
|
|
|
|
/* Get the hardware debug register capacity information from the
|
|
process represented by TID. */
|
|
|
|
void
|
|
aarch64_linux_get_debug_reg_capacity (int tid)
|
|
{
|
|
struct iovec iov;
|
|
struct user_hwdebug_state dreg_state;
|
|
|
|
iov.iov_base = &dreg_state;
|
|
iov.iov_len = sizeof (dreg_state);
|
|
|
|
/* Get hardware watchpoint register info. */
|
|
if (ptrace (PTRACE_GETREGSET, tid, NT_ARM_HW_WATCH, &iov) == 0
|
|
&& AARCH64_DEBUG_ARCH (dreg_state.dbg_info) == AARCH64_DEBUG_ARCH_V8)
|
|
{
|
|
aarch64_num_wp_regs = AARCH64_DEBUG_NUM_SLOTS (dreg_state.dbg_info);
|
|
if (aarch64_num_wp_regs > AARCH64_HWP_MAX_NUM)
|
|
{
|
|
warning (_("Unexpected number of hardware watchpoint registers"
|
|
" reported by ptrace, got %d, expected %d."),
|
|
aarch64_num_wp_regs, AARCH64_HWP_MAX_NUM);
|
|
aarch64_num_wp_regs = AARCH64_HWP_MAX_NUM;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
warning (_("Unable to determine the number of hardware watchpoints"
|
|
" available."));
|
|
aarch64_num_wp_regs = 0;
|
|
}
|
|
|
|
/* Get hardware breakpoint register info. */
|
|
if (ptrace (PTRACE_GETREGSET, tid, NT_ARM_HW_BREAK, &iov) == 0
|
|
&& AARCH64_DEBUG_ARCH (dreg_state.dbg_info) == AARCH64_DEBUG_ARCH_V8)
|
|
{
|
|
aarch64_num_bp_regs = AARCH64_DEBUG_NUM_SLOTS (dreg_state.dbg_info);
|
|
if (aarch64_num_bp_regs > AARCH64_HBP_MAX_NUM)
|
|
{
|
|
warning (_("Unexpected number of hardware breakpoint registers"
|
|
" reported by ptrace, got %d, expected %d."),
|
|
aarch64_num_bp_regs, AARCH64_HBP_MAX_NUM);
|
|
aarch64_num_bp_regs = AARCH64_HBP_MAX_NUM;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
warning (_("Unable to determine the number of hardware breakpoints"
|
|
" available."));
|
|
aarch64_num_bp_regs = 0;
|
|
}
|
|
}
|