62adc51030
PPC_OPCODE_440 being set for ppc476 meant that many opcodes needed to be deprecated for ppc476. There are far fewer to add specially for ppc476 if PPC_OPCODE_440 is not set for ppc476. * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440. * ppc-opc.c (MULHW): Add PPC_OPCODE_476. (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit removal of PPC_OPCODE_440 from ppc476 cpu selection bits.
517 lines
17 KiB
Plaintext
517 lines
17 KiB
Plaintext
2017-04-10 Alan Modra <amodra@gmail.com>
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* ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440.
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* ppc-opc.c (MULHW): Add PPC_OPCODE_476.
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(powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit
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removal of PPC_OPCODE_440 from ppc476 cpu selection bits.
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2017-04-09 Pip Cet <pipcet@gmail.com>
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* wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify
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appropriate floating-point precision directly.
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2017-04-07 Alan Modra <amodra@gmail.com>
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* ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
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lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
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lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
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lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
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vector instructions with E6500 not PPCVEC2.
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2017-04-06 Pip Cet <pipcet@gmail.com>
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* Makefile.am: Add wasm32-dis.c.
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* configure.ac: Add wasm32-dis.c to wasm32 target.
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* disassemble.c: Add wasm32 disassembler code.
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* wasm32-dis.c: New file.
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* Makefile.in: Regenerate.
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* configure: Regenerate.
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* po/POTFILES.in: Regenerate.
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* po/opcodes.pot: Regenerate.
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2017-04-05 Pedro Alves <palves@redhat.com>
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* arc-dis.c (parse_option, parse_disassembler_options): Constify.
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* arm-dis.c (parse_arm_disassembler_options): Constify.
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* ppc-dis.c (powerpc_init_dialect): Constify local.
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* vax-dis.c (parse_disassembler_options): Constify.
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2017-04-03 Palmer Dabbelt <palmer@dabbelt.com>
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* riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
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RISCV_GP_SYMBOL.
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2017-03-30 Pip Cet <pipcet@gmail.com>
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* configure.ac: Add (empty) bfd_wasm32_arch target.
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* configure: Regenerate
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* po/opcodes.pot: Regenerate.
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2017-03-29 Sheldon Lobo <sheldon.lobo@oracle.com>
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Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
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OSA2015.
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* opcodes/sparc-opc.c (asi_table): New ASIs.
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2017-03-29 Alan Modra <amodra@gmail.com>
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* ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags. Add
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"raw" option.
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(lookup_powerpc): Don't special case -1 dialect. Handle
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PPC_OPCODE_RAW.
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(print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
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lookup_powerpc call, pass it on second.
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2017-03-27 Alan Modra <amodra@gmail.com>
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PR 21303
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* ppc-dis.c (struct ppc_mopt): Comment.
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(ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
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2017-03-27 Rinat Zelig <rinat@mellanox.com>
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* arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
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* arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
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F_NPS_M, F_NPS_CORE, F_NPS_ALL.
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(insert_nps_misc_imm_offset): New function.
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(extract_nps_misc imm_offset): New function.
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(arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
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(arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
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2017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
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* s390-mkopc.c (main): Remove vx2 check.
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* s390-opc.txt: Remove vx2 instruction flags.
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2017-03-21 Rinat Zelig <rinat@mellanox.com>
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* arc-nps400-tbl.h: Add cp32/cp16 instructions format.
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* arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
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(insert_nps_imm_offset): New function.
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(extract_nps_imm_offset): New function.
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(insert_nps_imm_entry): New function.
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(extract_nps_imm_entry): New function.
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2017-03-17 Alan Modra <amodra@gmail.com>
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PR 21248
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* ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
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mtivor32, and mtivor33 for e6500. Move mfibatl and mfibatu after
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those spr mnemonics they alias. Similarly for mtibatl, mtibatu.
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2017-03-14 Kito Cheng <kito.cheng@gmail.com>
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* riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
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<c.andi>: Likewise.
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<c.addiw> Likewise.
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2017-03-14 Kito Cheng <kito.cheng@gmail.com>
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* riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
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2017-03-13 Andrew Waterman <andrew@sifive.com>
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* riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
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<srl> Likewise.
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<srai> Likewise.
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<sra> Likewise.
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2017-03-09 H.J. Lu <hongjiu.lu@intel.com>
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* i386-gen.c (opcode_modifiers): Replace S with Load.
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* i386-opc.h (S): Removed.
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(Load): New.
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(i386_opcode_modifier): Replace s with load.
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* i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
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and {evex}. Replace S with Load.
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* i386-tbl.h: Regenerated.
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2017-03-09 H.J. Lu <hongjiu.lu@intel.com>
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* i386-opc.tbl: Use CpuCET on rdsspq.
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* i386-tbl.h: Regenerated.
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2017-03-08 Peter Bergner <bergner@vnet.ibm.com>
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* ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
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<vsx>: Do not use PPC_OPCODE_VSX3;
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2017-03-08 Peter Bergner <bergner@vnet.ibm.com>
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* ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
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2017-03-06 H.J. Lu <hongjiu.lu@intel.com>
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* i386-dis.c (REG_0F1E_MOD_3): New enum.
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(MOD_0F1E_PREFIX_1): Likewise.
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(MOD_0F38F5_PREFIX_2): Likewise.
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(MOD_0F38F6_PREFIX_0): Likewise.
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(RM_0F1E_MOD_3_REG_7): Likewise.
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(PREFIX_MOD_0_0F01_REG_5): Likewise.
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(PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
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(PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
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(PREFIX_0F1E): Likewise.
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(PREFIX_MOD_0_0FAE_REG_5): Likewise.
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(PREFIX_0F38F5): Likewise.
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(dis386_twobyte): Use PREFIX_0F1E.
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(reg_table): Add REG_0F1E_MOD_3.
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(prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
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PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
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PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5. Update
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PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
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(three_byte_table): Use PREFIX_0F38F5.
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(mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
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Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
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(rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
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RM_0F1E_MOD_3_REG_7. Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
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PREFIX_MOD_3_0F01_REG_5_RM_2.
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* i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
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(cpu_flags): Add CpuCET.
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* i386-opc.h (CpuCET): New enum.
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(CpuUnused): Commented out.
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(i386_cpu_flags): Add cpucet.
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* i386-opc.tbl: Add Intel CET instructions.
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* i386-init.h: Regenerated.
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* i386-tbl.h: Likewise.
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2017-03-06 Alan Modra <amodra@gmail.com>
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PR 21124
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* ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
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(extract_raq, extract_ras, extract_rbx): New functions.
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(powerpc_operands): Use opposite corresponding insert function.
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(Q_MASK): Define.
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(powerpc_opcodes): Apply Q_MASK to all quad insns with even
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register restriction.
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2017-02-28 Peter Bergner <bergner@vnet.ibm.com>
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* disassemble.c Include "safe-ctype.h".
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(disassemble_init_for_target): Handle s390 init.
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(remove_whitespace_and_extra_commas): New function.
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(disassembler_options_cmp): Likewise.
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* arm-dis.c: Include "libiberty.h".
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(NUM_ELEM): Delete.
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(regnames): Use long disassembler style names.
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Add force-thumb and no-force-thumb options.
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(NUM_ARM_REGNAMES): Rename from this...
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(NUM_ARM_OPTIONS): ...to this. Use ARRAY_SIZE.
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(get_arm_regname_num_options): Delete.
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(set_arm_regname_option): Likewise.
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(get_arm_regnames): Likewise.
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(parse_disassembler_options): Likewise.
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(parse_arm_disassembler_option): Rename from this...
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(parse_arm_disassembler_options): ...to this. Make static.
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Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
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(print_insn): Use parse_arm_disassembler_options.
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(disassembler_options_arm): New function.
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(print_arm_disassembler_options): Handle updated regnames.
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* ppc-dis.c: Include "libiberty.h".
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(ppc_opts): Add "32" and "64" entries.
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(ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
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(powerpc_init_dialect): Add break to switch statement.
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Use new FOR_EACH_DISASSEMBLER_OPTION macro.
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(disassembler_options_powerpc): New function.
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(print_ppc_disassembler_options): Use ARRAY_SIZE.
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Remove printing of "32" and "64".
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* s390-dis.c: Include "libiberty.h".
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(init_flag): Remove unneeded variable.
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(struct s390_options_t): New structure type.
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(options): New structure.
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(init_disasm): Rename from this...
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(disassemble_init_s390): ...to this. Add initializations for
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current_arch_mask and option_use_insn_len_bits_p. Remove init_flag.
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(print_insn_s390): Delete call to init_disasm.
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(disassembler_options_s390): New function.
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(print_s390_disassembler_options): Print using information from
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struct 'options'.
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* po/opcodes.pot: Regenerate.
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2017-02-28 Jan Beulich <jbeulich@suse.com>
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* i386-dis.c (PCMPESTR_Fixup): New.
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(VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
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(prefix_table): Use PCMPESTR_Fixup.
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(vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
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PCMPESTR_Fixup.
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(vex_w_table): Delete VPCMPESTR{I,M} entries.
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* i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
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Split 64-bit and non-64-bit variants.
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* opcodes/i386-tbl.h: Re-generate.
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2017-02-24 Richard Sandiford <richard.sandiford@arm.com>
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* aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
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(OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
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(OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
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(OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
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(OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
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(OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
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(OP_SVE_V_HSD): New macros.
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(OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
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(OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
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(OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
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(aarch64_opcode_table): Add new SVE instructions.
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(aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
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for rotation operands. Add new SVE operands.
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* aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
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(ins_sve_quad_index): Likewise.
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(ins_imm_rotate): Split into...
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(ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
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* aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
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(aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
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functions.
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(aarch64_ins_sve_addr_ri_s4): New function.
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(aarch64_ins_sve_quad_index): Likewise.
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(do_misc_encoding): Handle "MOV Zn.Q, Qm".
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* aarch64-asm-2.c: Regenerate.
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* aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
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(ext_sve_quad_index): Likewise.
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(ext_imm_rotate): Split into...
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(ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
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* aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
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(aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
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functions.
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(aarch64_ext_sve_addr_ri_s4): New function.
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(aarch64_ext_sve_quad_index): Likewise.
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(aarch64_ext_sve_index): Allow quad indices.
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(do_misc_decoding): Likewise.
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* aarch64-dis-2.c: Regenerate.
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* aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
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aarch64_field_kinds.
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(OPD_F_OD_MASK): Widen by one bit.
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(OPD_F_NO_ZR): Bump accordingly.
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(get_operand_field_width): New function.
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* aarch64-opc.c (fields): Add new SVE fields.
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(operand_general_constraint_met_p): Handle new SVE operands.
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(aarch64_print_operand): Likewise.
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* aarch64-opc-2.c: Regenerate.
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||
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||
2017-02-24 Richard Sandiford <richard.sandiford@arm.com>
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* aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
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(aarch64_feature_compnum): ...this.
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(SIMD_V8_3): Replace with...
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(COMPNUM): ...this.
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||
(CNUM_INSN): New macro.
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||
(aarch64_opcode_table): Use it for the complex number instructions.
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||
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||
2017-02-24 Jan Beulich <jbeulich@suse.com>
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||
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||
* i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
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||
|
||
2017-02-23 Sheldon Lobo <sheldon.lobo@oracle.com>
|
||
|
||
Add support for associating SPARC ASIs with an architecture level.
|
||
* include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
|
||
* opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
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decoding of SPARC ASIs.
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||
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||
2017-02-23 Jan Beulich <jbeulich@suse.com>
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||
|
||
* i386-dis.c (get_valid_dis386): Don't special case VEX opcode
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||
82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
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||
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||
2017-02-21 Jan Beulich <jbeulich@suse.com>
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||
|
||
* aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
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||
1 (instead of to itself). Correct typo.
|
||
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||
2017-02-14 Andrew Waterman <andrew@sifive.com>
|
||
|
||
* riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
|
||
pseudoinstructions.
|
||
|
||
2017-02-15 Richard Sandiford <richard.sandiford@arm.com>
|
||
|
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* aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
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||
(aarch64_sys_reg_supported_p): Handle them.
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||
|
||
2017-02-15 Claudiu Zissulescu <claziss@synopsys.com>
|
||
|
||
* arc-opc.c (UIMM6_20R): Define.
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||
(SIMM12_20): Use above.
|
||
(SIMM12_20R): Define.
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||
(SIMM3_5_S): Use above.
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||
(UIMM7_A32_11R_S): Define.
|
||
(UIMM7_9_S): Use above.
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||
(UIMM3_13R_S): Define.
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||
(SIMM11_A32_7_S): Use above.
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||
(SIMM9_8R): Define.
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(UIMM10_A32_8_S): Use above.
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||
(UIMM8_8R_S): Define.
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(W6): Use above.
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(arc_relax_opcodes): Use all above defines.
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||
|
||
2017-02-15 Vineet Gupta <vgupta@synopsys.com>
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||
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* arc-regs.h: Distinguish some of the registers different on
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||
ARC700 and HS38 cpus.
|
||
|
||
2017-02-14 Alan Modra <amodra@gmail.com>
|
||
|
||
PR 21118
|
||
* ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
|
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with PPC_OPERAND_SPR. Flag PSQ and PSQM with PPC_OPERAND_GQR.
|
||
|
||
2017-02-11 Stafford Horne <shorne@gmail.com>
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Alan Modra <amodra@gmail.com>
|
||
|
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* cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
|
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Use insn_bytes_value and insn_int_value directly instead. Don't
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free allocated memory until function exit.
|
||
|
||
2017-02-10 Nicholas Piggin <npiggin@gmail.com>
|
||
|
||
* ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
|
||
|
||
2017-02-03 Nick Clifton <nickc@redhat.com>
|
||
|
||
PR 21096
|
||
* aarch64-opc.c (print_register_list): Ensure that the register
|
||
list index will fir into the tb buffer.
|
||
(print_register_offset_address): Likewise.
|
||
* tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
|
||
|
||
2017-01-27 Alexis Deruell <alexis.deruelle@gmail.com>
|
||
|
||
PR 21056
|
||
* tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
|
||
instructions when the previous fetch packet ends with a 32-bit
|
||
instruction.
|
||
|
||
2017-01-24 Dimitar Dimitrov <dimitar@dinux.eu>
|
||
|
||
* pru-opc.c: Remove vague reference to a future GDB port.
|
||
|
||
2017-01-20 Nick Clifton <nickc@redhat.com>
|
||
|
||
* po/ga.po: Updated Irish translation.
|
||
|
||
2017-01-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
|
||
|
||
* arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
|
||
|
||
2017-01-13 Yao Qi <yao.qi@linaro.org>
|
||
|
||
* m68k-dis.c (match_insn_m68k): Extend comments. Return -1
|
||
if FETCH_DATA returns 0.
|
||
(m68k_scan_mask): Likewise.
|
||
(print_insn_m68k): Update code to handle -1 return value.
|
||
|
||
2017-01-13 Yao Qi <yao.qi@linaro.org>
|
||
|
||
* m68k-dis.c (enum print_insn_arg_error): New.
|
||
(NEXTBYTE): Replace -3 with
|
||
PRINT_INSN_ARG_MEMORY_ERROR.
|
||
(NEXTULONG): Likewise.
|
||
(NEXTSINGLE): Likewise.
|
||
(NEXTDOUBLE): Likewise.
|
||
(NEXTDOUBLE): Likewise.
|
||
(NEXTPACKED): Likewise.
|
||
(FETCH_ARG): Likewise.
|
||
(FETCH_DATA): Update comments.
|
||
(print_insn_arg): Update comments. Replace magic numbers with
|
||
enum.
|
||
(match_insn_m68k): Likewise.
|
||
|
||
2017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
|
||
|
||
* i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
|
||
* i386-dis-evex.h (evex_table): Updated.
|
||
* i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
|
||
CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
|
||
(cpu_flags): Add CpuAVX512_VPOPCNTDQ.
|
||
* i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
|
||
(i386_cpu_flags): Add cpuavx512_vpopcntdq.
|
||
* i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
|
||
* i386-init.h: Regenerate.
|
||
* i386-tbl.h: Ditto.
|
||
|
||
2017-01-12 Yao Qi <yao.qi@linaro.org>
|
||
|
||
* msp430-dis.c (msp430_singleoperand): Return -1 if
|
||
msp430dis_opcode_signed returns false.
|
||
(msp430_doubleoperand): Likewise.
|
||
(msp430_branchinstr): Return -1 if
|
||
msp430dis_opcode_unsigned returns false.
|
||
(msp430x_calla_instr): Likewise.
|
||
(print_insn_msp430): Likewise.
|
||
|
||
2017-01-05 Nick Clifton <nickc@redhat.com>
|
||
|
||
PR 20946
|
||
* frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
|
||
could not be matched.
|
||
(frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
|
||
NULL.
|
||
|
||
2017-01-04 Szabolcs Nagy <szabolcs.nagy@arm.com>
|
||
|
||
* aarch64-tbl.h (RCPC, RCPC_INSN): Define.
|
||
(aarch64_opcode_table): Use RCPC_INSN.
|
||
|
||
2017-01-03 Kito Cheng <kito.cheng@gmail.com>
|
||
|
||
* riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
|
||
extension.
|
||
* riscv-opcodes/all-opcodes: Likewise.
|
||
|
||
2017-01-03 Dilyan Palauzov <dilyan.palauzov@aegee.org>
|
||
|
||
* riscv-dis.c (print_insn_args): Add fall through comment.
|
||
|
||
2017-01-03 Nick Clifton <nickc@redhat.com>
|
||
|
||
* po/sr.po: New Serbian translation.
|
||
* configure.ac (ALL_LINGUAS): Add sr.
|
||
* configure: Regenerate.
|
||
|
||
2017-01-02 Alan Modra <amodra@gmail.com>
|
||
|
||
* epiphany-desc.h: Regenerate.
|
||
* epiphany-opc.h: Regenerate.
|
||
* fr30-desc.h: Regenerate.
|
||
* fr30-opc.h: Regenerate.
|
||
* frv-desc.h: Regenerate.
|
||
* frv-opc.h: Regenerate.
|
||
* ip2k-desc.h: Regenerate.
|
||
* ip2k-opc.h: Regenerate.
|
||
* iq2000-desc.h: Regenerate.
|
||
* iq2000-opc.h: Regenerate.
|
||
* lm32-desc.h: Regenerate.
|
||
* lm32-opc.h: Regenerate.
|
||
* m32c-desc.h: Regenerate.
|
||
* m32c-opc.h: Regenerate.
|
||
* m32r-desc.h: Regenerate.
|
||
* m32r-opc.h: Regenerate.
|
||
* mep-desc.h: Regenerate.
|
||
* mep-opc.h: Regenerate.
|
||
* mt-desc.h: Regenerate.
|
||
* mt-opc.h: Regenerate.
|
||
* or1k-desc.h: Regenerate.
|
||
* or1k-opc.h: Regenerate.
|
||
* xc16x-desc.h: Regenerate.
|
||
* xc16x-opc.h: Regenerate.
|
||
* xstormy16-desc.h: Regenerate.
|
||
* xstormy16-opc.h: Regenerate.
|
||
|
||
2017-01-02 Alan Modra <amodra@gmail.com>
|
||
|
||
Update year range in copyright notice of all files.
|
||
|
||
For older changes see ChangeLog-2016
|
||
|
||
Copyright (C) 2017 Free Software Foundation, Inc.
|
||
|
||
Copying and distribution of this file, with or without modification,
|
||
are permitted in any medium without royalty provided the copyright
|
||
notice and this notice are preserved.
|
||
|
||
Local Variables:
|
||
mode: change-log
|
||
left-margin: 8
|
||
fill-column: 74
|
||
version-control: never
|
||
End:
|