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binutils-gdb/sim/mips/m16.igen
Andrew Bennett 8e394ffc7a [PATCH] Add micromips support to the MIPS simulator 
2015-09-25  Andrew Bennett  <andrew.bennett@imgtec.com>
 	      Ali Lown  <ali.lown@imgtec.com>

	sim/common/
	* sim-bits.h (EXTEND6): New macro.
	(EXTEND12): New macro.
	(EXTEND25): New macro.

	sim/mips/
	* Makefile.in (tmp-micromips): New rule.
	(tmp-mach-multi): Add support for micromips.
	* configure.ac (mips*-sde-elf* | mips*-mti-elf*): Made a multi sim
	that works for both mips64 and micromips64.
	(mipsisa32r2*-*-*): Made a multi sim that works for mips32 and
	micromips32.
	Add build support for micromips.
	* dsp.igen (do_ph_s_absq, do_w_s_absq, do_qb_s_absq, do_addsc,
	do_addwc, do_bitrev, do_extpv, do_extrv, do_extrv_s_h, do_insv,
	do_lxx do_modsub, do_mthlip, do_mulsaq_s_w_ph, do_ph_packrl, do_qb_pick
	do_ph_pick, do_qb_ph_precequ, do_qb_ph_preceu, do_w_preceq
	do_w_ph_precrq, do_ph_qb_precrq, do_w_ph_rs_precrq do_qb_w_raddu,
	do_rddsp, do_repl, do_shilov, do_ph_shl, do_qb_shl do_w_s_shllv,
	do_ph_shrlv, do_w_r_shrav, do_wrdsp, do_qb_shrav, do_append,
	do_balign, do_ph_w_mulsa, do_ph_qb_precr, do_prepend): New functions.
	Refactored instruction code to use these functions.
	* dsp2.igen: Refactored instruction code to use the new functions.
	* interp.c (decode_coproc): Refactored to work with any instruction
	encoding.
	(isa_mode): New variable
	(RSVD_INSTRUCTION): Changed to 0x00000039.
	* m16.igen (BREAK16): Refactored instruction to use do_break16.
	(JALX32): Add mips32, mips64, mips32r2 and mips64r2 models.
	* micromips.dc: New file.
	* micromips.igen: New file.
	* micromips16.dc: New file.
	* micromipsdsp.igen: New file.
	* micromipsrun.c: New file.
	* mips.igen (do_swc1): Changed to work with any instruction encoding.
	(do_add do_addi do_andi do_dadd do_daddi do_dsll32 do_dsra32
	do_dsrl32, do_dsub, do_break, do_break16, do_clo, do_clz, do_dclo
	do_dclz, do_lb, do_lh, do_lwr, do_lwl, do_lwc, do_lw, do_lwu, do_lhu
	do_ldc, do_lbu, do_ll, do_lld, do_lui, do_madd, do_dsp_madd, do_maddu
	do_dsp_maddu, do_dsp_mfhi, do_dsp_mflo, do_movn, do_movz, do_msub
	do_dsp_msub, do_msubu, do_dsp_msubu, do_mthi, do_dsp_mthi, do_mtlo
	do_dsp_mtlo, do_mul, do_dsp_mult, do_dsp_multu, do_pref, do_sc, do_scd
	do_sub, do_sw, do_teq, do_teqi, do_tge, do_tgei, do_tgeiu, do_tgeu, do_tlt
	do_tlti, do_tltiu, do_tltu, do_tne, do_tnei, do_abs_fmt, do_add_fmt
	do_alnv_ps, do_c_cond_fmt, do_ceil_fmt, do_cfc1, do_ctc1, do_cvt_d_fmt
	do_cvt_l_fmt, do_cvt_ps_s, do_cvt_s_fmt, do_cvt_s_pl, do_cvt_s_pu
	do_cvt_w_fmt, do_div_fmt, do_dmfc1b, do_dmtc1b, do_floor_fmt, do_luxc1_32
	do_luxc1_64, do_lwc1, do_lwxc1, do_madd_fmt, do_mfc1b, do_mov_fmt, do_movtf
	do_movtf_fmt, do_movn_fmt, do_movz_fmt, do_msub_fmt, do_mtc1b, do_mul_fmt
	do_neg_fmt, do_nmadd_fmt, do_nmsub_fmt, do_pll_ps, do_plu_ps, do_pul_ps
	do_puu_ps, do_recip_fmt, do_round_fmt, do_rsqrt_fmt, do_prefx, do_sdc1
	do_suxc1_32, do_suxc1_64, do_sqrt_fmt, do_sub_fmt, do_swc1, do_swxc1
	do_trunc_fmt): New functions, refactored from existing instructions.
	Refactored instruction code to use these functions.
	(RSVD): Changed to use new reserved instruction.
	(loadstore_ea, not_word_value, unpredictable, check_mt_hilo, check_mf_hilo,
	check_mult_hilo, check_div_hilo, check_u64, do_luxc1_32, do_sdc1, do_suxc1_32,
	check_fmt_p, check_fpu, do_load_double, do_store_double):  Added micromips32
	and micromips64 models.
	Added include for micromips.igen and micromipsdsp.igen
	Add micromips32 and micromips64 models.
	(DecodeCoproc): Updated to use new macro definition.
	* mips3264r2.igen (do_dsbh, do_dshd, do_dext, do_dextm, do_dextu, do_di,
	do_dins, do_dinsm, do_ei, do_ext, do_mfhc1, do_mthc1, do_ins, do_dinsu,
	do_seb, do_seh do_rdhwr, do_wsbh): New functions.
	Refactored instruction code to use these functions.
	* sim-main.h (CP0_operation): New enum.
	(DecodeCoproc): Updated macro.
	(IMEM32_MICROMIPS, IMEM16_MICROMIPS, MICROMIPS_MINOR_OPCODE,
	MICROMIPS_DELAYSLOT_SIZE_ANY, MICROMIPS_DELAYSLOT_SIZE_16, MICROMIPS_DELAYSLOT_SIZE_32,
	ISA_MODE_MIPS32 and ISA_MODE_MICROMIPS): New defines.
	(sim_state): Add isa_mode field.

	sim/testsuite/sim/mips/
       * basic.exp (run_micromips_test, run_sim_tests): New functions
	Add support for micromips tests.
	* hilo-hazard-4.s: New file.
	* testutils.inc (_dowrite): Changed reserved instruction encoding.
	(writemsg): Moved the la and li instructions before the data they are
	assigned to, which prevents a bug where MIPS32 relocations are used instead
	of micromips relocations when building for micromips.
2015-09-25 15:52:18 +01:00

1237 lines
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// -*- C -*-
//
//
// MIPS Architecture:
//
// CPU Instruction Set (mips16)
//
// The instructions in this section are ordered according
// to http://www.sgi.com/MIPS/arch/MIPS16/mips16.pdf.
// The MIPS16 codes registers in a special way, map from one to the other.
// :<type>:<flags>:<models>:<typedef>:<name>:<field>:<expression>
:compute:::int:TRX:RX:((RX < 2) ? (16 + RX) \: RX)
:compute:::int:TRY:RY:((RY < 2) ? (16 + RY) \: RY)
:compute:::int:TRZ:RZ:((RZ < 2) ? (16 + RZ) \: RZ)
:compute:::int:SHIFT:SHAMT:((SHAMT == 0) ? 8 \: SHAMT)
:compute:::int:SHAMT:SHAMT_4_0,S5:(LSINSERTED (S5, 5, 5) | SHAMT_4_0)
:compute:::address_word:IMMEDIATE:IMM_25_21,IMM_20_16,IMMED_15_0:(LSINSERTED (IMM_25_21, 25, 21) | LSINSERTED (IMM_20_16, 20, 16) | LSINSERTED (IMMED_15_0, 15, 0))
:compute:::int:R32:R32L,R32H:((R32H << 3) | R32L)
:compute:::address_word:IMMEDIATE:IMM_10_5,IMM_15_11,IMM_4_0:(LSINSERTED (IMM_10_5, 10, 5) | LSINSERTED (IMM_15_11, 15, 11) | LSINSERTED (IMM_4_0, 4, 0))
:compute:::address_word:IMMEDIATE:IMM_10_4,IMM_14_11,IMM_3_0:(LSINSERTED (IMM_10_4, 10, 4) | LSINSERTED (IMM_14_11, 14, 11) | LSINSERTED (IMM_3_0, 3, 0))
// Load and Store Instructions
10000,3.RX,3.RY,5.IMMED:RRI:16::LB
"lb r<TRY>, <IMMED> (r<TRX>)"
*mips16:
*vr4100:
{
GPR[TRY] = EXTEND8 (do_load (SD_, AccessLength_BYTE, GPR[TRX], IMMED));
}
11110,6.IMM_10_5,5.IMM_15_11 + 10000,3.RX,3.RY,5.IMM_4_0:EXT-RRI:16::LB
"lb r<TRY>, <IMMEDIATE> (r<TRX>)"
*mips16:
*vr4100:
{
GPR[TRY] = EXTEND8 (do_load (SD_, AccessLength_BYTE, GPR[TRX], EXTEND16 (IMMEDIATE)));
}
10100,3.RX,3.RY,5.IMMED:RRI:16::LBU
"lbu r<TRY>, <IMMED> (r<TRX>)"
*mips16:
*vr4100:
{
GPR[TRY] = do_load (SD_, AccessLength_BYTE, GPR[TRX], IMMED);
}
11110,6.IMM_10_5,5.IMM_15_11 + 10100,3.RX,3.RY,5.IMM_4_0:EXT-RRI:16::LBU
"lbu r<TRY>, <IMMEDIATE> (r<TRX>)"
*mips16:
*vr4100:
{
GPR[TRY] = do_load (SD_, AccessLength_BYTE, GPR[TRX], EXTEND16 (IMMEDIATE));
}
10001,3.RX,3.RY,5.IMMED:RRI:16::LH
"lh r<TRY>, <IMMED> (r<TRX>)"
*mips16:
*vr4100:
{
GPR[TRY] = EXTEND16 (do_load (SD_, AccessLength_HALFWORD, GPR[TRX], IMMED << 1));
}
11110,6.IMM_10_5,5.IMM_15_11 + 10001,3.RX,3.RY,5.IMM_4_0:EXT-RRI:16::LH
"lh r<TRY>, <IMMEDIATE> (r<TRX>)"
*mips16:
*vr4100:
{
GPR[TRY] = EXTEND16 (do_load (SD_, AccessLength_HALFWORD, GPR[TRX], EXTEND16 (IMMEDIATE)));
}
10101,3.RX,3.RY,5.IMMED:RRI:16::LHU
"lhu r<TRY>, <IMMED> (r<TRX>)"
*mips16:
*vr4100:
{
GPR[TRY] = do_load (SD_, AccessLength_HALFWORD, GPR[TRX], IMMED << 1);
}
11110,6.IMM_10_5,5.IMM_15_11 + 10101,3.RX,3.RY,5.IMM_4_0:EXT-RRI:16::LHU
"lhu r<TRY>, <IMMEDIATE> (r<TRX>)"
*mips16:
*vr4100:
{
GPR[TRY] = do_load (SD_, AccessLength_HALFWORD, GPR[TRX], EXTEND16 (IMMEDIATE));
}
10011,3.RX,3.RY,5.IMMED:RRI:16::LW
"lw r<TRY>, <IMMED> (r<TRX>)"
*mips16:
*vr4100:
{
GPR[TRY] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[TRX], IMMED << 2));
}
11110,6.IMM_10_5,5.IMM_15_11 + 10011,3.RX,3.RY,5.IMM_4_0:EXT-RRI:16::LW
"lw r<TRY>, <IMMEDIATE> (r<TRX>)"
*mips16:
*vr4100:
{
GPR[TRY] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[TRX], EXTEND16 (IMMEDIATE)));
}
10110,3.RX,8.IMMED:RI:16::LWPC
"lw r<TRX>, <IMMED> (PC)"
*mips16:
*vr4100:
{
GPR[TRX] = EXTEND32 (do_load (SD_, AccessLength_WORD,
basepc (SD_) & ~3, IMMED << 2));
}
11110,6.IMM_10_5,5.IMM_15_11 + 10110,3.RX,000,5.IMM_4_0:EXT-RI:16::LWPC
"lw r<TRX>, <IMMEDIATE> (PC)"
*mips16:
*vr4100:
{
GPR[TRX] = EXTEND32 (do_load (SD_, AccessLength_WORD, basepc (SD_) & ~3, EXTEND16 (IMMEDIATE)));
}
10010,3.RX,8.IMMED:RI:16::LWSP
"lw r<TRX>, <IMMED> (SP)"
*mips16:
*vr4100:
{
GPR[TRX] = EXTEND32 (do_load (SD_, AccessLength_WORD, SP, IMMED << 2));
}
11110,6.IMM_10_5,5.IMM_15_11 + 10010,3.RX,000,5.IMM_4_0:EXT-RI:16::LWSP
"lw r<TRX>, <IMMEDIATE> (SP)"
*mips16:
*vr4100:
{
GPR[TRX] = EXTEND32 (do_load (SD_, AccessLength_WORD, SP, EXTEND16 (IMMEDIATE)));
}
10111,3.RX,3.RY,5.IMMED:RRI:16::LWU
"lwu r<TRY>, <IMMED> (r<TRX>)"
*mips16:
*vr4100:
{
GPR[TRY] = do_load (SD_, AccessLength_WORD, GPR[TRX], IMMED << 2);
}
11110,6.IMM_10_5,5.IMM_15_11 + 10111,3.RX,3.RY,5.IMM_4_0:EXT-RRI:16::LWU
"lwu r<TRY>, <IMMEDIATE> (r<TRX>)"
*mips16:
*vr4100:
{
GPR[TRY] = do_load (SD_, AccessLength_WORD, GPR[TRX], EXTEND16 (IMMEDIATE));
}
00111,3.RX,3.RY,5.IMMED:RRI:16::LD
"ld r<TRY>, <IMMED> (r<TRX>)"
*mips16:
*vr4100:
{
GPR[TRY] = do_load (SD_, AccessLength_DOUBLEWORD, GPR[TRX], IMMED << 3);
}
11110,6.IMM_10_5,5.IMM_15_11 + 00111,3.RX,3.RY,5.IMM_4_0:EXT-RRI:16::LD
"ld r<TRY>, <IMMEDIATE> (r<TRX>)"
*mips16:
*vr4100:
{
GPR[TRY] = do_load (SD_, AccessLength_DOUBLEWORD, GPR[TRX], EXTEND16 (IMMEDIATE));
}
11111,100,3.RY,5.IMMED:RI64:16::LDPC
"ld r<TRY>, <IMMED> (PC)"
*mips16:
*vr4100:
{
GPR[TRY] = do_load (SD_, AccessLength_DOUBLEWORD,
basepc (SD_) & ~7, IMMED << 3);
}
11110,6.IMM_10_5,5.IMM_15_11 + 11111,100,3.RY,5.IMM_4_0:EXT-RI64:16::LDPC
"ld r<TRY>, <IMMEDIATE> (PC)"
*mips16:
*vr4100:
{
GPR[TRY] = do_load (SD_, AccessLength_DOUBLEWORD, basepc (SD_) & ~7, EXTEND16 (IMMEDIATE));
}
11111,000,3.RY,5.IMMED:RI64:16::LDSP
"ld r<TRY>, <IMMED> (SP)"
*mips16:
*vr4100:
{
GPR[TRY] = do_load (SD_, AccessLength_DOUBLEWORD, SP, IMMED << 3);
}
11110,6.IMM_10_5,5.IMM_15_11 + 11111,000,3.RY,5.IMM_4_0:EXT-RI64:16::LDSP
"ld r<TRY>, <IMMEDIATE> (SP)"
*mips16:
*vr4100:
{
GPR[TRY] = do_load (SD_, AccessLength_DOUBLEWORD, SP, EXTEND16 (IMMEDIATE));
}
11000,3.RX,3.RY,5.IMMED:RRI:16::SB
"sb r<TRY>, <IMMED> (r<TRX>)"
*mips16:
*vr4100:
{
do_store (SD_, AccessLength_BYTE, GPR[TRX], IMMED, GPR[TRY]);
}
11110,6.IMM_10_5,5.IMM_15_11 + 11000,3.RX,3.RY,5.IMM_4_0:EXT-RRI:16::SB
"sb r<TRY>, <IMMEDIATE> (r<TRX>)"
*mips16:
*vr4100:
{
do_store (SD_, AccessLength_BYTE, GPR[TRX], EXTEND16 (IMMEDIATE), GPR[TRY]);
}
11001,3.RX,3.RY,5.IMMED:RRI:16::SH
"sh r<TRY>, <IMMED> (r<TRX>)"
*mips16:
*vr4100:
{
do_store (SD_, AccessLength_HALFWORD, GPR[TRX], IMMED << 1, GPR[TRY]);
}
11110,6.IMM_10_5,5.IMM_15_11 + 11001,3.RX,3.RY,5.IMM_4_0:EXT-RRI:16::SH
"sh r<TRY>, <IMMEDIATE> (r<TRX>)"
*mips16:
*vr4100:
{
do_store (SD_, AccessLength_HALFWORD, GPR[TRX], EXTEND16 (IMMEDIATE), GPR[TRY]);
}
11011,3.RX,3.RY,5.IMMED:RRI:16::SW
"sw r<TRY>, <IMMED> (r<TRX>)"
*mips16:
*vr4100:
{
do_store (SD_, AccessLength_WORD, GPR[TRX], IMMED << 2, GPR[TRY]);
}
11110,6.IMM_10_5,5.IMM_15_11 + 11011,3.RX,3.RY,5.IMM_4_0:EXT-RRI:16::SW
"sw r<TRY>, <IMMEDIATE> (r<TRX>)"
*mips16:
*vr4100:
{
do_store (SD_, AccessLength_WORD, GPR[TRX], EXTEND16 (IMMEDIATE), GPR[TRY]);
}
11010,3.RX,8.IMMED:RI:16::SWSP
"sw r<TRX>, <IMMED> (SP)"
*mips16:
*vr4100:
{
do_store (SD_, AccessLength_WORD, SP, IMMED << 2, GPR[TRX]);
}
11110,6.IMM_10_5,5.IMM_15_11 + 11010,3.RX,000,5.IMM_4_0:EXT-RI:16::SWSP
"sw r<TRX>, <IMMEDIATE> (SP)"
*mips16:
*vr4100:
{
do_store (SD_, AccessLength_WORD, SP, EXTEND16 (IMMEDIATE), GPR[TRX]);
}
01100,010,8.IMMED:I8:16::SWRASP
"sw r<RAIDX>, <IMMED> (SP)"
*mips16:
*vr4100:
{
do_store (SD_, AccessLength_WORD, SP, IMMED << 2, RA);
}
11110,6.IMM_10_5,5.IMM_15_11 + 01100,010,000,5.IMM_4_0:EXT-I8:16::SWRASP
"sw r<RAIDX>, <IMMEDIATE> (SP)"
*mips16:
*vr4100:
{
do_store (SD_, AccessLength_WORD, SP, EXTEND16 (IMMEDIATE), RA);
}
01111,3.RX,3.RY,5.IMMED:RRI:16::SD
"sd r<TRY>, <IMMED> (r<TRX>)"
*mips16:
*vr4100:
{
do_store (SD_, AccessLength_DOUBLEWORD, GPR[TRX], IMMED << 3, GPR[TRY]);
}
11110,6.IMM_10_5,5.IMM_15_11 + 01111,3.RX,3.RY,5.IMM_4_0:EXT-RRI:16::SD
"sd r<TRY>, <IMMEDIATE> (r<TRX>)"
*mips16:
*vr4100:
{
do_store (SD_, AccessLength_DOUBLEWORD, GPR[TRX], EXTEND16 (IMMEDIATE), GPR[TRY]);
}
11111,001,3.RY,5.IMMED:RI64:16::SDSP
"sd r<TRY>, <IMMED> (SP)"
*mips16:
*vr4100:
{
do_store (SD_, AccessLength_DOUBLEWORD, SP, IMMED << 3, GPR[TRY]);
}
11110,6.IMM_10_5,5.IMM_15_11 + 11111,001,3.RY,5.IMM_4_0:EXT-RI64:16::SDSP
"sd r<TRY>, <IMMEDIATE> (SP)"
*mips16:
*vr4100:
{
do_store (SD_, AccessLength_DOUBLEWORD, SP, EXTEND16 (IMMEDIATE), GPR[TRY]);
}
11111,010,8.IMMED:I64:16::SDRASP
"sd r<RAIDX>, <IMMED> (SP)"
*mips16:
*vr4100:
{
do_store (SD_, AccessLength_DOUBLEWORD, SP, IMMED << 3, RA);
}
11110,6.IMM_10_5,5.IMM_15_11 + 11111,010,000,5.IMM_4_0:EXT-I64:16::SDRASP
"sd r<RAIDX>, <IMMEDIATE> (SP)"
*mips16:
*vr4100:
{
do_store (SD_, AccessLength_DOUBLEWORD, SP, EXTEND16 (IMMEDIATE), RA);
}
// ALU Immediate Instructions
01101,3.RX,8.IMMED:RI:16::LI
"li r<TRX>, <IMMED>"
*mips16:
*vr4100:
{
do_ori (SD_, 0, TRX, IMMED);
}
11110,6.IMM_10_5,5.IMM_15_11 + 01101,3.RX,000,5.IMM_4_0:EXT-RI:16::LI
"li r<TRX>, <IMMEDIATE>"
*mips16:
*vr4100:
{
do_ori (SD_, 0, TRX, IMMEDIATE);
}
01000,3.RX,3.RY,0,4.IMMED:RRI-A:16::ADDIU
"addiu r<TRY>, r<TRX>, <IMMED>"
*mips16:
*vr4100:
{
do_addiu (SD_, TRX, TRY, EXTEND4 (IMMED));
}
11110,7.IMM_10_4,4.IMM_14_11 + 01000,3.RX,3.RY,0,4.IMM_3_0:EXT-RRI-A:16::ADDIU
"addiu r<TRY>, r<TRX>, <IMMEDIATE>"
*mips16:
*vr4100:
{
do_addiu (SD_, TRX, TRY, EXTEND15 (IMMEDIATE));
}
01001,3.RX,8.IMMED:RI:16::ADDIU8
"addiu r<TRX>, <IMMED>"
*mips16:
*vr4100:
{
do_addiu (SD_, TRX, TRX, EXTEND8 (IMMED));
}
11110,6.IMM_10_5,5.IMM_15_11 + 01001,3.RX,000,5.IMM_4_0:EXT-RI:16::ADDIU8
"addiu r<TRX>, <IMMEDIATE>"
*mips16:
*vr4100:
{
do_addiu (SD_, TRX, TRX, EXTEND16 (IMMEDIATE));
}
01100,011,8.IMMED:I8:16::ADJSP
"addiu SP, <IMMED>"
*mips16:
*vr4100:
{
do_addiu (SD_, SPIDX, SPIDX, EXTEND8 (IMMED) << 3);
}
11110,6.IMM_10_5,5.IMM_15_11 + 01100,011,000,5.IMM_4_0:EXT-I8:16::ADJSP
"addiu SP, <IMMEDIATE>"
*mips16:
*vr4100:
{
do_addiu (SD_, SPIDX, SPIDX, EXTEND16 (IMMEDIATE));
}
00001,3.RX,8.IMMED:RI:16::ADDIUPC
"addiu r<TRX>, PC, <IMMED>"
*mips16:
*vr4100:
{
unsigned32 temp = (basepc (SD_) & ~3) + (IMMED << 2);
GPR[TRX] = EXTEND32 (temp);
}
11110,6.IMM_10_5,5.IMM_15_11 + 00001,3.RX,000,5.IMM_4_0:EXT-RI:16::ADDIUPC
"addiu r<TRX>, PC, <IMMEDIATE>"
*mips16:
*vr4100:
{
unsigned32 temp = (basepc (SD_) & ~3) + EXTEND16 (IMMEDIATE);
GPR[TRX] = EXTEND32 (temp);
}
00000,3.RX,8.IMMED:RI:16::ADDIUSP
"addiu r<TRX>, SP, <IMMED>"
*mips16:
*vr4100:
{
do_addiu (SD_, SPIDX, TRX, IMMED << 2);
}
11110,6.IMM_10_5,5.IMM_15_11 + 00000,3.RX,000,5.IMM_4_0:EXT-RI:16::ADDIUSP
"addiu r<TRX>, SP, <IMMEDIATE>"
*mips16:
*vr4100:
{
do_addiu (SD_, SPIDX, TRX, EXTEND16 (IMMEDIATE));
}
01000,3.RX,3.RY,1,4.IMMED:RRI-A:16::DADDIU
"daddiu r<TRY>, r<TRX>, <IMMED>"
*mips16:
*vr4100:
{
do_daddiu (SD_, TRX, TRY, EXTEND4 (IMMED));
}
11110,7.IMM_10_4,4.IMM_14_11 + 01000,3.RX,3.RY,1,4.IMM_3_0:EXT-RRI-A:16::DADDIU
"daddiu r<TRY>, r<TRX>, <IMMEDIATE>"
*mips16:
*vr4100:
{
do_daddiu (SD_, TRX, TRY, EXTEND15 (IMMEDIATE));
}
11111,101,3.RY,5.IMMED:RI64:16::DADDIU5
"daddiu r<TRY>, <IMMED>"
*mips16:
*vr4100:
{
do_daddiu (SD_, TRY, TRY, EXTEND5 (IMMED));
}
11110,6.IMM_10_5,5.IMM_15_11 + 11111,101,3.RY,5.IMM_4_0:EXT-RI64:16::DADDIU5
"daddiu r<TRY>, <IMMEDIATE>"
*mips16:
*vr4100:
{
do_daddiu (SD_, TRY, TRY, EXTEND16 (IMMEDIATE));
}
11111,011,8.IMMED:I64:16::DADJSP
"daddiu SP, <IMMED>"
*mips16:
*vr4100:
{
do_daddiu (SD_, SPIDX, SPIDX, EXTEND8 (IMMED) << 3);
}
11110,6.IMM_10_5,5.IMM_15_11 + 11111,011,000,5.IMM_4_0:EXT-I64:16::DADJSP
"daddiu SP, <IMMEDIATE>"
*mips16:
*vr4100:
{
do_daddiu (SD_, SPIDX, SPIDX, EXTEND16 (IMMEDIATE));
}
11111,110,3.RY,5.IMMED:RI64:16::DADDIUPC
"daddiu r<TRY>, PC, <IMMED>"
*mips16:
*vr4100:
{
GPR[TRY] = (basepc (SD_) & ~3) + (IMMED << 2);
}
11110,6.IMM_10_5,5.IMM_15_11 + 11111,110,3.RY,5.IMM_4_0:EXT-RI64:16::DADDIUPC
"daddiu r<TRY>, PC, <IMMEDIATE>"
*mips16:
*vr4100:
{
GPR[TRY] = (basepc (SD_) & ~3) + EXTEND16 (IMMEDIATE);
}
11111,111,3.RY,5.IMMED:RI64:16::DADDIUSP
"daddiu r<TRY>, SP, <IMMED>"
*mips16:
*vr4100:
{
do_daddiu (SD_, SPIDX, TRY, IMMED << 2);
}
11110,6.IMM_10_5,5.IMM_15_11 + 11111,111,3.RY,5.IMM_4_0:EXT-RI64:16::DADDIUSP
"daddiu r<TRY>, SP, <IMMEDIATE>"
*mips16:
*vr4100:
{
do_daddiu (SD_, SPIDX, TRY, EXTEND16 (IMMEDIATE));
}
01010,3.RX,8.IMMED:RI:16::SLTI
"slti r<TRX>, <IMMED>"
*mips16:
*vr4100:
{
do_slti (SD_, TRX, T8IDX, IMMED);
}
11110,6.IMM_10_5,5.IMM_15_11 + 01010,3.RX,000,5.IMM_4_0:EXT-RI:16::SLTI
"slti r<TRX>, <IMMEDIATE>"
*mips16:
*vr4100:
{
do_slti (SD_, TRX, T8IDX, IMMEDIATE);
}
01011,3.RX,8.IMMED:RI:16::SLTIU
"sltiu r<TRX>, <IMMED>"
*mips16:
*vr4100:
{
do_sltiu (SD_, TRX, T8IDX, IMMED);
}
11110,6.IMM_10_5,5.IMM_15_11 + 01011,3.RX,000,5.IMM_4_0:EXT-RI:16::SLTIU
"sltiu r<TRX>, <IMMEDIATE>"
*mips16:
*vr4100:
{
do_sltiu (SD_, TRX, T8IDX, IMMEDIATE);
}
11101,3.RX,3.RY,01010:RR:16::CMP
"cmp r<TRX>, r<TRY>"
*mips16:
*vr4100:
{
do_xor (SD_, TRX, TRY, T8IDX);
}
01110,3.RX,8.IMMED:RI:16::CMPI
"cmpi r<TRX>, <IMMED>"
*mips16:
*vr4100:
{
do_xori (SD_, TRX, T8IDX, IMMED);
}
11110,6.IMM_10_5,5.IMM_15_11 + 01110,3.RX,000,5.IMM_4_0:EXT-RI:16::CMPI
"sltiu r<TRX>, <IMMEDIATE>"
*mips16:
*vr4100:
{
do_xori (SD_, TRX, T8IDX, IMMEDIATE);
}
// Two/Three Operand, Register-Type
11100,3.RX,3.RY,3.RZ,01:RRR:16::ADDU
"addu r<TRZ>, r<TRX>, r<TRY>"
*mips16:
*vr4100:
{
do_addu (SD_, TRX, TRY, TRZ);
}
11100,3.RX,3.RY,3.RZ,11:RRR:16::SUBU
"subu r<TRZ>, r<TRX>, r<TRY>"
*mips16:
*vr4100:
{
do_subu (SD_, TRX, TRY, TRZ);
}
11100,3.RX,3.RY,3.RZ,00:RRR:16::DADDU
"daddu r<TRZ>, r<TRX>, r<TRY>"
*mips16:
*vr4100:
{
do_daddu (SD_, TRX, TRY, TRZ);
}
11100,3.RX,3.RY,3.RZ,10:RRR:16::DSUBU
"dsubu r<TRZ>, r<TRX>, r<TRY>"
*mips16:
*vr4100:
{
do_dsubu (SD_, TRX, TRY, TRZ);
}
11101,3.RX,3.RY,00010:RR:16::SLT
"slt r<TRX>, r<TRY>"
*mips16:
*vr4100:
{
do_slt (SD_, TRX, TRY, T8IDX);
}
11101,3.RX,3.RY,00011:RR:16::SLTU
"sltu r<TRX>, r<TRY>"
*mips16:
*vr4100:
{
do_sltu (SD_, TRX, TRY, T8IDX);
}
11101,3.RX,3.RY,01011:RR:16::NEG
"neg r<TRX>, r<TRY>"
*mips16:
*vr4100:
{
do_subu (SD_, 0, TRY, TRX);
}
11101,3.RX,3.RY,01100:RR:16::AND
"and r<TRX>, r<TRY>"
*mips16:
*vr4100:
{
do_and (SD_, TRX, TRY, TRX);
}
11101,3.RX,3.RY,01101:RR:16::OR
"or r<TRX>, r<TRY>"
*mips16:
*vr4100:
{
do_or (SD_, TRX, TRY, TRX);
}
11101,3.RX,3.RY,01110:RR:16::XOR
"xor r<TRX>, r<TRY>"
*mips16:
*vr4100:
{
do_xor (SD_, TRX, TRY, TRX);
}
11101,3.RX,3.RY,01111:RR:16::NOT
"not r<TRX>, r<TRY>"
*mips16:
*vr4100:
{
do_nor (SD_, 0, TRY, TRX);
}
01100,111,3.RY,5.R32:I8_MOVR32:16::MOVR32
"move r<TRY>, r<R32>"
*mips16:
*vr4100:
{
do_or (SD_, R32, 0, TRY);
}
01100,101,3.R32L,2.R32H,3.RZ:I8_MOV32R:16::MOV32R
"move r<R32>, r<TRZ>"
*mips16:
*vr4100:
{
do_or (SD_, TRZ, 0, R32);
}
00110,3.RX,3.RY,3.SHAMT,00:SHIFT:16::SLL
"sll r<TRX>, r<TRY>, <SHIFT>"
*mips16:
*vr4100:
{
do_sll (SD_, TRY, TRX, SHIFT);
}
11110,5.SHAMT,0,00000 + 00110,3.RX,3.RY,000,00:EXT-SHIFT:16::SLL
"sll r<TRX>, r<TRY>, <SHIFT>"
*mips16:
*vr4100:
{
do_sll (SD_, TRY, TRX, SHAMT);
}
00110,3.RX,3.RY,3.SHAMT,10:SHIFT:16::SRL
"srl r<TRX>, r<TRY>, <SHIFT>"
*mips16:
*vr4100:
{
do_srl (SD_, TRY, TRX, SHIFT);
}
11110,5.SHAMT,0,00000 + 00110,3.RX,3.RY,000,10:EXT-SHIFT:16::SRL
"srl r<TRX>, r<TRY>, <SHIFT>"
*mips16:
*vr4100:
{
do_srl (SD_, TRY, TRX, SHAMT);
}
00110,3.RX,3.RY,3.SHAMT,11:SHIFT:16::SRA
"sra r<TRX>, r<TRY>, <SHIFT>"
*mips16:
*vr4100:
{
do_sra (SD_, TRY, TRX, SHIFT);
}
11110,5.SHAMT,0,00000 + 00110,3.RX,3.RY,000,11:EXT-SHIFT:16::SRA
"sra r<TRX>, r<TRY>, <SHIFT>"
*mips16:
*vr4100:
{
do_sra (SD_, TRY, TRX, SHAMT);
}
11101,3.RX,3.RY,00100:RR:16::SLLV
"sllv r<TRY>, r<TRX>"
*mips16:
*vr4100:
{
do_sllv (SD_, TRX, TRY, TRY);
}
11101,3.RX,3.RY,00110:RR:16::SRLV
"srlv r<TRY>, r<TRX>"
*mips16:
*vr4100:
{
do_srlv (SD_, TRX, TRY, TRY);
}
11101,3.RX,3.RY,00111:RR:16::SRAV
"srav r<TRY>, r<TRX>"
*mips16:
*vr4100:
{
do_srav (SD_, TRX, TRY, TRY);
}
00110,3.RX,3.RY,3.SHAMT,01:SHIFT:16::DSLL
"dsll r<TRY>, r<TRX>, <SHIFT>"
*mips16:
*vr4100:
{
do_dsll (SD_, TRY, TRX, SHIFT);
}
11110,5.SHAMT_4_0,1.S5,00000 + 00110,3.RX,3.RY,000,01:EXT-SHIFT:16::DSLL
"dsll r<TRY>, r<TRX>, <SHAMT>"
*mips16:
*vr4100:
{
do_dsll (SD_, TRY, TRX, SHAMT);
}
11101,3.SHAMT,3.RY,01000:SHIFT64:16::DSRL
"dsrl r<TRY>, <SHIFT>"
*mips16:
*vr4100:
{
do_dsrl (SD_, TRY, TRY, SHIFT);
}
11110,5.SHAMT_4_0,1.S5,00000 + 11101,000,3.RY,01000:EXT-SHIFT64:16::DSRL
"dsrl r<TRY>, <SHAMT>"
*mips16:
*vr4100:
{
do_dsrl (SD_, TRY, TRY, SHAMT);
}
11101,3.SHAMT,3.RY,10011:SHIFT64:16::DSRA
"dsra r<TRY>, <SHIFT>"
*mips16:
*vr4100:
{
do_dsra (SD_, TRY, TRY, SHIFT);
}
11110,5.SHAMT_4_0,1.S5,00000 + 11101,000,3.RY,10011:EXT-SHIFT64:16::DSRA
"dsra r<TRY>, <SHAMT>"
*mips16:
*vr4100:
{
do_dsra (SD_, TRY, TRY, SHAMT);
}
11101,3.RX,3.RY,10100:RR:16::DSLLV
"dsllv r<TRY>, r<TRX>"
*mips16:
*vr4100:
{
do_dsllv (SD_, TRX, TRY, TRY);
}
11101,3.RX,3.RY,10110:RR:16::DSRLV
"dsrlv r<TRY>, r<TRX>"
*mips16:
*vr4100:
{
do_dsrlv (SD_, TRX, TRY, TRY);
}
11101,3.RX,3.RY,10111:RR:16::DSRAV
"dsrav r<TRY>, r<TRX>"
*mips16:
*vr4100:
{
do_dsrav (SD_, TRX, TRY, TRY);
}
// Multiply /Divide Instructions
11101,3.RX,3.RY,11000:RR:16::MULT
"mult r<TRX>, r<TRY>"
*mips16:
*vr4100:
{
do_mult (SD_, TRX, TRY, 0);
}
11101,3.RX,3.RY,11001:RR:16::MULTU
"multu r<TRX>, r<TRY>"
*mips16:
*vr4100:
{
do_multu (SD_, TRX, TRY, 0);
}
11101,3.RX,3.RY,11010:RR:16::DIV
"div r<TRX>, r<TRY>"
*mips16:
*vr4100:
{
do_div (SD_, TRX, TRY);
}
11101,3.RX,3.RY,11011:RR:16::DIVU
"divu r<TRX>, r<TRY>"
*mips16:
*vr4100:
{
do_divu (SD_, TRX, TRY);
}
11101,3.RX,000,10000:RR:16::MFHI
"mfhi r<TRX>"
*mips16:
*vr4100:
{
do_mfhi (SD_, TRX);
}
11101,3.RX,000,10010:RR:16::MFLO
"mflo r<TRX>"
*mips16:
*vr4100:
{
do_mflo (SD_, TRX);
}
11101,3.RX,3.RY,11100:RR:16::DMULT
"dmult r<TRX>, r<TRY>"
*mips16:
*vr4100:
{
do_dmult (SD_, TRX, TRY, 0);
}
11101,3.RX,3.RY,11101:RR:16::DMULTU
"dmultu r<TRX>, r<TRY>"
*mips16:
*vr4100:
{
do_dmultu (SD_, TRX, TRY, 0);
}
11101,3.RX,3.RY,11110:RR:16::DDIV
"ddiv r<TRX>, r<TRY>"
*mips16:
*vr4100:
{
do_ddiv (SD_, TRX, TRY);
}
11101,3.RX,3.RY,11111:RR:16::DDIVU
"ddivu r<TRX>, r<TRY>"
*mips16:
*vr4100:
{
do_ddivu (SD_, TRX, TRY);
}
// Jump and Branch Instructions
// Issue instruction in delay slot of branch
:function:::address_word:delayslot16:address_word nia, address_word target
{
instruction_word delay_insn;
sim_events_slip (SD, 1);
DSPC = CIA; /* save current PC somewhere */
STATE |= simDELAYSLOT;
delay_insn = IMEM16 (nia); /* NOTE: mips16 */
idecode_issue (CPU_, delay_insn, (nia));
STATE &= ~simDELAYSLOT;
return target;
}
// compute basepc dependant on us being in a delay slot
:function:::address_word:basepc:
{
if (STATE & simDELAYSLOT)
{
return DSPC; /* return saved address of preceeding jmp */
}
else
{
return CIA;
}
}
// JAL
00011,0,5.IMM_20_16,5.IMM_25_21 + 16.IMMED_15_0:JAL:16::JAL
"jal <IMMEDIATE>"
*mips16:
*vr4100:
{
address_word region = (NIA & MASK (63, 28));
RA = NIA + 2; /* skip 16 bit delayslot insn */
NIA = delayslot16 (SD_, NIA, (region | (IMMEDIATE << 2))) | 1;
}
// JALX - 32 and 16 bit versions.
011101,26.IMMED:JALX:32::JALX32
"jalx <IMMED>"
*mips32:
*mips64:
*mips32r2:
*mips64r2:
*mips16:
*vr4100:
{
address_word region = (NIA & MASK (63, 28));
RA = NIA + 4; /* skip 32 bit delayslot insn */
NIA = delayslot32 (SD_, (region | (IMMED << 2)) | 1);
}
00011,1,5.IMM_20_16,5.IMM_25_21 + 16.IMMED_15_0:JALX:16::JALX16
"jalx <IMMEDIATE>"
*mips16:
*vr4100:
{
address_word region = (NIA & MASK (63, 28));
RA = NIA + 2; /* 16 bit INSN */
NIA = delayslot16 (SD_, NIA, (region | (IMMEDIATE << 2)) & ~1);
}
11101,3.RX,000,00000:RR:16::JR
"jr r<TRX>"
*mips16:
*vr4100:
{
NIA = delayslot16 (SD_, NIA, GPR[TRX]);
}
11101,000,001,00000:RR:16::JRRA
"jrra"
*mips16:
*vr4100:
{
NIA = delayslot16 (SD_, NIA, RA);
}
11101,3.RX,010,00000:RR:16::JALR
"jalr r<TRX>"
*mips16:
*vr4100:
{
RA = NIA + 2;
NIA = delayslot16 (SD_, NIA, GPR[TRX]);
}
00100,3.RX,8.IMMED:RI:16::BEQZ
"beqz r<TRX>, <IMMED>"
*mips16:
*vr4100:
{
if (GPR[TRX] == 0)
NIA = (NIA + (EXTEND8 (IMMED) << 1));
}
11110,6.IMM_10_5,5.IMM_15_11 + 00100,3.RX,000,5.IMM_4_0:EXT-RI:16::BEQZ
"beqz r<TRX>, <IMMEDIATE>"
*mips16:
*vr4100:
{
if (GPR[TRX] == 0)
NIA = (NIA + (EXTEND16 (IMMEDIATE) << 1));
}
00101,3.RX,8.IMMED:RI:16::BNEZ
"bnez r<TRX>, <IMMED>"
*mips16:
*vr4100:
{
if (GPR[TRX] != 0)
NIA = (NIA + (EXTEND8 (IMMED) << 1));
}
11110,6.IMM_10_5,5.IMM_15_11 + 00101,3.RX,000,5.IMM_4_0:EXT-RI:16::BNEZ
"bnez r<TRX>, <IMMEDIATE>"
*mips16:
*vr4100:
{
if (GPR[TRX] != 0)
NIA = (NIA + (EXTEND16 (IMMEDIATE) << 1));
}
01100,000,8.IMMED:I8:16::BTEQZ
"bteqz <IMMED>"
*mips16:
*vr4100:
{
if (T8 == 0)
NIA = (NIA + (EXTEND8 (IMMED) << 1));
}
11110,6.IMM_10_5,5.IMM_15_11 + 01100,000,000,5.IMM_4_0:EXT-I8:16::BTEQZ
"bteqz <IMMEDIATE>"
*mips16:
*vr4100:
{
if (T8 == 0)
NIA = (NIA + (EXTEND16 (IMMEDIATE) << 1));
}
01100,001,8.IMMED:I8:16::BTNEZ
"btnez <IMMED>"
*mips16:
*vr4100:
{
if (T8 != 0)
NIA = (NIA + (EXTEND8 (IMMED) << 1));
}
11110,6.IMM_10_5,5.IMM_15_11 + 01100,001,000,5.IMM_4_0:EXT-I8:16::BTNEZ
"btnez <IMMEDIATE>"
*mips16:
*vr4100:
{
if (T8 != 0)
NIA = (NIA + (EXTEND16 (IMMEDIATE) << 1));
}
00010,11.IMMED:I:16::B
"b <IMMED>"
*mips16:
*vr4100:
{
NIA = (NIA + (EXTEND11 (IMMED) << 1));
}
11110,6.IMM_10_5,5.IMM_15_11 + 00010,6.0,5.IMM_4_0:EXT-I:16::B
"b <IMMEDIATE>"
*mips16:
*vr4100:
{
NIA = (NIA + (EXTEND16 (IMMEDIATE) << 1));
}
11101,3.RX,3.RY,00101:RR:16::BREAK
"break"
*mips16:
*vr4100:
{
do_break16 (SD_, instruction_0);
}
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