823 lines
25 KiB
Plaintext
823 lines
25 KiB
Plaintext
2011-12-15 Nick Clifton <nickc@redhat.com>
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* cgen-asm.c (cgen_parse_signed_integer): Add code to handle the
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sign extension of negative values on a 64-bit host.
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* frv-asm.c: Regenerate.
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2011-12-13 Alan Modra <amodra@gmail.com>
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* ppc-opc.c (ISA_V2): Define and use for relevant BO field tests.
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(valid_bo_pre_v2, valid_bo_post_v2): New functions, extracted from..
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(valid_bo): ..here. When disassembling, accept either 'y' or 'at'
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type encoding on second pass.
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(powerpc_opcodes): Use ISA_V2 to enable branch insns rather than
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POWER4.
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* ppc-dis.c (print_insn_powerpc): Delete dialect_orig. Instead
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ignore deprecated on second pass.
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2011-12-08 Andrew Pinski <apinski@cavium.com>
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* mips-opc.c (mips_builtin_opcodes): Add "pause".
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2011-12-08 Andrew Pinski <apinski@cavium.com>
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Adam Nemet <anemet@caviumnetworks.com>
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* mips-dis.c (mips_arch_choices): Add Octeon2.
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For "octeon+", just include OcteonP for the insn.
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* mips-opc.c (IOCT): Include Octeon2.
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(IOCTP): Include Octeon2.
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(IOCT2): New macro.
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(mips_builtin_opcodes): Add "laa", "laad", "lac", "lacd", "lad",
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"ladd", "lai", "laid", "las", "lasd", "law", "lawd".
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Move "lbux", "ldx", "lhx", "lwx", and "lwux" up to where the standard
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loads are, and add IOCT2 to them.
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Add "lbx" and "lhux".
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Add "qmac.00", "qmac.01", "qmac.02", "qmac.03", "qmacs.00",
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"qmacs.01", "qmacs.01", "qmacs.02" and "qmacs.03".
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Add "zcb" and "zcbt".
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2011-11-29 Andrew Pinski <apinski@cavium.com>
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* mips-dis.c (mips_arch_choices): Add Octeon+.
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* mips-opc.c (IOCT): Include Octeon+.
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(IOCTP): New macro.
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(mips_builtin_opcodes): Add "saa" and "saad".
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2011-11-25 Pierre Muller <muller@ics.u-strasbg.fr>
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* mips-dis.c (print_insn_micromips): Rename local variable iprintf
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to infprintf to avoid shadow warning.
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2011-11-25 Nick Clifton <nickc@redhat.com>
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* po/it.po: Updated Italian translation.
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2011-11-16 Maciej W. Rozycki <macro@codesourcery.com>
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* micromips-opc.c (micromips_opcodes): Use NODS rather than TRAP
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for "alnv.ps".
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2011-11-02 Nick Clifton <nickc@redhat.com>
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* po/it.po: New Italian translation.
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* configure.in (ALL_LINGUAS): Add it.
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* configure: Regenerate.
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* po/opcodes.pot: Regenerate.
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2011-11-01 DJ Delorie <dj@redhat.com>
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* Makefile.am (TARGET_LIBOPCODES_CFILES): Add rl78-decode.c and
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rl78-dis.c.
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(MAINTAINERCLEANFILES): Add rl78-decode.c.
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(rl78-decode.c): New rule, built from rl78-decode.opc and opc2c.
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* Makefile.in: Regenerate.
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* configure.in: Add bfd_rl78_arch case.
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* configure: Regenerate.
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* disassemble.c: Define ARCH_rl78.
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(disassembler): Add ARCH_rl78 case.
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* rl78-decode.c: New file.
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* rl78-decode.opc: New file.
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* rl78-dis.c: New file.
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2011-10-27 Peter Bergner <bergner@vnet.ibm.com>
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* ppc-opc.c (powerpc_opcodes) <drrndq, drrndq., dtstexq, dctqpq,
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dctqpq., dctfixq, dctfixq., dxexq, dxexq., dtstsfq, dcffixq, dcffixq.,
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diexq, diexq.>: Use FRT, FRA, FRB and FRBp repsectively on DFP quad
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instructions.
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2011-10-26 Nick Clifton <nickc@redhat.com>
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PR binutils/13348
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* i386-dis.c (print_insn): Fix testing of array subscript.
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2011-10-26 Joern Rennecke <joern.rennecke@embecosm.com>
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* disassemble.c (ARCH_epiphany): Move into alphasorted spot.
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* epiphany-asm.c, epiphany-opc.h: Regenerate.
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2011-10-25 Joern Rennecke <joern.rennecke@embecosm.com>
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* Makefile.am (HFILES): Add epiphany-desc.h and epiphany-opc.h .
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(TARGET_LIBOPCODES_CFILES): Add epiphany-asm.c, epiphany-desc.c,
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epiphany-dis.c, epiphany-ibld.c and epiphany-opc.c .
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(CLEANFILES): Add stamp-epiphany.
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(EPIPHANY_DEPS): Set. Make CGEN-generated Epiphany files depend on it.
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(stamp-epiphany): New rule.
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* configure.in: Handle bfd_epiphany_arch.
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* disassemble.c (ARCH_epiphany): Define.
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(disassembler): Handle bfd_arch_epiphany.
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* epiphany-asm.c: New file.
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* epiphany-desc.c: New file.
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* epiphany-desc.h: New file.
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* epiphany-dis.c: New file.
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* epiphany-ibld.c: New file.
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* epiphany-opc.c: New file.
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* epiphany-opc.h: New file.
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* Makefile.in: Regenerate.
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* configure: Regenerate.
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* po/POTFILES.in: Regenerate.
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* po/opcodes.pot: Regenerate.
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2011-10-24 Julian Brown <julian@codesourcery.com>
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* m68k-opc.c (m68k_opcodes): Fix entries for ColdFire moveml.
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2011-10-21 Jan Glauber <jang@linux.vnet.ibm.com>
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* s390-opc.txt: Add CPUMF instructions.
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2011-10-18 Jie Zhang <jie@codesourcery.com>
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Julian Brown <julian@codesourcery.com>
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* arm-dis.c (print_insn_arm): Explicitly specify rotation if needed.
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2011-10-10 Nick Clifton <nickc@redhat.com>
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* po/es.po: Updated Spanish translation.
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* po/fi.po: Updated Finnish translation.
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2011-09-28 Jan Beulich <jbeulich@suse.com>
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* ppc-opc.c (insert_nbi, insert_rbx, FRAp, FRBp, FRSp, FRTp, NBI, RAX,
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RBX): New.
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(insert_bo, insert_boe): Reject bcctr with bit 2 in bo unset.
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(powerpc_opcodes): Use RAX for second and RBXC for third operand of
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lswx. Use NBI for third operand of lswi. Use FRTp for first operand of
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lfdp and lfdpx. Use FRSp for first operand of stfdp and stfdpx, and
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mark them as invalid on POWER7. Use FRTp, FRAp, and FRBp repsectively
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on DFP quad instructions.
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2011-09-27 David S. Miller <davem@davemloft.net>
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* sparc-opc.c (sparc_opcodes): Fix random instruction to write
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to a float instead of an integer register.
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2011-09-26 David S. Miller <davem@davemloft.net>
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* sparc-opc.c (sparc_opcodes): Add integer multiply-add
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instructions.
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2011-09-21 David S. Miller <davem@davemloft.net>
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* sparc-opc.c (sparc_opcodes): Annotate table with HWCAP flag
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bits. Fix "fchksm16" mnemonic.
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2011-09-08 Mark Fortescue <mark@mtfhpc.demon.co.uk>
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The changes below bring 'mov' and 'ticc' instructions into line
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with the V8 SPARC Architecture Manual.
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* sparc-opc.c (sparc_opcodes): Add entry for 'ticc imm + regrs1'.
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* sparc-opc.c (sparc_opcodes): Add alias entries for
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'mov regrs2,%asrX'; 'mov regrs2,%y'; 'mov regrs2,%prs';
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'mov regrs2,%wim' and 'mov regrs2,%tbr'.
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* sparc-opc.c (sparc_opcodes): Move/Change entries for
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'mov imm,%asrX'; 'mov imm,%y'; 'mov imm,%prs'; 'mov imm,%wim'
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and 'mov imm,%tbr'.
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* sparc-opc.c (sparc_opcodes): Add wr alias entries to match above
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mov aliases.
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* sparc-opc.c (sparc_opcodes): Add entry for 'save simm13,regrs1,regrd'
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This has been reported as being accepted by the Sun assmebler.
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2011-09-08 David S. Miller <davem@davemloft.net>
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* sparc-opc.c (pdistn): Destination is integer not float register.
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2011-09-07 Andreas Schwab <schwab@linux-m68k.org>
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PR gas/13145
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* m68k-opc.c: Use "y" in moveml pattern for mcfisa_a.
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2011-08-26 Nick Clifton <nickc@redhat.com>
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* po/es.po: Updated Spanish translation.
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2011-08-22 Nick Clifton <nickc@redhat.com>
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* Makefile.am (CPUDIR): Redfine to point to top level cpu
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directory.
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(stamp-frv): Use CPUDIR.
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(stamp-iq2000): Likewise.
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(stamp-lm32): Likewise.
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(stamp-m32c): Likewise.
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(stamp-mt): Likewise.
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(stamp-xc16x): Likewise.
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* Makefile.in: Regenerate.
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2011-08-09 Chao-ying Fu <fu@mips.com>
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Maciej W. Rozycki <macro@codesourcery.com>
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* mips-dis.c (mips_arch_choices): Enable MCU for "mips32r2"
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and "mips64r2".
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(print_insn_args, print_insn_micromips): Handle MCU.
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* micromips-opc.c (MC): New macro.
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(micromips_opcodes): Add "aclr", "aset" and "iret".
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* mips-opc.c (MC): New macro.
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(mips_builtin_opcodes): Add "aclr", "aset" and "iret".
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2011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
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* micromips-opc.c (MOD_mb, MOD_mc, MOD_md): Remove macros.
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(MOD_me, MOD_mf, MOD_mg, MOD_mhi, MOD_mj, MOD_ml): Likewise.
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(MOD_mm, MOD_mn, MOD_mp, MOD_mq, MOD_sp): Likewise.
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(WR_mb, RD_mc, RD_md, WR_md, RD_me, RD_mf, WR_mf): New macros.
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(RD_mg, WR_mhi, RD_mj, WR_mj, RD_ml, RD_mmn): Likewise.
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(RD_mp, WR_mp, RD_mq, RD_sp, WR_sp): Likewise.
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(WR_s): Update macro.
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(micromips_opcodes): Update register use flags of: "addiu",
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"addiupc", "addiur1sp", "addiur2", "addius5", "addiusp", "addu",
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"and", "andi", "beq", "beqz", "bne", "bnez", "di", "ei", "j",
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"jalr", "jalrs", "jr", "jraddiusp", "jrc", "lbu", "lhu", "li",
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"lui", "lw", "lwm", "mfhi", "mflo", "move", "movep", "not",
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"nor", "or", "ori", "sb", "sh", "sll", "srl", "subu", "sw",
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"swm" and "xor" instructions.
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2011-08-05 David S. Miller <davem@davemloft.net>
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* sparc-dis.c (v9a_ast_reg_names): Add "cps".
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(X_RS3): New macro.
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(print_insn_sparc): Handle '4', '5', and '(' format codes.
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Accept %asr numbers below 28.
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* sparc-opc.c (sparc_opcodes): Add entries for HPC and VIS3
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instructions.
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2011-08-02 Quentin Neill <quentin.neill@amd.com>
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* i386-dis.c (xop_table): Remove spurious bextr insn.
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2011-08-01 H.J. Lu <hongjiu.lu@intel.com>
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PR ld/13048
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* i386-dis.c (print_insn): Optimize info->mach check.
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2011-08-01 H.J. Lu <hongjiu.lu@intel.com>
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PR gas/13046
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* i386-opc.tbl: Add Disp32S to 64bit call.
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* i386-tbl.h: Regenerated.
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2011-07-24 Chao-ying Fu <fu@mips.com>
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Maciej W. Rozycki <macro@codesourcery.com>
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* micromips-opc.c: New file.
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* mips-dis.c (micromips_to_32_reg_b_map): New array.
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(micromips_to_32_reg_c_map, micromips_to_32_reg_d_map): Likewise.
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(micromips_to_32_reg_e_map, micromips_to_32_reg_f_map): Likewise.
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(micromips_to_32_reg_g_map, micromips_to_32_reg_l_map): Likewise.
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(micromips_to_32_reg_q_map): Likewise.
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(micromips_imm_b_map, micromips_imm_c_map): Likewise.
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(micromips_ase): New variable.
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(is_micromips): New function.
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(set_default_mips_dis_options): Handle microMIPS ASE.
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(print_insn_micromips): New function.
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(is_compressed_mode_p): Likewise.
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(_print_insn_mips): Handle microMIPS instructions.
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* Makefile.am (CFILES): Add micromips-opc.c.
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* configure.in (bfd_mips_arch): Add micromips-opc.lo.
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* Makefile.in: Regenerate.
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* configure: Regenerate.
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* mips-dis.c (micromips_to_32_reg_h_map): New variable.
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(micromips_to_32_reg_i_map): Likewise.
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(micromips_to_32_reg_m_map): Likewise.
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(micromips_to_32_reg_n_map): New macro.
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2011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
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* mips-opc.c (NODS): New macro.
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(TRAP): Adjust for the rename of INSN_TRAP to INSN_NO_DELAY_SLOT.
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(DSP_VOLA): Likewise.
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(mips_builtin_opcodes): Add NODS annotation to "deret" and
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"eret". Replace INSN_SYNC with NODS throughout. Use NODS in
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place of TRAP for "wait", "waiti" and "yield".
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* mips16-opc.c (NODS): New macro.
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(TRAP): Adjust for the rename of INSN_TRAP to INSN_NO_DELAY_SLOT.
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(mips16_opcodes): Use NODS in place of TRAP for "jalrc", "jrc",
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"restore" and "save".
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2011-07-22 H.J. Lu <hongjiu.lu@intel.com>
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* configure.in: Handle bfd_k1om_arch.
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* configure: Regenerated.
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* disassemble.c (disassembler): Handle bfd_k1om_arch.
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* i386-dis.c (print_insn): Handle bfd_mach_k1om and
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bfd_mach_k1om_intel_syntax.
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* i386-gen.c (cpu_flag_init): Set CPU_UNKNOWN_FLAGS to
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~(CpuL1OM|CpuK1OM). Add CPU_K1OM_FLAGS.
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(cpu_flags): Add CpuK1OM.
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* i386-opc.h (CpuK1OM): New.
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(i386_cpu_flags): Add cpuk1om.
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* i386-init.h: Regenerated.
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* i386-tbl.h: Likewise.
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2011-07-12 Nick Clifton <nickc@redhat.com>
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* arm-dis.c (print_insn_arm): Revert previous, undocumented,
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accidental change.
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2011-07-01 Nick Clifton <nickc@redhat.com>
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PR binutils/12329
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* avr-dis.c (avr_operand): Fix disassembly of ELPM, LPM and SPM
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insns using post-increment addressing.
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2011-06-30 H.J. Lu <hongjiu.lu@intel.com>
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* i386-dis.c (vex_len_table): Update rorxS.
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2011-06-30 H.J. Lu <hongjiu.lu@intel.com>
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AVX Programming Reference (June, 2011)
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* i386-dis.c (vex_len_table): Correct rorxS.
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* i386-opc.tbl: Correct rorx.
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* i386-tbl.h: Regenerated.
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2011-06-29 H.J. Lu <hongjiu.lu@intel.com>
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* tilegx-opc.c (find_opcode): Replace "index" with "i".
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* tilepro-opc.c (find_opcode): Likewise.
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2011-06-29 Richard Sandiford <rdsandiford@googlemail.com>
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* mips16-opc.c (jalrc, jrc): Move earlier in file.
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2011-06-21 H.J. Lu <hongjiu.lu@intel.com>
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* i386-dis.c (prefix_table): Re-indent PREFIX_VEX_0F388C and
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PREFIX_VEX_0F388E.
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2011-06-17 Andreas Schwab <schwab@redhat.com>
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* Makefile.am (MAINTAINERCLEANFILES): Move s390-opc.tab ...
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(MOSTLYCLEANFILES): ... here.
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* Makefile.in: Regenerate.
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2011-06-14 Alan Modra <amodra@gmail.com>
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* Makefile.in: Regenerate.
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2011-06-13 Walter Lee <walt@tilera.com>
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* Makefile.am (TARGET_LIBOPCODES_CFILES): Add tilegx-dis.c,
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tilegx-opc.c, tilepro-dis.c, and tilepro-opc.c.
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* Makefile.in: Regenerate.
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* configure.in: Handle bfd_tilegx_arch and bfd_tilepro_arch.
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* configure: Regenerate.
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* disassemble.c (disassembler): Add ARCH_tilegx and ARCH_tilepro.
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* po/POTFILES.in: Regenerate.
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* tilegx-dis.c: New file.
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* tilegx-opc.c: New file.
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* tilepro-dis.c: New file.
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* tilepro-opc.c: New file.
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2011-06-10 H.J. Lu <hongjiu.lu@intel.com>
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AVX Programming Reference (June, 2011)
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* i386-dis.c (XMGatherQ): New.
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* i386-dis.c (EXxmm_mb): New.
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(EXxmm_mb): Likewise.
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(EXxmm_mw): Likewise.
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(EXxmm_md): Likewise.
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(EXxmm_mq): Likewise.
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(EXxmmdw): Likewise.
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(EXxmmqd): Likewise.
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(VexGatherQ): Likewise.
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(MVexVSIBDWpX): Likewise.
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(MVexVSIBQWpX): Likewise.
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(xmm_mb_mode): Likewise.
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(xmm_mw_mode): Likewise.
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(xmm_md_mode): Likewise.
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(xmm_mq_mode): Likewise.
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(xmmdw_mode): Likewise.
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(xmmqd_mode): Likewise.
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(ymmxmm_mode): Likewise.
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(vex_vsib_d_w_dq_mode): Likewise.
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(vex_vsib_q_w_dq_mode): Likewise.
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(MOD_VEX_0F385A_PREFIX_2): Likewise.
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(MOD_VEX_0F388C_PREFIX_2): Likewise.
|
||
(MOD_VEX_0F388E_PREFIX_2): Likewise.
|
||
(PREFIX_0F3882): Likewise.
|
||
(PREFIX_VEX_0F3816): Likewise.
|
||
(PREFIX_VEX_0F3836): Likewise.
|
||
(PREFIX_VEX_0F3845): Likewise.
|
||
(PREFIX_VEX_0F3846): Likewise.
|
||
(PREFIX_VEX_0F3847): Likewise.
|
||
(PREFIX_VEX_0F3858): Likewise.
|
||
(PREFIX_VEX_0F3859): Likewise.
|
||
(PREFIX_VEX_0F385A): Likewise.
|
||
(PREFIX_VEX_0F3878): Likewise.
|
||
(PREFIX_VEX_0F3879): Likewise.
|
||
(PREFIX_VEX_0F388C): Likewise.
|
||
(PREFIX_VEX_0F388E): Likewise.
|
||
(PREFIX_VEX_0F3890..PREFIX_VEX_0F3893): Likewise.
|
||
(PREFIX_VEX_0F38F5): Likewise.
|
||
(PREFIX_VEX_0F38F6): Likewise.
|
||
(PREFIX_VEX_0F3A00): Likewise.
|
||
(PREFIX_VEX_0F3A01): Likewise.
|
||
(PREFIX_VEX_0F3A02): Likewise.
|
||
(PREFIX_VEX_0F3A38): Likewise.
|
||
(PREFIX_VEX_0F3A39): Likewise.
|
||
(PREFIX_VEX_0F3A46): Likewise.
|
||
(PREFIX_VEX_0F3AF0): Likewise.
|
||
(VEX_LEN_0F3816_P_2): Likewise.
|
||
(VEX_LEN_0F3819_P_2): Likewise.
|
||
(VEX_LEN_0F3836_P_2): Likewise.
|
||
(VEX_LEN_0F385A_P_2_M_0): Likewise.
|
||
(VEX_LEN_0F38F5_P_0): Likewise.
|
||
(VEX_LEN_0F38F5_P_1): Likewise.
|
||
(VEX_LEN_0F38F5_P_3): Likewise.
|
||
(VEX_LEN_0F38F6_P_3): Likewise.
|
||
(VEX_LEN_0F38F7_P_1): Likewise.
|
||
(VEX_LEN_0F38F7_P_2): Likewise.
|
||
(VEX_LEN_0F38F7_P_3): Likewise.
|
||
(VEX_LEN_0F3A00_P_2): Likewise.
|
||
(VEX_LEN_0F3A01_P_2): Likewise.
|
||
(VEX_LEN_0F3A38_P_2): Likewise.
|
||
(VEX_LEN_0F3A39_P_2): Likewise.
|
||
(VEX_LEN_0F3A46_P_2): Likewise.
|
||
(VEX_LEN_0F3AF0_P_3): Likewise.
|
||
(VEX_W_0F3816_P_2): Likewise.
|
||
(VEX_W_0F3818_P_2): Likewise.
|
||
(VEX_W_0F3819_P_2): Likewise.
|
||
(VEX_W_0F3836_P_2): Likewise.
|
||
(VEX_W_0F3846_P_2): Likewise.
|
||
(VEX_W_0F3858_P_2): Likewise.
|
||
(VEX_W_0F3859_P_2): Likewise.
|
||
(VEX_W_0F385A_P_2_M_0): Likewise.
|
||
(VEX_W_0F3878_P_2): Likewise.
|
||
(VEX_W_0F3879_P_2): Likewise.
|
||
(VEX_W_0F3A00_P_2): Likewise.
|
||
(VEX_W_0F3A01_P_2): Likewise.
|
||
(VEX_W_0F3A02_P_2): Likewise.
|
||
(VEX_W_0F3A38_P_2): Likewise.
|
||
(VEX_W_0F3A39_P_2): Likewise.
|
||
(VEX_W_0F3A46_P_2): Likewise.
|
||
(MOD_VEX_0F3818_PREFIX_2): Removed.
|
||
(MOD_VEX_0F3819_PREFIX_2): Likewise.
|
||
(VEX_LEN_0F60_P_2..VEX_LEN_0F6D_P_2): Likewise.
|
||
(VEX_LEN_0F70_P_1..VEX_LEN_0F76_P_2): Likewise.
|
||
(VEX_LEN_0FD1_P_2..VEX_LEN_0FD5_P_2): Likewise.
|
||
(VEX_LEN_0FD7_P_2_M_1..VEX_LEN_0F3819_P_2_M_0): Likewise.
|
||
(VEX_LEN_0F381C_P_2..VEX_LEN_0F3840_P_2): Likewise.
|
||
(VEX_LEN_0F3A0E_P_2): Likewise.
|
||
(VEX_LEN_0F3A0F_P_2): Likewise.
|
||
(VEX_LEN_0F3A42_P_2): Likewise.
|
||
(VEX_LEN_0F3A4C_P_2): Likewise.
|
||
(VEX_W_0F3818_P_2_M_0): Likewise.
|
||
(VEX_W_0F3819_P_2_M_0): Likewise.
|
||
(prefix_table): Updated.
|
||
(three_byte_table): Likewise.
|
||
(vex_table): Likewise.
|
||
(vex_len_table): Likewise.
|
||
(vex_w_table): Likewise.
|
||
(mod_table): Likewise.
|
||
(putop): Handle "LW".
|
||
(intel_operand_size): Handle xmm_mb_mode, xmm_mw_mode,
|
||
xmm_md_mode, xmm_mq_mode, xmmdw_mode, xmmqd_mode, ymmxmm_mode,
|
||
vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode.
|
||
(OP_EX): Likewise.
|
||
(OP_E_memory): Handle vex_vsib_d_w_dq_mode and
|
||
vex_vsib_q_w_dq_mode.
|
||
(OP_XMM): Handle vex_vsib_q_w_dq_mode.
|
||
(OP_VEX): Likewise.
|
||
|
||
* i386-gen.c (cpu_flag_init): Add CpuAVX2 to CPU_ANY_SSE_FLAGS
|
||
and CPU_ANY_AVX_FLAGS. Add CPU_BMI2_FLAGS, CPU_LZCNT_FLAGS,
|
||
CPU_INVPCID_FLAGS and CPU_AVX2_FLAGS.
|
||
(cpu_flags): Add CpuAVX2, CpuBMI2, CpuLZCNT and CpuINVPCID.
|
||
(opcode_modifiers): Add VecSIB.
|
||
|
||
* i386-opc.h (CpuAVX2): New.
|
||
(CpuBMI2): Likewise.
|
||
(CpuLZCNT): Likewise.
|
||
(CpuINVPCID): Likewise.
|
||
(VecSIB128): Likewise.
|
||
(VecSIB256): Likewise.
|
||
(VecSIB): Likewise.
|
||
(i386_cpu_flags): Add cpuavx2, cpubmi2, cpulzcnt and cpuinvpcid.
|
||
(i386_opcode_modifier): Add vecsib.
|
||
|
||
* i386-opc.tbl: Add invpcid, AVX2 and BMI2 instructions.
|
||
* i386-init.h: Regenerated.
|
||
* i386-tbl.h: Likewise.
|
||
|
||
2011-06-03 Quentin Neill <quentin.neill@amd.com>
|
||
|
||
* i386-gen.c (cpu_flag_init): Add CpuF16C to CPU_BDVER2_FLAGS.
|
||
* i386-init.h: Regenerated.
|
||
|
||
2011-06-03 Nick Clifton <nickc@redhat.com>
|
||
|
||
PR binutils/12752
|
||
* arm-dis.c (print_insn_coprocessor): Use bfd_vma type for
|
||
computing address offsets.
|
||
(print_arm_address): Likewise.
|
||
(print_insn_arm): Likewise.
|
||
(print_insn_thumb16): Likewise.
|
||
(print_insn_thumb32): Likewise.
|
||
|
||
2011-06-02 Jie Zhang <jie@codesourcery.com>
|
||
Nathan Sidwell <nathan@codesourcery.com>
|
||
Maciej Rozycki <macro@codesourcery.com>
|
||
|
||
* arm-dis.c (print_insn_coprocessor): Explicitly print #-0
|
||
as address offset.
|
||
(print_arm_address): Likewise. Elide positive #0 appropriately.
|
||
(print_insn_arm): Likewise.
|
||
|
||
2011-06-02 Nick Clifton <nickc@redhat.com>
|
||
|
||
PR gas/12752
|
||
* arm-dis.c (print_insn_thumb32): Do not sign extend addresses
|
||
passed to print_address_func.
|
||
|
||
2011-06-02 Nick Clifton <nickc@redhat.com>
|
||
|
||
* arm-dis.c: Fix spelling mistakes.
|
||
* op/opcodes.pot: Regenerate.
|
||
|
||
2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
|
||
|
||
* s390-opc.c: Replace S390_OPERAND_REG_EVEN with
|
||
S390_OPERAND_REG_PAIR. Fix INSTR_RRF_0UFEF instruction type.
|
||
* s390-opc.txt: Fix cxr instruction type.
|
||
|
||
2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
|
||
|
||
* s390-opc.c: Add new instruction types marking register pair
|
||
operands.
|
||
* s390-opc.txt: Match instructions having register pair operands
|
||
to the new instruction types.
|
||
|
||
2011-05-19 Nick Clifton <nickc@redhat.com>
|
||
|
||
* v850-opc.c (cmpf.[sd]): Reverse the order of the reg1 and reg2
|
||
operands.
|
||
|
||
2011-05-10 Quentin Neill <quentin.neill@amd.com>
|
||
|
||
* i386-gen.c (cpu_flag_init): Add new CPU_BDVER2_FLAGS.
|
||
* i386-init.h: Regenerated.
|
||
|
||
2011-04-27 Nick Clifton <nickc@redhat.com>
|
||
|
||
* po/da.po: Updated Danish translation.
|
||
|
||
2011-04-26 Anton Blanchard <anton@samba.org>
|
||
|
||
* ppc-opc.c: (powerpc_opcodes): Enable icswx for POWER7.
|
||
|
||
2011-04-21 DJ Delorie <dj@redhat.com>
|
||
|
||
* rx-decode.opc (rx_decode_opcode): Set the syntax for multi-byte NOPs.
|
||
* rx-decode.c: Regenerate.
|
||
|
||
2011-04-20 H.J. Lu <hongjiu.lu@intel.com>
|
||
|
||
* i386-init.h: Regenerated.
|
||
|
||
2011-04-19 Quentin Neill <quentin.neill@amd.com>
|
||
|
||
* i386-gen.c (cpu_flag_init): Remove 3dnow and 3dnowa bits
|
||
from bdver1 flags.
|
||
|
||
2011-04-13 Nick Clifton <nickc@redhat.com>
|
||
|
||
* v850-dis.c (disassemble): Always print a closing square brace if
|
||
an opening square brace was printed.
|
||
|
||
2011-04-12 Nick Clifton <nickc@redhat.com>
|
||
|
||
PR binutils/12534
|
||
* arm-dis.c (thumb32_opcodes): Add %L suffix to LDRD and STRD insn
|
||
patterns.
|
||
(print_insn_thumb32): Handle %L.
|
||
|
||
2011-04-11 Julian Brown <julian@codesourcery.com>
|
||
|
||
* arm-dis.c (psr_name): Fix typo for BASEPRI_MAX.
|
||
(print_insn_thumb32): Add APSR bitmask support.
|
||
|
||
2011-04-07 Paul Carroll<pcarroll@codesourcery.com>
|
||
|
||
* arm-dis.c (print_insn): init vars moved into private_data structure.
|
||
|
||
2011-03-24 Mike Frysinger <vapier@gentoo.org>
|
||
|
||
* bfin-dis.c (decode_dsp32mac_0): Move MM zeroing down to MAC0 logic.
|
||
|
||
2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
|
||
|
||
* avr-dis.c (avr_operand): Add opcode_str parameter. Check for
|
||
post-increment to support LPM Z+ instruction. Add support for 'E'
|
||
constraint for DES instruction.
|
||
(print_insn_avr): Adjust calls to avr_operand. Rename variable.
|
||
|
||
2011-03-14 Richard Sandiford <richard.sandiford@linaro.org>
|
||
|
||
* arm-dis.c (get_sym_code_type): Treat STT_GNU_IFUNCs as code.
|
||
|
||
2011-03-14 Richard Sandiford <richard.sandiford@linaro.org>
|
||
|
||
* arm-dis.c (get_sym_code_type): Don't check for STT_ARM_TFUNC.
|
||
Use branch types instead.
|
||
(print_insn): Likewise.
|
||
|
||
2011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
|
||
|
||
* mips-opc.c (mips_builtin_opcodes): Correct register use
|
||
annotation of "alnv.ps".
|
||
|
||
2011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
|
||
|
||
* mips-opc.c (mips_builtin_opcodes): Add "pref" macro.
|
||
|
||
2011-02-22 Mike Frysinger <vapier@gentoo.org>
|
||
|
||
* bfin-dis.c (OUTS): Remove p NULL check and txt NUL check.
|
||
|
||
2011-02-22 Mike Frysinger <vapier@gentoo.org>
|
||
|
||
* bfin-dis.c (print_insn_bfin): Change outf->fprintf_func to OUTS.
|
||
|
||
2011-02-19 Mike Frysinger <vapier@gentoo.org>
|
||
|
||
* bfin-dis.c (saved_state): Mark static. Change a[01]x to ax[] and
|
||
a[01]w to aw[]. Delete ac0, ac0_copy, ac1, an, aq, av0, av0s, av1,
|
||
av1s, az, cc, v, v_copy, vs, rnd_mod, v_internal, pc, ticks, insts,
|
||
exception, end_of_registers, msize, memory, bfd_mach.
|
||
(CCREG, PCREG, A0XREG, A0WREG, A1XREG, A1WREG, LC0REG, LT0REG,
|
||
LB0REG, LC1REG, LT1REG, LB1REG): Delete
|
||
(AXREG, AWREG, LCREG, LTREG, LBREG): Define.
|
||
(get_allreg): Change to new defines. Fallback to abort().
|
||
|
||
2011-02-14 Mike Frysinger <vapier@gentoo.org>
|
||
|
||
* bfin-dis.c: Add whitespace/parenthesis where needed.
|
||
|
||
2011-02-14 Mike Frysinger <vapier@gentoo.org>
|
||
|
||
* bfin-dis.c (decode_LoopSetup_0): Return when reg is greater
|
||
than 7.
|
||
|
||
2011-02-13 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
|
||
|
||
* configure: Regenerate.
|
||
|
||
2011-02-13 Mike Frysinger <vapier@gentoo.org>
|
||
|
||
* bfin-dis.c (decode_dsp32alu_0): Fix typo with A1 reg.
|
||
|
||
2011-02-13 Mike Frysinger <vapier@gentoo.org>
|
||
|
||
* bfin-dis.c (decode_dsp32mult_0): Add 1 to dst for mac1. Output
|
||
dregs only when P is set, and dregs_lo otherwise.
|
||
|
||
2011-02-13 Mike Frysinger <vapier@gentoo.org>
|
||
|
||
* bfin-dis.c (decode_dsp32alu_0): Delete BYTEOP2M code.
|
||
|
||
2011-02-12 Mike Frysinger <vapier@gentoo.org>
|
||
|
||
* bfin-dis.c (decode_pseudoDEBUG_0): Add space after PRNT.
|
||
|
||
2011-02-12 Mike Frysinger <vapier@gentoo.org>
|
||
|
||
* bfin-dis.c (machine_registers): Delete REG_GP.
|
||
(reg_names): Delete "GP".
|
||
(decode_allregs): Change REG_GP to REG_LASTREG.
|
||
|
||
2011-02-12 Mike Frysinger <vapier@gentoo.org>
|
||
|
||
* bfin-dis.c (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2,
|
||
M_IH, M_IU): Delete.
|
||
|
||
2011-02-11 Mike Frysinger <vapier@gentoo.org>
|
||
|
||
* bfin-dis.c (reg_names): Add const.
|
||
(decode_dregs_lo, decode_dregs_hi, decode_dregs, decode_dregs_byte,
|
||
decode_pregs, decode_iregs, decode_mregs, decode_dpregs, decode_gregs,
|
||
decode_regs, decode_regs_lo, decode_regs_hi, decode_statbits,
|
||
decode_counters, decode_allregs): Likewise.
|
||
|
||
2011-02-09 Michael Snyder <msnyder@vmware.com>
|
||
|
||
* i386-dis.c (OP_J): Parenthesize expression to prevent
|
||
truncated addresses.
|
||
(print_insn): Fix indentation off-by-one.
|
||
|
||
2011-02-01 Nick Clifton <nickc@redhat.com>
|
||
|
||
* po/da.po: Updated Danish translation.
|
||
|
||
2011-01-21 Dave Murphy <davem@devkitpro.org>
|
||
|
||
* ppc-opc.c (NON32, NO371): Remove PPC_OPCODE_PPCPS.
|
||
|
||
2011-01-18 H.J. Lu <hongjiu.lu@intel.com>
|
||
|
||
* i386-dis.c (sIbT): New.
|
||
(b_T_mode): Likewise.
|
||
(dis386): Replace sIb with sIbT on "pushT".
|
||
(x86_64_table): Replace sIb with Ib on "aam" and "aad".
|
||
(OP_sI): Handle b_T_mode. Properly sign-extend byte.
|
||
|
||
2011-01-18 Jan Kratochvil <jan.kratochvil@redhat.com>
|
||
|
||
* i386-init.h: Regenerated.
|
||
* i386-tbl.h: Regenerated
|
||
|
||
2011-01-17 Quentin Neill <quentin.neill@amd.com>
|
||
|
||
* i386-dis.c (REG_XOP_TBM_01): New.
|
||
(REG_XOP_TBM_02): New.
|
||
(reg_table): Add REG_XOP_TBM_01 and REG_XOP_TBM_02 tables.
|
||
(xop_table): Redirect to REG_XOP_TBM_01 and REG_XOP_TBM_02
|
||
entries, and add bextr instruction.
|
||
|
||
* i386-gen.c (cpu_flag_init): Add CPU_TBM_FLAGS, CpuTBM.
|
||
(cpu_flags): Add CpuTBM.
|
||
|
||
* i386-opc.h (CpuTBM) New.
|
||
(i386_cpu_flags): Add bit cputbm.
|
||
|
||
* i386-opc.tbl: Add bextr, blcfill, blci, blcic, blcmsk,
|
||
blcs, blsfill, blsic, t1mskc, and tzmsk.
|
||
|
||
2011-01-12 DJ Delorie <dj@redhat.com>
|
||
|
||
* rx-dis.c (print_insn_rx): Support RX_Operand_TwoReg.
|
||
|
||
2011-01-11 Mingjie Xing <mingjie.xing@gmail.com>
|
||
|
||
* mips-dis.c (print_insn_args): Adjust the value to print the real
|
||
offset for "+c" argument.
|
||
|
||
2011-01-10 Nick Clifton <nickc@redhat.com>
|
||
|
||
* po/da.po: Updated Danish translation.
|
||
|
||
2011-01-05 Nathan Sidwell <nathan@codesourcery.com>
|
||
|
||
* arm-dis.c (thumb32_opcodes): BLX must have bit zero clear.
|
||
|
||
2011-01-04 H.J. Lu <hongjiu.lu@intel.com>
|
||
|
||
* i386-dis.c (REG_VEX_38F3): New.
|
||
(PREFIX_0FBC): Likewise.
|
||
(PREFIX_VEX_38F2): Likewise.
|
||
(PREFIX_VEX_38F3_REG_1): Likewise.
|
||
(PREFIX_VEX_38F3_REG_2): Likewise.
|
||
(PREFIX_VEX_38F3_REG_3): Likewise.
|
||
(PREFIX_VEX_38F7): Likewise.
|
||
(VEX_LEN_38F2_P_0): Likewise.
|
||
(VEX_LEN_38F3_R_1_P_0): Likewise.
|
||
(VEX_LEN_38F3_R_2_P_0): Likewise.
|
||
(VEX_LEN_38F3_R_3_P_0): Likewise.
|
||
(VEX_LEN_38F7_P_0): Likewise.
|
||
(dis386_twobyte): Use PREFIX_0FBC.
|
||
(reg_table): Add REG_VEX_38F3.
|
||
(prefix_table): Add PREFIX_0FBC, PREFIX_VEX_38F2,
|
||
PREFIX_VEX_38F3_REG_1, PREFIX_VEX_38F3_REG_2,
|
||
PREFIX_VEX_38F3_REG_3 and PREFIX_VEX_38F7.
|
||
(vex_table): Use PREFIX_VEX_38F2, REG_VEX_38F3 and
|
||
PREFIX_VEX_38F7.
|
||
(vex_len_table): Add VEX_LEN_38F2_P_0, VEX_LEN_38F3_R_1_P_0,
|
||
VEX_LEN_38F3_R_2_P_0, VEX_LEN_38F3_R_3_P_0 and
|
||
VEX_LEN_38F7_P_0.
|
||
|
||
* i386-gen.c (cpu_flag_init): Add CPU_BMI_FLAGS.
|
||
(cpu_flags): Add CpuBMI.
|
||
|
||
* i386-opc.h (CpuBMI): New.
|
||
(i386_cpu_flags): Add cpubmi.
|
||
|
||
* i386-opc.tbl: Add andn, bextr, blsi, blsmsk, blsr and tzcnt.
|
||
* i386-init.h: Regenerated.
|
||
* i386-tbl.h: Likewise.
|
||
|
||
2011-01-04 H.J. Lu <hongjiu.lu@intel.com>
|
||
|
||
* i386-dis.c (VexGdq): New.
|
||
(OP_VEX): Handle dq_mode.
|
||
|
||
2011-01-01 H.J. Lu <hongjiu.lu@intel.com>
|
||
|
||
* i386-gen.c (process_copyright): Update copyright to 2011.
|
||
|
||
For older changes see ChangeLog-2010
|
||
|
||
Local Variables:
|
||
mode: change-log
|
||
left-margin: 8
|
||
fill-column: 74
|
||
version-control: never
|
||
End:
|