325 lines
13 KiB
C
325 lines
13 KiB
C
/* Assemble Matsushita MN10300 instructions.
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Copyright (C) 1996 Free Software Foundation, Inc.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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#include "ansidecl.h"
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#include "opcode/mn10300.h"
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/* Formats. Right now we don't use this. We probably will later for
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the size of the instruction and other random stuff. */
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#define FMT_S0 0
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#define FMT_S1 1
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#define FMT_S2 2
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#define FMT_S4 3
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#define FMT_S6 4
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#define FMT_D0 5
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#define FMT_D1 6
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#define FMT_D2 7
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#define FMT_D4 8
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#define FMT_D5 9
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/* Operands currently used. This is temporary. */
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#define DN 0
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#define DM 0
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#define AN 0
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#define AM 0
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#define IMM8 0
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#define IMM16 0
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#define IMM32 0
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#define D8 0
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#define FMT_D16 0
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#define UIMM8 0
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#define SP 0
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#define PSW 0
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#define D32 0
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#define MDR 0
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#define ABFMT_S16 0
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#define ABS32 0
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#define DI 0
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#define REGS 0
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const struct mn10300_operand mn10300_operands[] = {
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#define UNUSED 0
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{ 0, 0, 0 },
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} ;
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/* The opcode table.
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The format of the opcode table is:
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NAME OPCODE MASK { OPERANDS }
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NAME is the name of the instruction.
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OPCODE is the instruction opcode.
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MASK is the opcode mask; this is used to tell the disassembler
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which bits in the actual opcode must match OPCODE.
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OPERANDS is the list of operands.
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The disassembler reads the table in order and prints the first
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instruction which matches, so this table is sorted to put more
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specific instructions before more general instructions. It is also
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sorted by major opcode. */
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const struct mn10300_opcode mn10300_opcodes[] = {
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{ "mov", 0x8000, 0xf000, {FMT_S1, IMM8, DN}, },
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{ "mov", 0x80, 0xf0, {FMT_S0, DM, DN}, },
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{ "mov", 0xf1e0, 0xfff0, {FMT_D0, DM, AN}, },
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{ "mov", 0xf1d0, 0xfff0, {FMT_D0, AM, DN}, },
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{ "mov", 0x9000, 0xf000, {FMT_S1, IMM8, AN}, },
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{ "mov", 0x90, 0xf0, {FMT_S0, AM, AN}, },
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{ "mov", 0x3c, 0xfc, {FMT_S0, SP, AN}, },
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{ "mov", 0xf2f0, 0xfff3, {FMT_D0, AM, SP}, },
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{ "mov", 0xf2e4, 0xfffc, {FMT_D0, PSW, DN}, },
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{ "mov", 0xf2f3, 0xfff3, {FMT_D0, DM, PSW}, },
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{ "mov", 0xf2e0, 0xfffc, {FMT_D0, MDR, DN}, },
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{ "mov", 0xf2f2, 0xfff3, {FMT_D0, DM, MDR}, },
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{ "mov", 0x70, 0xf0, {FMT_S0, AM, DN}, },
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{ "mov", 0xf80000, 0xfff000, {FMT_D1, D8, AM, DN}, },
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{ "mov", 0xfa000000, 0xfff00000, {FMT_D2, FMT_D16, AM, DN}, },
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{ "mov", 0xfc000000, 0xfff00000, {FMT_D4, D32, AM, DN}, },
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{ "mov", 0x5800, 0xfc00, {FMT_S1, D8, SP, DN}, },
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{ "mov", 0xfab40000, 0xfffc0000, {FMT_D2, FMT_D16, SP, DN}, },
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{ "mov", 0xfcb40000, 0xfffc0000, {FMT_D4, D32, SP, DN}, },
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{ "mov", 0xf300, 0xffc0, {FMT_D0, DI, AM, DN}, },
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{ "mov", 0x300000, 0xfc0000, {FMT_S2, ABFMT_S16, DN}, },
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{ "mov", 0xfca40000, 0xfffc0000, {FMT_D4, ABS32, DN}, },
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{ "mov", 0xf000, 0xfff0, {FMT_D0, AM, AN}, },
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{ "mov", 0xf82000, 0xfff000, {FMT_D1, D8, AM, AN}, },
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{ "mov", 0xfa200000, 0xfff00000, {FMT_D2, FMT_D16, AM, AN}, },
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{ "mov", 0xfc200000, 0xfff00000, {FMT_D4, D32, AM, AN}, },
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{ "mov", 0x5c00, 0xfc00, {FMT_S1, D8, SP, AN}, },
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{ "mov", 0xfab00000, 0xfffc0000, {FMT_D2, FMT_D16, SP, AN}, },
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{ "mov", 0xfcd00000, 0xfffc0000, {FMT_D4, D32, SP, AN}, }, /* XXX */
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{ "mov", 0xf380, 0xffc0, {FMT_D0, DI, AM, AN}, },
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{ "mov", 0xfaa00000, 0xfffc0000, {FMT_D2, ABFMT_S16, AN}, },
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{ "mov", 0xfca00000, 0xfffc0000, {FMT_D4, ABS32, AN}, },
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{ "mov", 0xf8f000, 0xfffc00, {FMT_D1, D8, AM, SP}, },
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{ "mov", 0x60, 0xf0, {FMT_S0, DM, AN}, },
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{ "mov", 0xf81000, 0xfff000, {FMT_D1, DM, D8, AN}, },
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{ "mov", 0xfa100000, 0xfff00000, {FMT_D2, DM, FMT_D16, AN}, },
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{ "mov", 0xfc100000, 0xfff00000, {FMT_D4, DM, D32, AN}, },
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{ "mov", 0x4200, 0xf300, {FMT_S1, DM, D8, SP}, },
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{ "mov", 0xfa910000, 0xfff30000, {FMT_D2, DM, FMT_D16, SP}, },
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{ "mov", 0xfc910000, 0xfff30000, {FMT_D4, DM, D32, SP}, },
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{ "mov", 0xf340, 0xffc0, {FMT_D0, DM, DI, AN}, },
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{ "mov", 0x010000, 0xf30000, {FMT_S2, DM, ABFMT_S16}, },
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{ "mov", 0xfc810000, 0xfff30000, {FMT_D4, DM, ABS32}, },
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{ "mov", 0xf010, 0xfff0, {FMT_D0, AM, AN}, },
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{ "mov", 0xf83000, 0xfff000, {FMT_D1, AM, D8, AN}, },
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{ "mov", 0xfa300000, 0xfff00000, {FMT_D2, AM, FMT_D16, AN}, },
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{ "mov", 0xfc300000, 0xfff00000, {FMT_D4, AM, D32, AN}, },
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{ "mov", 0x4300, 0xf300, {FMT_S1, AM, D8, SP}, },
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{ "mov", 0xfa900000, 0xfff30000, {FMT_D2, AM, FMT_D16, SP}, },
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{ "mov", 0xfc900000, 0xfc930000, {FMT_D4, AM, D32, SP}, },
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{ "mov", 0xf3c0, 0xffc0, {FMT_D0, AM, DI, AN}, },
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{ "mov", 0xfa800000, 0xfff30000, {FMT_D2, AM, ABFMT_S16}, },
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{ "mov", 0xfc800000, 0xfff30000, {FMT_D4, AM, ABS32}, },
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{ "mov", 0xf8f400, 0xfffc00, {FMT_D1, SP, D8, AN}, },
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{ "mov", 0x2c0000, 0xfc0000, {FMT_S2, IMM16, DN}, },
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{ "mov", 0xfcdc0000, 0xfffc0000, {FMT_D4, IMM32, DN}, },
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{ "mov", 0x240000, 0xfc0000, {FMT_S2, IMM16, AN}, },
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{ "mov", 0xfcdc0000, 0xfffc0000, {FMT_D4, IMM32, AN}, },
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{ "movbu", 0xf040, 0xfff0, {FMT_D0, AM, DN}, },
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{ "movbu", 0xf84000, 0xfff000, {FMT_D1, D8, AM, DN}, },
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{ "movbu", 0xf8400000, 0xfff00000, {FMT_D2, FMT_D16, AM, DN}, },
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{ "movbu", 0xfc400000, 0xfff00000, {FMT_D4, D32, AM, DN}, },
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{ "movbu", 0xf8b800, 0xfffc00, {FMT_D1, D8, SP, DN}, },
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{ "movbu", 0xfab80000, 0xfffc0000, {FMT_D2, FMT_D16, SP, DN}, },
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{ "movbu", 0xfcd80000, 0xfffc0000, {FMT_D4, D32, SP, DN}, },
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{ "movbu", 0xf400, 0xffc0, {FMT_D0, DI, AM, DN}, },
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{ "movbu", 0x340000, 0xfc0000, {FMT_S2, ABFMT_S16, DN}, },
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{ "movbu", 0xfca80000, 0xfffc0000, {FMT_D4, ABS32, DN}, },
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{ "movbu", 0xf050, 0xfff0, {FMT_D0, DM, AN}, },
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{ "movbu", 0xf85000, 0xfff000, {FMT_D1, DM, D8, AN}, },
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{ "movbu", 0xfa500000, 0xfff00000, {FMT_D2, DM, FMT_D16, AN}, },
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{ "movbu", 0xfc500000, 0xfff00000, {FMT_D4, DM, D32, AN}, },
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{ "movbu", 0xf89200, 0xfff300, {FMT_D1, DM, D8, SP}, },
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{ "movbu", 0xfa920000, 0xfff30000, {FMT_D2, DM, FMT_D16, SP}, },
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{ "movbu", 0xfc920000, 0xfff30000, {FMT_D4, DM, D32, SP}, },
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{ "movbu", 0xf440, 0xffc0, {FMT_D0, DM, DI, AN}, },
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{ "movbu", 0x020000, 0xf30000, {FMT_S2, DM, ABFMT_S16}, },
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{ "movbu", 0xfc820000, 0xfff30000, {FMT_D4, DM, ABS32}, },
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{ "movhu", 0xf060, 0xfff0, {FMT_D0, AM, DN}, },
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{ "movhu", 0xf86000, 0xfff000, {FMT_D1, D8, AM, DN}, },
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{ "movhu", 0xfa600000, 0xfff00000, {FMT_D2, FMT_D16, AM, DN}, },
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{ "movhu", 0xfc600000, 0xfff00000, {FMT_D4, D32, AM, DN}, },
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{ "movhu", 0xf8bc00, 0xfffc00, {FMT_D1, D8, SP, DN}, },
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{ "movhu", 0xfabc0000, 0xfffc0000, {FMT_D2, FMT_D16, SP, DN}, },
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{ "movhu", 0xfcdc0000, 0xfffc0000, {FMT_D4, D32, SP, DN}, }, /* XXX */
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{ "movhu", 0xf480, 0xffc0, {FMT_D0, DI, AM, DN}, },
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{ "movhu", 0xc80000, 0xfc0000, {FMT_S2, ABFMT_S16, DN}, },
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{ "movhu", 0xfcac0000, 0xfffc0000, {FMT_D4, ABS32, DN}, },
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{ "movhu", 0xf070, 0xfff0, {FMT_D0, DM, AN}, },
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{ "movhu", 0xf87000, 0xfff000, {FMT_D1, DM, D8, AN}, },
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{ "movhu", 0xfa700000, 0xfff00000, {FMT_D2, DM, FMT_D16, AN}, },
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{ "movhu", 0xfc700000, 0xfff00000, {FMT_D4, DM, D32, AN}, },
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{ "movhu", 0xf89300, 0xfff300, {FMT_D1, DM, D8, SP}, },
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{ "movhu", 0xfa930000, 0xfff30000, {FMT_D2, DM, FMT_D16, SP}, },
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{ "movhu", 0xfa930000, 0xfff30000, {FMT_D4, DM, D32, SP}, },
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{ "movhu", 0xf4c0, 0xffc0, {FMT_D0, DM, DI, AN}, },
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{ "movhu", 0x030000, 0xf30000, {FMT_S2, DM, ABFMT_S16}, },
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{ "movhu", 0xfc830000, 0xfff30000, {FMT_D4, DM, ABS32}, },
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{ "ext", 0xf2d0, 0xfffc, {FMT_D0, DN}, },
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{ "extb", 0x10, 0xfc, {FMT_S0, DN}, },
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{ "extbu", 0x14, 0xfc, {FMT_S0, DN}, },
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{ "exth", 0x18, 0xfc, {FMT_S0, DN}, },
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{ "exthu", 0x1c, 0xfc, {FMT_S0, DN}, },
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{ "movm", 0xce00, 0xff00, {FMT_S1, SP, REGS}, },
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{ "movm", 0xcf00, 0xff00, {FMT_S1, REGS, SP}, },
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{ "clr", 0x00, 0xf3, {FMT_S0, DN}, },
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{ "add", 0xe0, 0xf0, {FMT_S0, DM, DN}, },
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{ "add", 0xf160, 0xfff0, {FMT_D0, DM, AN}, },
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{ "add", 0xf150, 0xfff0, {FMT_D0, AM, DN}, },
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{ "add", 0xf170, 0xfff0, {FMT_D0, AM, AN}, },
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{ "add", 0x2800, 0xfc00, {FMT_S1, IMM8, DN}, },
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{ "add", 0xfac00000, 0xfffc0000, {FMT_D2, IMM16, DN}, },
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{ "add", 0xfcc00000, 0xfffc0000, {FMT_D4, IMM32, DN}, },
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{ "add", 0x2000, 0xfc00, {FMT_S1, IMM8, AN}, },
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{ "add", 0xfad00000, 0xfffc0000, {FMT_D2, IMM16, AN}, },
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{ "add", 0xfcd00000, 0xfffc0000, {FMT_D4, IMM32, AN}, },
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{ "add", 0xf8fe00, 0xffff00, {FMT_D1, IMM8, SP}, },
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{ "add", 0xfafe0000, 0xfffc0000, {FMT_D2, IMM16, SP}, },
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{ "add", 0xfcfe0000, 0xfff0000, {FMT_D4, IMM32, SP}, },
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{ "addc", 0xf140, 0xfff0, {FMT_D0, DM, DN}, },
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{ "sub", 0xf100, 0xfff0, {FMT_D0, DM, DN}, },
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{ "sub", 0xf120, 0xfff0, {FMT_D0, DM, AN}, },
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{ "sub", 0xf110, 0xfff0, {FMT_D0, AM, DN}, },
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{ "sub", 0xf130, 0xfff0, {FMT_D0, AM, AN}, },
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{ "sub", 0xfcc40000, 0xfffc0000, {FMT_D4, IMM32, DN}, },
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{ "sub", 0xfcd80000, 0xfffc0000, {FMT_D4, IMM32, AN}, },
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{ "subc", 0xf180, 0xfff0, {FMT_D0, DM, DN}, },
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{ "mul", 0xf240, 0xfff0, {FMT_D0, DM, DN}, },
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{ "mulu", 0xf250, 0xfff0, {FMT_D0, DM, DN}, },
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{ "div", 0xf260, 0xfff0, {FMT_D0, DM, DN}, },
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{ "divu", 0xf270, 0xfff0, {FMT_D0, DM, DN}, },
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{ "inc", 0x40, 0xf3, {FMT_S0, DN}, },
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{ "inc", 0x41, 0xf3, {FMT_S0, AN}, },
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{ "inc4", 0x50, 0xfc, {FMT_S0, AN}, },
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{ "cmp", 0xa000, 0xf000, {FMT_S1, IMM8, DN}, },
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{ "cmp", 0xa0, 0xf0, {FMT_S0, DM, DN}, },
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{ "cmp", 0xf1a0, 0xfff0, {FMT_D0, DM, AN}, },
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{ "cmp", 0xf190, 0xfff0, {FMT_D0, AM, DN}, },
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{ "cmp", 0xb000, 0xf000, {FMT_S1, IMM8, AN}, },
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{ "cmp", 0xb0, 0xf0, {FMT_S0, AM, AN}, },
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{ "cmp", 0xfac80000, 0xfffc0000, {FMT_D2, IMM16, DN}, },
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{ "cmp", 0xfcc80000, 0xfffc0000, {FMT_D4, IMM32, DN}, },
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{ "cmp", 0xfad80000, 0xfffc0000, {FMT_D2, IMM16, AN}, },
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{ "cmp", 0xfcd80000, 0xfffc0000, {FMT_D4, IMM32, AN}, },
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{ "and", 0xf200, 0xfff0, {FMT_D0, DM, DN}, },
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{ "and", 0xf8e000, 0xfffc00, {FMT_D1, IMM8, DN}, },
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{ "and", 0xfae00000, 0xfffc0000, {FMT_D2, IMM16, DN}, },
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{ "and", 0xfce00000, 0xfffc0000, {FMT_D4, IMM32, DN}, },
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{ "and", 0xfafc0000, 0xfffc0000, {FMT_D2, IMM16, PSW}, },
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{ "or", 0xf210, 0xfff0, {FMT_D0, DM, DN}, },
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{ "or", 0xf8e400, 0xfffc00, {FMT_D1, IMM8, DN}, },
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{ "or", 0xfae40000, 0xfffc0000, {FMT_D2, IMM16, DN}, },
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{ "or", 0xfce40000, 0xfffc0000, {FMT_D4, IMM32, DN}, },
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{ "or", 0xfafd0000, 0xfffc0000, {FMT_D2, IMM16, PSW}, },
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{ "xor", 0xf220, 0xfff0, {FMT_D0, DM, DN}, },
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{ "xor", 0xfae80000, 0xfffc0000, {FMT_D2, IMM16, DN}, },
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{ "xor", 0xfce80000, 0xfffc0000, {FMT_D4, IMM32, DN}, },
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{ "not", 0xf230, 0xfffc, {FMT_D0, DN}, },
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{ "btst", 0xf8ec00, 0xfffc00, {FMT_D1, IMM8, DN}, },
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{ "btst", 0xfaec0000, 0xfffc0000, {FMT_D2, IMM16, DN}, },
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{ "btst", 0xfcec0000, 0xfffc0000, {FMT_D4, IMM32, DN}, },
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{ "btst", 0xfaf80000, 0xfffc0000, {FMT_D2, IMM8, D8, AN}, },
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{ "btst", 0xfe020000, 0xffff0000, {FMT_D5, IMM8, ABS32}, },
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{ "bset", 0xf080, 0xfff0, {FMT_D0, DM, AN}, },
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{ "bset", 0xfaf00000, 0xfffc0000, {FMT_D2, IMM8, D8, AN}, },
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{ "bset", 0xfe000000, 0xffff0000, {FMT_D5, IMM8, ABS32}, },
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{ "bclr", 0xf090, 0xfff0, {FMT_D0, DM, AN}, },
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{ "bclr", 0xfaf40000, 0xfffc0000, {FMT_D2, IMM8, D8, AN}, },
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{ "bclr", 0xfe010000, 0xffff0000, {FMT_D5, IMM8, ABS32}, },
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{ "asr", 0xf2b0, 0xfff0, {FMT_D0, DM, DN}, },
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{ "asr", 0xf8c800, 0xfffc00, {FMT_D1, UIMM8, DN}, },
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{ "lsr", 0xf2a0, 0xfff0, {FMT_D0, DM, DN}, },
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{ "lsr", 0xf8c4, 0xfffc00, {FMT_D0, UIMM8, DN}, },
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{ "asl", 0xf290, 0xfff0, {FMT_D0, DM, DN}, },
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{ "asl", 0xf8c000, 0xfffc00, {FMT_D0, UIMM8, DN}, },
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{ "asl2", 0x54, 0xfc, {FMT_S0, DN}, },
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{ "ror", 0xf284, 0xfffc, {FMT_D0, DN}, },
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{ "rol", 0xf280, 0xfffc, {FMT_D0, DN}, },
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{ "beq", 0xc800, 0xff00, {FMT_S1, D8}, },
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{ "bne", 0xc900, 0xff00, {FMT_S1, D8}, },
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{ "bgt", 0xc100, 0xff00, {FMT_S1, D8}, },
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{ "bge", 0xc200, 0xff00, {FMT_S1, D8}, },
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{ "ble", 0xc300, 0xff00, {FMT_S1, D8}, },
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{ "blt", 0xc000, 0xff00, {FMT_S1, D8}, },
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{ "bhi", 0xc500, 0xff00, {FMT_S1, D8}, },
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{ "bcc", 0xc600, 0xff00, {FMT_S1, D8}, },
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{ "bls", 0xc700, 0xff00, {FMT_S1, D8}, },
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{ "bcs", 0xc400, 0xff00, {FMT_S1, D8}, },
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{ "bvc", 0xf8e800, 0xffff00, {FMT_D1, D8}, },
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{ "bvs", 0xf8e900, 0xffff00, {FMT_D1, D8}, },
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{ "bnc", 0xf8ea00, 0xffff00, {FMT_D1, D8}, },
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{ "bns", 0xf8eb00, 0xffff00, {FMT_D1, D8}, },
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||
{ "bra", 0xca00, 0xff00, {FMT_S1, D8}, },
|
||
|
||
{ "leq", 0xd8, 0xff, {FMT_S0}, },
|
||
{ "lne", 0xd9, 0xff, {FMT_S0}, },
|
||
{ "lgt", 0xd1, 0xff, {FMT_S0}, },
|
||
{ "lge", 0xd2, 0xff, {FMT_S0}, },
|
||
{ "lle", 0xd3, 0xff, {FMT_S0}, },
|
||
{ "llt", 0xd0, 0xff, {FMT_S0}, },
|
||
{ "lhi", 0xd5, 0xff, {FMT_S0}, },
|
||
{ "lcc", 0xd6, 0xff, {FMT_S0}, },
|
||
{ "lls", 0xd7, 0xff, {FMT_S0}, },
|
||
{ "lcs", 0xd4, 0xff, {FMT_S0}, },
|
||
{ "lra", 0xda, 0xff, {FMT_S0}, },
|
||
{ "lcc", 0xd6, 0xff, {FMT_S0}, },
|
||
{ "setlb", 0xdb, 0xff, {FMT_S0}, },
|
||
|
||
{ "jmp", 0xf0f4, 0xfffc, {FMT_D0, AN}, },
|
||
{ "jmp", 0xcc0000, 0xff0000, {FMT_S2, FMT_D16}, },
|
||
{ "jmp", 0xdc0000, 0xff0000, {FMT_S4, D32}, },
|
||
{ "call", 0, 0, {FMT_S4, FMT_D16,}, },
|
||
{ "call", 0xdd000000, 0xff000000, {FMT_S6, D32,}, },
|
||
{ "calls", 0xf0f0, 0xfffc, {FMT_D0, AN}, },
|
||
{ "calls", 0xfaff0000, 0xffff0000, {FMT_D2, FMT_D16}, },
|
||
{ "calls", 0xfcff0000, 0xffff0000, {FMT_D4, D32}, },
|
||
|
||
{ "ret", 0xdf0000, 0xff00000, {FMT_S2}, },
|
||
{ "retf", 0xde0000, 0xff00000, {FMT_S2}, },
|
||
{ "rets", 0xf0fc, 0xffff, {FMT_D0}, },
|
||
{ "rti", 0xf0fd, 0xffff, {FMT_D0}, },
|
||
{ "trap", 0xf0fe, 0xffff, {FMT_D0}, },
|
||
{ "rtm", 0xf0ff, 0xffff, {FMT_D0}, },
|
||
{ "nop", 0xcb, 0xff, {FMT_S0}, },
|
||
/* { "udf", 0, 0, {0}, }, */
|
||
} ;
|
||
|
||
const int mn10300_num_opcodes =
|
||
sizeof (mn10300_opcodes) / sizeof (mn10300_opcodes[0]);
|
||
|
||
|