241 lines
8.0 KiB
C
241 lines
8.0 KiB
C
/* CPU data header for m32r.
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THIS FILE IS MACHINE GENERATED WITH CGEN.
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Copyright 1996-2005 Free Software Foundation, Inc.
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This file is part of the GNU Binutils and/or GDB, the GNU debugger.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2, or (at your option)
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any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License along
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with this program; if not, write to the Free Software Foundation, Inc.,
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51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
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*/
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#ifndef M32R_CPU_H
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#define M32R_CPU_H
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#define CGEN_ARCH m32r
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/* Given symbol S, return m32r_cgen_<S>. */
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#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
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#define CGEN_SYM(s) m32r##_cgen_##s
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#else
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#define CGEN_SYM(s) m32r/**/_cgen_/**/s
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#endif
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/* Selected cpu families. */
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#define HAVE_CPU_M32RBF
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#define HAVE_CPU_M32RXF
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#define HAVE_CPU_M32R2F
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#define CGEN_INSN_LSB0_P 0
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/* Minimum size of any insn (in bytes). */
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#define CGEN_MIN_INSN_SIZE 2
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/* Maximum size of any insn (in bytes). */
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#define CGEN_MAX_INSN_SIZE 4
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#define CGEN_INT_INSN_P 1
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/* Maximum number of syntax elements in an instruction. */
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#define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 15
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/* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands.
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e.g. In "b,a foo" the ",a" is an operand. If mnemonics have operands
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we can't hash on everything up to the space. */
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#define CGEN_MNEMONIC_OPERANDS
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/* Maximum number of fields in an instruction. */
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#define CGEN_ACTUAL_MAX_IFMT_OPERANDS 7
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/* Enums. */
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/* Enum declaration for insn format enums. */
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typedef enum insn_op1 {
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OP1_0, OP1_1, OP1_2, OP1_3
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, OP1_4, OP1_5, OP1_6, OP1_7
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, OP1_8, OP1_9, OP1_10, OP1_11
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, OP1_12, OP1_13, OP1_14, OP1_15
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} INSN_OP1;
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/* Enum declaration for op2 enums. */
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typedef enum insn_op2 {
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OP2_0, OP2_1, OP2_2, OP2_3
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, OP2_4, OP2_5, OP2_6, OP2_7
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, OP2_8, OP2_9, OP2_10, OP2_11
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, OP2_12, OP2_13, OP2_14, OP2_15
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} INSN_OP2;
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/* Enum declaration for . */
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typedef enum gr_names {
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H_GR_FP = 13, H_GR_LR = 14, H_GR_SP = 15, H_GR_R0 = 0
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, H_GR_R1 = 1, H_GR_R2 = 2, H_GR_R3 = 3, H_GR_R4 = 4
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, H_GR_R5 = 5, H_GR_R6 = 6, H_GR_R7 = 7, H_GR_R8 = 8
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, H_GR_R9 = 9, H_GR_R10 = 10, H_GR_R11 = 11, H_GR_R12 = 12
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, H_GR_R13 = 13, H_GR_R14 = 14, H_GR_R15 = 15
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} GR_NAMES;
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/* Enum declaration for . */
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typedef enum cr_names {
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H_CR_PSW = 0, H_CR_CBR = 1, H_CR_SPI = 2, H_CR_SPU = 3
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, H_CR_BPC = 6, H_CR_BBPSW = 8, H_CR_BBPC = 14, H_CR_EVB = 5
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, H_CR_CR0 = 0, H_CR_CR1 = 1, H_CR_CR2 = 2, H_CR_CR3 = 3
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, H_CR_CR4 = 4, H_CR_CR5 = 5, H_CR_CR6 = 6, H_CR_CR7 = 7
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, H_CR_CR8 = 8, H_CR_CR9 = 9, H_CR_CR10 = 10, H_CR_CR11 = 11
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, H_CR_CR12 = 12, H_CR_CR13 = 13, H_CR_CR14 = 14, H_CR_CR15 = 15
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} CR_NAMES;
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/* Attributes. */
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/* Enum declaration for machine type selection. */
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typedef enum mach_attr {
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MACH_BASE, MACH_M32R, MACH_M32RX, MACH_M32R2
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, MACH_MAX
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} MACH_ATTR;
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/* Enum declaration for instruction set selection. */
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typedef enum isa_attr {
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ISA_M32R, ISA_MAX
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} ISA_ATTR;
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/* Enum declaration for parallel execution pipeline selection. */
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typedef enum pipe_attr {
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PIPE_NONE, PIPE_O, PIPE_S, PIPE_OS
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, PIPE_O_OS
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} PIPE_ATTR;
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/* Number of architecture variants. */
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#define MAX_ISAS 1
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#define MAX_MACHS ((int) MACH_MAX)
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/* Ifield support. */
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/* Ifield attribute indices. */
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/* Enum declaration for cgen_ifld attrs. */
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typedef enum cgen_ifld_attr {
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CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED
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, CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_RELOC, CGEN_IFLD_END_BOOLS
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, CGEN_IFLD_START_NBOOLS = 31, CGEN_IFLD_MACH, CGEN_IFLD_END_NBOOLS
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} CGEN_IFLD_ATTR;
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/* Number of non-boolean elements in cgen_ifld_attr. */
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#define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1)
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/* Enum declaration for m32r ifield types. */
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typedef enum ifield_type {
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M32R_F_NIL, M32R_F_ANYOF, M32R_F_OP1, M32R_F_OP2
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, M32R_F_COND, M32R_F_R1, M32R_F_R2, M32R_F_SIMM8
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, M32R_F_SIMM16, M32R_F_SHIFT_OP2, M32R_F_UIMM3, M32R_F_UIMM4
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, M32R_F_UIMM5, M32R_F_UIMM8, M32R_F_UIMM16, M32R_F_UIMM24
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, M32R_F_HI16, M32R_F_DISP8, M32R_F_DISP16, M32R_F_DISP24
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, M32R_F_OP23, M32R_F_OP3, M32R_F_ACC, M32R_F_ACCS
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, M32R_F_ACCD, M32R_F_BITS67, M32R_F_BIT4, M32R_F_BIT14
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, M32R_F_IMM1, M32R_F_MAX
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} IFIELD_TYPE;
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#define MAX_IFLD ((int) M32R_F_MAX)
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/* Hardware attribute indices. */
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/* Enum declaration for cgen_hw attrs. */
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typedef enum cgen_hw_attr {
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CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE
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, CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_END_NBOOLS
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} CGEN_HW_ATTR;
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/* Number of non-boolean elements in cgen_hw_attr. */
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#define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1)
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/* Enum declaration for m32r hardware types. */
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typedef enum cgen_hw_type {
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HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR
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, HW_H_IADDR, HW_H_PC, HW_H_HI16, HW_H_SLO16
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, HW_H_ULO16, HW_H_GR, HW_H_CR, HW_H_ACCUM
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, HW_H_ACCUMS, HW_H_COND, HW_H_PSW, HW_H_BPSW
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, HW_H_BBPSW, HW_H_LOCK, HW_MAX
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} CGEN_HW_TYPE;
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#define MAX_HW ((int) HW_MAX)
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/* Operand attribute indices. */
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/* Enum declaration for cgen_operand attrs. */
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typedef enum cgen_operand_attr {
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CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT
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, CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY
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, CGEN_OPERAND_RELOC, CGEN_OPERAND_HASH_PREFIX, CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31
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, CGEN_OPERAND_MACH, CGEN_OPERAND_END_NBOOLS
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} CGEN_OPERAND_ATTR;
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/* Number of non-boolean elements in cgen_operand_attr. */
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#define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1)
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/* Enum declaration for m32r operand types. */
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typedef enum cgen_operand_type {
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M32R_OPERAND_PC, M32R_OPERAND_SR, M32R_OPERAND_DR, M32R_OPERAND_SRC1
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, M32R_OPERAND_SRC2, M32R_OPERAND_SCR, M32R_OPERAND_DCR, M32R_OPERAND_SIMM8
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, M32R_OPERAND_SIMM16, M32R_OPERAND_UIMM3, M32R_OPERAND_UIMM4, M32R_OPERAND_UIMM5
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, M32R_OPERAND_UIMM8, M32R_OPERAND_UIMM16, M32R_OPERAND_IMM1, M32R_OPERAND_ACCD
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, M32R_OPERAND_ACCS, M32R_OPERAND_ACC, M32R_OPERAND_HASH, M32R_OPERAND_HI16
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, M32R_OPERAND_SLO16, M32R_OPERAND_ULO16, M32R_OPERAND_UIMM24, M32R_OPERAND_DISP8
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, M32R_OPERAND_DISP16, M32R_OPERAND_DISP24, M32R_OPERAND_CONDBIT, M32R_OPERAND_ACCUM
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, M32R_OPERAND_MAX
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} CGEN_OPERAND_TYPE;
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/* Number of operands types. */
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#define MAX_OPERANDS 28
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/* Maximum number of operands referenced by any insn. */
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#define MAX_OPERAND_INSTANCES 11
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/* Insn attribute indices. */
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/* Enum declaration for cgen_insn attrs. */
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typedef enum cgen_insn_attr {
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CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI
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, CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED
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, CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_FILL_SLOT, CGEN_INSN_SPECIAL
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, CGEN_INSN_SPECIAL_M32R, CGEN_INSN_SPECIAL_FLOAT, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31
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, CGEN_INSN_MACH, CGEN_INSN_PIPE, CGEN_INSN_END_NBOOLS
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} CGEN_INSN_ATTR;
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/* Number of non-boolean elements in cgen_insn_attr. */
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#define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1)
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/* cgen.h uses things we just defined. */
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#include "opcode/cgen.h"
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extern const struct cgen_ifld m32r_cgen_ifld_table[];
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/* Attributes. */
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extern const CGEN_ATTR_TABLE m32r_cgen_hardware_attr_table[];
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extern const CGEN_ATTR_TABLE m32r_cgen_ifield_attr_table[];
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extern const CGEN_ATTR_TABLE m32r_cgen_operand_attr_table[];
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extern const CGEN_ATTR_TABLE m32r_cgen_insn_attr_table[];
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/* Hardware decls. */
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extern CGEN_KEYWORD m32r_cgen_opval_gr_names;
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extern CGEN_KEYWORD m32r_cgen_opval_cr_names;
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extern CGEN_KEYWORD m32r_cgen_opval_h_accums;
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extern const CGEN_HW_ENTRY m32r_cgen_hw_table[];
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#endif /* M32R_CPU_H */
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