253 lines
9.8 KiB
Plaintext
253 lines
9.8 KiB
Plaintext
/* -- dis.c */
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#undef CGEN_PRINT_INSN
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#define CGEN_PRINT_INSN my_print_insn
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static int
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my_print_insn (pc, info, buf, buflen)
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bfd_vma pc;
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disassemble_info *info;
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char *buf;
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int buflen;
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{
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/* 32 bit insn? */
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if ((pc & 3) == 0 && (buf[0] & 0x80) != 0)
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return print_insn (pc, info, buf, buflen);
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/* Print the first insn. */
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if ((pc & 3) == 0)
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{
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if (print_insn (pc, info, buf, 16) == 0)
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(*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
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buf += 2;
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}
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if (buf[0] & 0x80)
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{
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/* Parallel. */
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(*info->fprintf_func) (info->stream, " || ");
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buf[0] &= 0x7f;
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}
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else
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(*info->fprintf_func) (info->stream, " -> ");
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/* The "& 3" is to ensure the branch address is computed correctly
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[if it is a branch]. */
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if (print_insn (pc & ~ (bfd_vma) 3, info, buf, 16) == 0)
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(*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
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return (pc & 3) ? 2 : 4;
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}
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/* -- */
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/* Main entry point for operand extraction.
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This function is basically just a big switch statement. Earlier versions
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used tables to look up the function to use, but
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- if the table contains both assembler and disassembler functions then
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the disassembler contains much of the assembler and vice-versa,
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- there's a lot of inlining possibilities as things grow,
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- using a switch statement avoids the function call overhead.
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This function could be moved into `print_insn_normal', but keeping it
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separate makes clear the interface between `print_insn_normal' and each of
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the handlers.
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*/
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CGEN_INLINE int
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m32r_cgen_extract_operand (opindex, buf_ctrl, insn_value, fields)
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int opindex;
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void *buf_ctrl;
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cgen_insn_t insn_value;
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CGEN_FIELDS *fields;
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{
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int length;
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switch (opindex)
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{
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case M32R_OPERAND_SR :
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length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 12, 4, 0, CGEN_FIELDS_BITSIZE (fields), &fields->f_r2);
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break;
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case M32R_OPERAND_DR :
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length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 4, 4, 0, CGEN_FIELDS_BITSIZE (fields), &fields->f_r1);
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break;
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case M32R_OPERAND_SRC1 :
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length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 4, 4, 0, CGEN_FIELDS_BITSIZE (fields), &fields->f_r1);
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break;
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case M32R_OPERAND_SRC2 :
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length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 12, 4, 0, CGEN_FIELDS_BITSIZE (fields), &fields->f_r2);
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break;
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case M32R_OPERAND_SCR :
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length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 12, 4, 0, CGEN_FIELDS_BITSIZE (fields), &fields->f_r2);
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break;
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case M32R_OPERAND_DCR :
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length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 4, 4, 0, CGEN_FIELDS_BITSIZE (fields), &fields->f_r1);
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break;
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case M32R_OPERAND_SIMM8 :
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length = extract_normal (NULL /*FIXME*/, insn_value, 0, 8, 8, 0, CGEN_FIELDS_BITSIZE (fields), &fields->f_simm8);
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break;
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case M32R_OPERAND_SIMM16 :
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length = extract_normal (NULL /*FIXME*/, insn_value, 0, 16, 16, 0, CGEN_FIELDS_BITSIZE (fields), &fields->f_simm16);
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break;
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case M32R_OPERAND_UIMM4 :
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length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 12, 4, 0, CGEN_FIELDS_BITSIZE (fields), &fields->f_uimm4);
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break;
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case M32R_OPERAND_UIMM5 :
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length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 11, 5, 0, CGEN_FIELDS_BITSIZE (fields), &fields->f_uimm5);
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break;
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case M32R_OPERAND_UIMM16 :
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length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 16, 16, 0, CGEN_FIELDS_BITSIZE (fields), &fields->f_uimm16);
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break;
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case M32R_OPERAND_ACC_S :
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length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 12, 2, 0, CGEN_FIELDS_BITSIZE (fields), &fields->f_acc_s);
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break;
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case M32R_OPERAND_ACC :
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length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 8, 1, 0, CGEN_FIELDS_BITSIZE (fields), &fields->f_acc);
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break;
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case M32R_OPERAND_HI16 :
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length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_UNSIGNED), 16, 16, 0, CGEN_FIELDS_BITSIZE (fields), &fields->f_hi16);
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break;
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case M32R_OPERAND_SLO16 :
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length = extract_normal (NULL /*FIXME*/, insn_value, 0, 16, 16, 0, CGEN_FIELDS_BITSIZE (fields), &fields->f_simm16);
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break;
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case M32R_OPERAND_ULO16 :
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length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 16, 16, 0, CGEN_FIELDS_BITSIZE (fields), &fields->f_uimm16);
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break;
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case M32R_OPERAND_UIMM24 :
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length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_ABS_ADDR)|(1<<CGEN_OPERAND_UNSIGNED), 8, 24, 0, CGEN_FIELDS_BITSIZE (fields), &fields->f_uimm24);
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break;
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case M32R_OPERAND_DISP8 :
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length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), 8, 8, 2, CGEN_FIELDS_BITSIZE (fields), &fields->f_disp8);
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break;
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case M32R_OPERAND_DISP16 :
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length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), 16, 16, 2, CGEN_FIELDS_BITSIZE (fields), &fields->f_disp16);
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break;
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case M32R_OPERAND_DISP24 :
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length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), 8, 24, 2, CGEN_FIELDS_BITSIZE (fields), &fields->f_disp24);
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break;
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default :
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fprintf (stderr, "Unrecognized field %d while decoding insn.\n",
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opindex);
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abort ();
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}
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return length;
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}
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/* Main entry point for printing operands.
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This function is basically just a big switch statement. Earlier versions
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used tables to look up the function to use, but
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- if the table contains both assembler and disassembler functions then
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the disassembler contains much of the assembler and vice-versa,
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- there's a lot of inlining possibilities as things grow,
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- using a switch statement avoids the function call overhead.
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This function could be moved into `print_insn_normal', but keeping it
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separate makes clear the interface between `print_insn_normal' and each of
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the handlers.
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*/
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CGEN_INLINE void
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m32r_cgen_print_operand (opindex, info, fields, attrs, pc, length)
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int opindex;
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disassemble_info *info;
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CGEN_FIELDS *fields;
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void const * attrs;
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bfd_vma pc;
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int length;
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{
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switch (opindex)
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{
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case M32R_OPERAND_SR :
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print_keyword (info, & m32r_cgen_opval_h_gr, fields->f_r2, 0|(1<<CGEN_OPERAND_UNSIGNED));
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break;
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case M32R_OPERAND_DR :
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print_keyword (info, & m32r_cgen_opval_h_gr, fields->f_r1, 0|(1<<CGEN_OPERAND_UNSIGNED));
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break;
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case M32R_OPERAND_SRC1 :
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print_keyword (info, & m32r_cgen_opval_h_gr, fields->f_r1, 0|(1<<CGEN_OPERAND_UNSIGNED));
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break;
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case M32R_OPERAND_SRC2 :
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print_keyword (info, & m32r_cgen_opval_h_gr, fields->f_r2, 0|(1<<CGEN_OPERAND_UNSIGNED));
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break;
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case M32R_OPERAND_SCR :
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print_keyword (info, & m32r_cgen_opval_h_cr, fields->f_r2, 0|(1<<CGEN_OPERAND_UNSIGNED));
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break;
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case M32R_OPERAND_DCR :
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print_keyword (info, & m32r_cgen_opval_h_cr, fields->f_r1, 0|(1<<CGEN_OPERAND_UNSIGNED));
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break;
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case M32R_OPERAND_SIMM8 :
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print_normal (info, fields->f_simm8, 0, pc, length);
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break;
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case M32R_OPERAND_SIMM16 :
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print_normal (info, fields->f_simm16, 0, pc, length);
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break;
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case M32R_OPERAND_UIMM4 :
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print_normal (info, fields->f_uimm4, 0|(1<<CGEN_OPERAND_UNSIGNED), pc, length);
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break;
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case M32R_OPERAND_UIMM5 :
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print_normal (info, fields->f_uimm5, 0|(1<<CGEN_OPERAND_UNSIGNED), pc, length);
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break;
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case M32R_OPERAND_UIMM16 :
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print_normal (info, fields->f_uimm16, 0|(1<<CGEN_OPERAND_UNSIGNED), pc, length);
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break;
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case M32R_OPERAND_ACC_S :
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print_keyword (info, & m32r_cgen_opval_h_accums, fields->f_acc_s, 0|(1<<CGEN_OPERAND_UNSIGNED));
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break;
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case M32R_OPERAND_ACC :
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print_keyword (info, & m32r_cgen_opval_h_accums, fields->f_acc, 0|(1<<CGEN_OPERAND_UNSIGNED));
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break;
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case M32R_OPERAND_HI16 :
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print_normal (info, fields->f_hi16, 0|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_UNSIGNED), pc, length);
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break;
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case M32R_OPERAND_SLO16 :
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print_normal (info, fields->f_simm16, 0, pc, length);
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break;
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case M32R_OPERAND_ULO16 :
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print_normal (info, fields->f_uimm16, 0|(1<<CGEN_OPERAND_UNSIGNED), pc, length);
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break;
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case M32R_OPERAND_UIMM24 :
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print_normal (info, fields->f_uimm24, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_ABS_ADDR)|(1<<CGEN_OPERAND_UNSIGNED), pc, length);
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break;
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case M32R_OPERAND_DISP8 :
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print_normal (info, fields->f_disp8, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
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break;
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case M32R_OPERAND_DISP16 :
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print_normal (info, fields->f_disp16, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
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break;
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case M32R_OPERAND_DISP24 :
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print_normal (info, fields->f_disp24, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
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break;
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default :
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fprintf (stderr, "Unrecognized field %d while printing insn.\n",
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opindex);
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abort ();
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}
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}
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cgen_extract_fn *m32r_cgen_extract_handlers[] = {
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0, /* default */
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extract_insn_normal,
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};
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cgen_print_fn *m32r_cgen_print_handlers[] = {
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0, /* default */
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print_insn_normal,
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};
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void
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m32r_cgen_init_dis (mach, endian)
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int mach;
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enum cgen_endian endian;
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{
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m32r_cgen_init_tables (mach);
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cgen_set_cpu (& m32r_cgen_opcode_data, mach, endian);
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cgen_dis_init ();
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}
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