binutils-gdb/cpu
Stafford Horne a2e4218f23 cpu/or1k: Update fpu compare symbols to imply set flag
The fpu compare symbols where not including 'sf' in the mnemonic.  So
instead of `lf-sfeq` (implying set flag if operands are equal) we were
having `lf-eq`.   This patch adds the 'sf'.  This helps with making the
generated CGEN documentation consistent and ordered correctly.

cpu/ChangeLog:

yyyy-mm-dd  Stafford Horne  <shorne@gmail.com>

	* or1korfpx.cpu (float-setflag-insn-base): Add 'sf' to symbol.
2019-06-13 06:16:19 +09:00
..
bpf.cpu cpu: add eBPF cpu description 2019-05-23 19:33:50 +02:00
bpf.opc cpu: add eBPF cpu description 2019-05-23 19:33:50 +02:00
ChangeLog cpu/or1k: Update fpu compare symbols to imply set flag 2019-06-13 06:16:19 +09:00
cris.cpu
epiphany.cpu
epiphany.opc epiphany/disassembler: Improve alignment of output. 2016-02-02 11:09:17 +00:00
fr30.cpu Correct fr30 comment 2016-03-03 12:55:30 +10:30
fr30.opc
frv.cpu
frv.opc opcodes error messages 2018-03-03 11:34:26 +10:30
ip2k.cpu
ip2k.opc
iq10.cpu
iq2000.cpu
iq2000.opc
iq2000m.cpu
lm32.cpu PR binutils/15241 2013-03-08 17:25:12 +00:00
lm32.opc
m32c.cpu
m32c.opc
m32r.cpu
m32r.opc
mep-avc2.cpu
mep-avc.cpu
mep-c5.cpu
mep-core.cpu
mep-default.cpu
mep-ext-cop.cpu
mep-fmax.cpu
mep-h1.cpu
mep-ivc2.cpu
mep-rhcop.cpu
mep-sample-ucidsp.cpu
mep.cpu
mep.opc Add fall through comment to source in cpu/ 2016-10-06 22:48:37 +10:30
mt.cpu
mt.opc
or1k.cpu cpu/or1k: Document no branch delay slot architectures and l.adrp 2019-06-13 06:16:19 +09:00
or1k.opc cpu/or1k: Add support for orfp64a32 spec 2019-06-13 06:16:18 +09:00
or1kcommon.cpu cpu/or1k: Add support for orfp64a32 spec 2019-06-13 06:16:18 +09:00
or1korbis.cpu cpu/or1k: Document no branch delay slot architectures and l.adrp 2019-06-13 06:16:19 +09:00
or1korfpx.cpu cpu/or1k: Update fpu compare symbols to imply set flag 2019-06-13 06:16:19 +09:00
sh64-compact.cpu
sh64-media.cpu
sh.cpu
sh.opc
simplify.inc
xc16x.cpu
xc16x.opc
xstormy16.cpu
xstormy16.opc