binutils-gdb/sim/mips
Frank Ch. Eigler 3fa454e95f * Monster patch - may destablize MIPS sims for a little while.
* Followup patch for SCEI PR 15853
* First check-in of TX3904 interrupt controller devices for ECC. [sanitized]
* First implementation of MIPS hardware interrupt emulation.
Mon May 18 18:22:42 1998  Frank Ch. Eigler  <fche@cygnus.com>
	* configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
 	modules.  Recognize TX39 target with "mips*tx39" pattern.
	* configure: Rebuilt.
	* sim-main.h (*): Added many macros defining bits in
 	TX39 control registers.
	(SignalInterrupt): Send actual PC instead of NULL.
	(SignalNMIReset): New exception type.
	* interp.c (board): New variable for future use to identify
	a particular board being simulated.
	(mips_option_handler,mips_options): Added "--board" option.
	(interrupt_event): Send actual PC.
	(sim_open): Make memory layout conditional on board setting.
	(signal_exception): Initial implementation of hardware interrupt
 	handling.  Accept another break instruction variant for simulator
 	exit.
	(decode_coproc): Implement RFE instruction for TX39.
	(mips.igen): Decode RFE instruction as such.
start-sanitize-tx3904
	* configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
	* interp.c: Define "jmr3904" and "jmr3904debug" board types and
	bbegin to implement memory map.
	* dv-tx3904cpu.c: New file.
	* dv-tx3904irc.c: New file.
end-sanitize-tx3904
1998-05-18 15:55:05 +00:00
..
.Sanitize * Monster patch - may destablize MIPS sims for a little while. 1998-05-18 15:55:05 +00:00
acconfig.h
ChangeLog * Monster patch - may destablize MIPS sims for a little while. 1998-05-18 15:55:05 +00:00
config.in
configure * Monster patch - may destablize MIPS sims for a little while. 1998-05-18 15:55:05 +00:00
configure.in * Monster patch - may destablize MIPS sims for a little while. 1998-05-18 15:55:05 +00:00
dv-tx3904cpu.c * Monster patch - may destablize MIPS sims for a little while. 1998-05-18 15:55:05 +00:00
dv-tx3904irc.c * Monster patch - may destablize MIPS sims for a little while. 1998-05-18 15:55:05 +00:00
gencode.c
interp.c * Monster patch - may destablize MIPS sims for a little while. 1998-05-18 15:55:05 +00:00
m16.dc
m16.igen
m16run.c
Makefile.in
mdmx.igen
mips.dc
mips.igen * Monster patch - may destablize MIPS sims for a little while. 1998-05-18 15:55:05 +00:00
README.Cygnus
sim-main.c
sim-main.h * Monster patch - may destablize MIPS sims for a little while. 1998-05-18 15:55:05 +00:00
sky-pke.c
sky-pke.h
tconfig.in
tx.igen
vr4320.igen
vr5400.igen

This directory contains two very different simulators:

	o	gencode (old)

		Gencode.c outputs a single monolithic file that is
		#included by interp.c

	o	igen (new)

		The *.igen files are used as inputs to ../igen/igen.
		A number of separate, fairly modula files, are created.

The new simulator has a number of advantages:

	o	builtin support for multi-simming (single simulator
		image supporting a number of different instruction
		set architectures).

	o	Easier maintenance. The input files are not confused
		by an intermixing with the generator code.

gencode continues to exist so that old architectures can be emulated.
*.igen should be used when adding new architectures or adding
instructions to an existing ISA.

Known bugs?

A mips16 simulator cannot be built using igen.  A custom mips16
engine.c needs to be written.

In mips.igen, the semantics for many of the instructions were created
using code generated by gencode.  Those semantic segments could be
greatly simplified.


----

Old README.Cygnus ...

> README.Cygnus
-------------------------------------------------------------------------------

The following are the main reasons for constructing the simulator as a
generator:

1) Avoid large fixed decode source file, with lots of #ifs controlling
   the compilation. i.e. keep the source cleaner, smaller and easier
   to parse.

2) Allow optimum code to be created, without run-time checks on
   instruction types. Ensure that the simulator engine only includes
   code for the architecture being targetted. e.g. This avoids
   run-time checks on ISA conformance, aswell as increasing
   throughput.

3) Allow updates to the instruction sets to be added quickly. Having a
   table means that the information is together, and is easier to
   manipulate. Having the table generate the engine, rather than the
   run-time parse the table gives higher performance at simulation
   time.

4) Keep all the similar simulation code together. i.e. have a single
   place where, for example, the addition code is held. This ensures that
   updates to the simulation are not spread over a large flat source
   file maintained by the developer.

-------------------------------------------------------------------------------

To keep the simulator simple (and to avoid the slight chance of
mis-matched files) the manifests describing an engine, and the
simulator engine itself, are held in the same source file.

This means that the engine must be included twice, with the first pass
controlled by the SIM_MANIFESTS definition.

-------------------------------------------------------------------------------
> EOF README.Cygnus