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binutils-gdb/sim/mips/Makefile.in
Frank Ch. Eigler 15232df4a3 * Inserted skeleton of R5900 COP2 simulation. Merged old vu[01].[ch] code 
into single PKE-style vu.[ch].


[ChangeLog]

Fri Mar 27 16:19:29 1998  Frank Ch. Eigler  <fche@cygnus.com>

start-sanitize-sky
	* Makefile.in (SIM_SKY_OBJS): Replaced sky-vu[01].o with sky-vu.o.

	* interp.c (sim_{load,store}_register): Use new vu[01]_device
 	static to access VU registers.
	(decode_coproc): Added skeleton of sky COP2 (VU) instruction
 	decoding.  Work in progress.

	* mips.igen (LDCzz, SDCzz): Removed *5900 case for this
 	overlapping/redundant bit pattern.
	(LQC2, SQC2): Added *5900 COP2 instruction skeleta.  Work in
	progress.

	* sim-main.h (status_CU[012]): Added COP[n]-enabled flags for
 	status register.

end-sanitize-sky

	* interp.c (cop_lq, cop_sq): New functions for future 128-bit
 	access to coprocessor registers.

	* sim-main.h (COP_LQ, COP_SQ): New macro front-ends for above.

[ChangeLog.sky]

	* sky-engine.c (engine_run): Adapted from vu[01] -> vu merge.

	* sky-hardware.c (register_devices): Ditto

	* sky-pke.c (pke_fifo_*): Made these functions private again, now
 	that the GPUIF code does not use them.

	* sky-pke.h (pke_fifo_*): Removed newly private declarations.

	* sky-vu.c (*): Major rework: merge of old sky-vu0.c and
 	sky-vu1.c.  Management of two VU devices parallels two PKEs.
	Work in progress.

	* sky-vu.h (*): Other half of merge.
	(vu_device): New struct, parallel to pke_device.
1998-03-27 22:00:56 +00:00

346 lines
8.4 KiB
Makefile
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# Makefile template for Configure for the MIPS simulator.
# Written by Cygnus Support.
## COMMON_PRE_CONFIG_FRAG
srcdir=@srcdir@
srcroot=$(srcdir)/../../
SIM_NO_OBJ =
# start-sanitize-sky
SIM_SKY_OBJS = \
sky-device.o \
sky-dma.o \
sky-engine.o \
sky-gpuif.o \
sky-hardware.o \
sky-libvpe.o \
sky-pke.o \
sky-vu.o \
sky-gs.o \
sky-gdb.o
# end-sanitize-sky
SIM_IGEN_OBJ = \
support.o \
itable.o \
semantics.o \
idecode.o \
icache.o \
engine.o \
irun.o \
SIM_M16_OBJ = \
m16_support.o \
m16_semantics.o \
m16_idecode.o \
m16_icache.o \
\
m32_support.o \
m32_semantics.o \
m32_idecode.o \
m32_icache.o \
\
itable.o \
m16run.o \
MIPS_EXTRA_OBJS = @mips_extra_objs@
MIPS_EXTRA_LIBS = @mips_extra_libs@
SIM_OBJS = \
$(SIM_@sim_gen@_OBJ) \
$(SIM_NEW_COMMON_OBJS) \
$(MIPS_EXTRA_OBJS) \
interp.o \
sim-hload.o \
sim-engine.o \
sim-stop.o \
sim-resume.o \
sim-reason.o \
# List of flags to always pass to $(CC).
SIM_SUBTARGET=@SIM_SUBTARGET@
SIM_NO_CFLAGS = -DWITH_IGEN=0
SIM_IGEN_CFLAGS = -DWITH_IGEN=1
SIM_M16_CFLAGS = -DWITH_IGEN=1
# FIXME: Hack to find syscall.h? Better support for syscall.h
# is in progress.
SIM_EXTRA_CFLAGS = \
$(SIM_SUBTARGET) \
-I$(srcdir)/../../newlib/libc/sys/idt \
$(SIM_@sim_gen@_CFLAGS)
SIM_EXTRA_CLEAN = clean-extra
SIM_EXTRA_ALL = $(SIM_@sim_gen@_ALL)
SIM_EXTRA_LIBS = $(MIPS_EXTRA_LIBS)
# List of main object files for `run'.
SIM_RUN_OBJS = nrun.o
## COMMON_POST_CONFIG_FRAG
SIM_NO_INTERP = oengine.c
interp.o: $(srcdir)/interp.c config.h sim-main.h $(SIM_@sim_gen@_INTERP)
#
# Old deprecated generator
#
SIM_NO_ALL = oengine.c
oengine.c: gencode
./gencode @SIMCONF@ > tmp-oengine
mv tmp-oengine oengine.c
gencode: gencode.o getopt.o getopt1.o
$(CC_FOR_BUILD) -o $@ gencode.o getopt.o getopt1.o
gencode.o: $(srcdir)/gencode.c
$(CC_FOR_BUILD) -c -g -I${srcroot}/include $(srcdir)/gencode.c
getopt.o: $(srcdir)/../../libiberty/getopt.c
$(CC_FOR_BUILD) -c -g -I${srcroot}/include $(srcdir)/../../libiberty/getopt.c
getopt1.o: $(srcdir)/../../libiberty/getopt1.c
$(CC_FOR_BUILD) -c -g -I${srcroot}/include $(srcdir)/../../libiberty/getopt1.c
../igen/igen:
cd ../igen && $(MAKE)
IGEN_TRACE= # -G omit-line-numbers # -G trace-rule-selection -G trace-rule-rejection -G trace-entries
IGEN_INSN=$(srcdir)/mips.igen
IGEN_DC=$(srcdir)/mips.dc
M16_DC=$(srcdir)/m16.dc
IGEN_INCLUDE=\
$(start-sanitize-r5900) \
$(srcdir)/r5900.igen \
$(end-sanitize-r5900) \
$(start-sanitize-vr5400) \
$(srcdir)/vr5400.igen \
$(srcdir)/mdmx.igen \
$(end-sanitize-vr5400) \
$(start-sanitize-vr4320) \
$(srcdir)/vr4320.igen \
$(end-sanitize-vr4320) \
$(srcdir)/m16.igen
SIM_IGEN_ALL = tmp-igen
BUILT_SRC_FROM_IGEN = \
icache.h \
icache.c \
idecode.h \
idecode.c \
semantics.h \
semantics.c \
model.h \
model.c \
support.h \
support.c \
engine.h \
engine.c \
irun.c \
# NB: Since these can be built by either tmp-igen or tmp-m16
# they are explicitly marked as being dependant on the
# dependant on the selected generator.
BUILT_SRC_FROM_GEN = \
itable.h \
itable.c \
$(BUILT_SRC_FROM_GEN): $(SIM_@sim_gen@_ALL)
$(BUILT_SRC_FROM_IGEN): tmp-igen
tmp-igen: $(IGEN_INSN) $(IGEN_DC) ../igen/igen $(IGEN_INCLUDE)
cd ../igen && $(MAKE)
../igen/igen \
$(IGEN_TRACE) \
-I $(srcdir) \
-Werror \
-Wnodiscard \
@sim_igen_flags@ \
-G gen-direct-access \
-G gen-zero-r0 \
-B 32 \
-H 31 \
-i $(IGEN_INSN) \
-o $(IGEN_DC) \
-x \
-n icache.h -hc tmp-icache.h \
-n icache.c -c tmp-icache.c \
-n semantics.h -hs tmp-semantics.h \
-n semantics.c -s tmp-semantics.c \
-n idecode.h -hd tmp-idecode.h \
-n idecode.c -d tmp-idecode.c \
-n model.h -hm tmp-model.h \
-n model.c -m tmp-model.c \
-n support.h -hf tmp-support.h \
-n support.c -f tmp-support.c \
-n itable.h -ht tmp-itable.h \
-n itable.c -t tmp-itable.c \
-n engine.h -he tmp-engine.h \
-n engine.c -e tmp-engine.c \
-n irun.c -r tmp-irun.c
$(srcdir)/../../move-if-change tmp-icache.h icache.h
$(srcdir)/../../move-if-change tmp-icache.c icache.c
$(srcdir)/../../move-if-change tmp-idecode.h idecode.h
$(srcdir)/../../move-if-change tmp-idecode.c idecode.c
$(srcdir)/../../move-if-change tmp-semantics.h semantics.h
$(srcdir)/../../move-if-change tmp-semantics.c semantics.c
$(srcdir)/../../move-if-change tmp-model.h model.h
$(srcdir)/../../move-if-change tmp-model.c model.c
$(srcdir)/../../move-if-change tmp-support.h support.h
$(srcdir)/../../move-if-change tmp-support.c support.c
$(srcdir)/../../move-if-change tmp-itable.h itable.h
$(srcdir)/../../move-if-change tmp-itable.c itable.c
$(srcdir)/../../move-if-change tmp-engine.h engine.h
$(srcdir)/../../move-if-change tmp-engine.c engine.c
$(srcdir)/../../move-if-change tmp-irun.c irun.c
touch tmp-igen
semantics.o: sim-main.h $(SIM_EXTRA_DEPS)
engine.o: sim-main.h $(SIM_EXTRA_DEPS)
support.o: sim-main.h $(SIM_EXTRA_DEPS)
idecode.o: sim-main.h $(SIM_EXTRA_DEPS)
itable.o: sim-main.h $(SIM_EXTRA_DEPS)
SIM_M16_ALL = tmp-m16
BUILT_SRC_FROM_M16 = \
m16_icache.h \
m16_icache.c \
m16_idecode.h \
m16_idecode.c \
m16_semantics.h \
m16_semantics.c \
m16_model.h \
m16_model.c \
m16_support.h \
m16_support.c \
\
m32_icache.h \
m32_icache.c \
m32_idecode.h \
m32_idecode.c \
m32_semantics.h \
m32_semantics.c \
m32_model.h \
m32_model.c \
m32_support.h \
m32_support.c \
$(BUILT_SRC_FROM_M16): tmp-m16
tmp-m16: $(IGEN_INSN) $(IGEN_DC) ../igen/igen $(IGEN_INCLUDE)
cd ../igen && $(MAKE)
../igen/igen \
$(IGEN_TRACE) \
-I $(srcdir) \
-Werror \
-Wnodiscard \
@sim_m16_flags@ \
-G gen-direct-access \
-G gen-zero-r0 \
-B 16 \
-H 15 \
-i $(IGEN_INSN) \
-o $(M16_DC) \
-P m16_ \
-x \
-n m16_icache.h -hc tmp-icache.h \
-n m16_icache.c -c tmp-icache.c \
-n m16_semantics.h -hs tmp-semantics.h \
-n m16_semantics.c -s tmp-semantics.c \
-n m16_idecode.h -hd tmp-idecode.h \
-n m16_idecode.c -d tmp-idecode.c \
-n m16_model.h -hm tmp-model.h \
-n m16_model.c -m tmp-model.c \
-n m16_support.h -hf tmp-support.h \
-n m16_support.c -f tmp-support.c \
#
$(srcdir)/../../move-if-change tmp-icache.h m16_icache.h
$(srcdir)/../../move-if-change tmp-icache.c m16_icache.c
$(srcdir)/../../move-if-change tmp-idecode.h m16_idecode.h
$(srcdir)/../../move-if-change tmp-idecode.c m16_idecode.c
$(srcdir)/../../move-if-change tmp-semantics.h m16_semantics.h
$(srcdir)/../../move-if-change tmp-semantics.c m16_semantics.c
$(srcdir)/../../move-if-change tmp-model.h m16_model.h
$(srcdir)/../../move-if-change tmp-model.c m16_model.c
$(srcdir)/../../move-if-change tmp-support.h m16_support.h
$(srcdir)/../../move-if-change tmp-support.c m16_support.c
../igen/igen \
$(IGEN_TRACE) \
-I $(srcdir) \
-Werror \
-Wnodiscard \
@sim_igen_flags@ \
-G gen-direct-access \
-G gen-zero-r0 \
-B 32 \
-H 31 \
-i $(IGEN_INSN) \
-o $(IGEN_DC) \
-P m32_ \
-x \
-n m32_icache.h -hc tmp-icache.h \
-n m32_icache.c -c tmp-icache.c \
-n m32_semantics.h -hs tmp-semantics.h \
-n m32_semantics.c -s tmp-semantics.c \
-n m32_idecode.h -hd tmp-idecode.h \
-n m32_idecode.c -d tmp-idecode.c \
-n m32_model.h -hm tmp-model.h \
-n m32_model.c -m tmp-model.c \
-n m32_support.h -hf tmp-support.h \
-n m32_support.c -f tmp-support.c \
#
$(srcdir)/../../move-if-change tmp-icache.h m32_icache.h
$(srcdir)/../../move-if-change tmp-icache.c m32_icache.c
$(srcdir)/../../move-if-change tmp-idecode.h m32_idecode.h
$(srcdir)/../../move-if-change tmp-idecode.c m32_idecode.c
$(srcdir)/../../move-if-change tmp-semantics.h m32_semantics.h
$(srcdir)/../../move-if-change tmp-semantics.c m32_semantics.c
$(srcdir)/../../move-if-change tmp-model.h m32_model.h
$(srcdir)/../../move-if-change tmp-model.c m32_model.c
$(srcdir)/../../move-if-change tmp-support.h m32_support.h
$(srcdir)/../../move-if-change tmp-support.c m32_support.c
../igen/igen \
$(IGEN_TRACE) \
-I $(srcdir) \
-Werror \
-Wnodiscard \
-Wnowidth \
@sim_igen_flags@ @sim_m16_flags@ \
-G gen-direct-access \
-G gen-zero-r0 \
-i $(IGEN_INSN) \
-n itable.h -ht tmp-itable.h \
-n itable.c -t tmp-itable.c \
#
$(srcdir)/../../move-if-change tmp-itable.h itable.h
$(srcdir)/../../move-if-change tmp-itable.c itable.c
touch tmp-m16
clean-extra:
rm -f gencode oengine.c tmp.igen
rm -f $(BUILT_SRC_FROM_GEN)
rm -f $(BUILT_SRC_FROM_IGEN)
rm -f $(BUILT_SRC_FROM_M16)
rm -f tmp-igen
rm -f tmp-m16
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