0fd3a4776c
bfd: * elf32-xtensa.c (vsprint_msg): Add format attribute. Fix format bugs. * vms.h (_bfd_vms_debug): Add format attribute. (_bfd_vms_debug, _bfd_hexdump): Fix typos. binutils: * bucomm.h (report): Add format attribute. * dlltool.c (inform): Likewise. * dllwrap.c (display, inform, warn): Likewise. * objdump.c (objdump_sprintf): Likewise. * readelf.c (error, warn): Likewise. Fix format bugs. gas: * config/tc-tic30.c (debug): Add format attribute. Fix format bugs. include: * dis-asm.h (fprintf_ftype): Add format attribute. opcodes: * arc-dis.c, arm-dis.c, cris-dis.c, crx-dis.c, d10v-dis.c, d30v-dis.c, fr30-dis.c, h8300-dis.c, h8500-dis.c, i860-dis.c, ia64-dis.c, ip2k-dis.c, m10200-dis.c, m10300-dis.c, m88k-dis.c, mcore-dis.c, mips-dis.c, ms1-dis.c, or32-dis.c, ppc-dis.c, sh64-dis.c, sparc-dis.c, tic4x-dis.c, tic80-dis.c, v850-dis.c: Fix format bugs. * ia64-gen.c (fail, warn): Add format attribute. * or32-opc.c (debug): Likewise.
620 lines
16 KiB
C
620 lines
16 KiB
C
/* Disassemble SH64 instructions.
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Copyright 2000, 2001, 2002, 2003, 2005 Free Software Foundation, Inc.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
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#include <stdio.h>
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#include "dis-asm.h"
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#include "sysdep.h"
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#include "sh64-opc.h"
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#include "libiberty.h"
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/* We need to refer to the ELF header structure. */
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#include "elf-bfd.h"
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#include "elf/sh.h"
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#include "elf32-sh64.h"
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#define ELF_MODE32_CODE_LABEL_P(SYM) \
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(((elf_symbol_type *) (SYM))->internal_elf_sym.st_other & STO_SH5_ISA32)
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#define SAVED_MOVI_R(INFO) \
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(((struct sh64_disassemble_info *) ((INFO)->private_data))->address_reg)
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#define SAVED_MOVI_IMM(INFO) \
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(((struct sh64_disassemble_info *) ((INFO)->private_data))->built_address)
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struct sh64_disassemble_info
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{
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/* When we see a MOVI, we save the register and the value, and merge a
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subsequent SHORI and display the address, if there is one. */
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unsigned int address_reg;
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bfd_signed_vma built_address;
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/* This is the range decriptor for the current address. It is kept
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around for the next call. */
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sh64_elf_crange crange;
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};
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/* Each item in the table is a mask to indicate which bits to be set
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to determine an instruction's operator.
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The index is as same as the instruction in the opcode table.
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Note that some archs have this as a field in the opcode table. */
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static unsigned long *shmedia_opcode_mask_table;
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/* Initialize the SH64 opcode mask table for each instruction in SHmedia
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mode. */
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static void
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initialize_shmedia_opcode_mask_table (void)
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{
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int n_opc;
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int n;
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/* Calculate number of opcodes. */
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for (n_opc = 0; shmedia_table[n_opc].name != NULL; n_opc++)
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;
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shmedia_opcode_mask_table
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= xmalloc (sizeof (shmedia_opcode_mask_table[0]) * n_opc);
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for (n = 0; n < n_opc; n++)
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{
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int i;
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unsigned long mask = 0;
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for (i = 0; shmedia_table[n].arg[i] != A_NONE; i++)
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{
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int offset = shmedia_table[n].nibbles[i];
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int length;
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switch (shmedia_table[n].arg[i])
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{
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case A_GREG_M:
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case A_GREG_N:
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case A_GREG_D:
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case A_CREG_K:
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case A_CREG_J:
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case A_FREG_G:
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case A_FREG_H:
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case A_FREG_F:
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case A_DREG_G:
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case A_DREG_H:
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case A_DREG_F:
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case A_FMREG_G:
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case A_FMREG_H:
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case A_FMREG_F:
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case A_FPREG_G:
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case A_FPREG_H:
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case A_FPREG_F:
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case A_FVREG_G:
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case A_FVREG_H:
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case A_FVREG_F:
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case A_REUSE_PREV:
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length = 6;
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break;
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case A_TREG_A:
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case A_TREG_B:
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length = 3;
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break;
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case A_IMMM:
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abort ();
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break;
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case A_IMMU5:
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length = 5;
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break;
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case A_IMMS6:
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case A_IMMU6:
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case A_IMMS6BY32:
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length = 6;
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break;
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case A_IMMS10:
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case A_IMMS10BY1:
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case A_IMMS10BY2:
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case A_IMMS10BY4:
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case A_IMMS10BY8:
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length = 10;
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break;
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case A_IMMU16:
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case A_IMMS16:
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case A_PCIMMS16BY4:
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case A_PCIMMS16BY4_PT:
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length = 16;
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break;
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default:
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abort ();
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length = 0;
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break;
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}
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if (length != 0)
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mask |= (0xffffffff >> (32 - length)) << offset;
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}
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shmedia_opcode_mask_table[n] = 0xffffffff & ~mask;
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}
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}
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/* Get a predefined control-register-name, or return NULL. */
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static const char *
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creg_name (int cregno)
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{
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const shmedia_creg_info *cregp;
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/* If control register usage is common enough, change this to search a
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hash-table. */
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for (cregp = shmedia_creg_table; cregp->name != NULL; cregp++)
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if (cregp->cregno == cregno)
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return cregp->name;
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return NULL;
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}
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/* Main function to disassemble SHmedia instructions. */
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static int
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print_insn_shmedia (bfd_vma memaddr, struct disassemble_info *info)
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{
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fprintf_ftype fprintf_fn = info->fprintf_func;
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void *stream = info->stream;
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unsigned char insn[4];
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unsigned long instruction;
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int status;
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int n;
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const shmedia_opcode_info *op;
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int i;
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unsigned int r = 0;
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long imm = 0;
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bfd_vma disp_pc_addr;
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status = info->read_memory_func (memaddr, insn, 4, info);
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/* If we can't read four bytes, something is wrong. Display any data we
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can get as .byte:s. */
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if (status != 0)
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{
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int i;
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for (i = 0; i < 3; i++)
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{
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status = info->read_memory_func (memaddr + i, insn, 1, info);
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if (status != 0)
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break;
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(*fprintf_fn) (stream, "%s0x%02x",
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i == 0 ? ".byte " : ", ",
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insn[0]);
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}
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return i ? i : -1;
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}
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/* Rearrange the bytes to make up an instruction. */
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if (info->endian == BFD_ENDIAN_LITTLE)
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instruction = bfd_getl32 (insn);
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else
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instruction = bfd_getb32 (insn);
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/* FIXME: Searching could be implemented using a hash on relevant
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fields. */
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for (n = 0, op = shmedia_table;
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op->name != NULL
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&& ((instruction & shmedia_opcode_mask_table[n]) != op->opcode_base);
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n++, op++)
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;
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/* FIXME: We should also check register number constraints. */
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if (op->name == NULL)
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{
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fprintf_fn (stream, ".long 0x%08lx", instruction);
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return 4;
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}
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fprintf_fn (stream, "%s\t", op->name);
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for (i = 0; i < 3 && op->arg[i] != A_NONE; i++)
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{
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unsigned long temp = instruction >> op->nibbles[i];
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int by_number = 0;
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if (i > 0 && op->arg[i] != A_REUSE_PREV)
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fprintf_fn (stream, ",");
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switch (op->arg[i])
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{
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case A_REUSE_PREV:
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continue;
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case A_GREG_M:
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case A_GREG_N:
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case A_GREG_D:
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r = temp & 0x3f;
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fprintf_fn (stream, "r%d", r);
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break;
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case A_FVREG_F:
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case A_FVREG_G:
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case A_FVREG_H:
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r = temp & 0x3f;
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fprintf_fn (stream, "fv%d", r);
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break;
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case A_FPREG_F:
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case A_FPREG_G:
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case A_FPREG_H:
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r = temp & 0x3f;
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fprintf_fn (stream, "fp%d", r);
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break;
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case A_FMREG_F:
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case A_FMREG_G:
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case A_FMREG_H:
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r = temp & 0x3f;
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fprintf_fn (stream, "mtrx%d", r);
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break;
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case A_CREG_K:
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case A_CREG_J:
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{
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const char *name;
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r = temp & 0x3f;
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name = creg_name (r);
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if (name != NULL)
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fprintf_fn (stream, "%s", name);
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else
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fprintf_fn (stream, "cr%d", r);
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}
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break;
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case A_FREG_G:
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case A_FREG_H:
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case A_FREG_F:
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r = temp & 0x3f;
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fprintf_fn (stream, "fr%d", r);
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break;
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case A_DREG_G:
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case A_DREG_H:
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case A_DREG_F:
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r = temp & 0x3f;
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fprintf_fn (stream, "dr%d", r);
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break;
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case A_TREG_A:
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case A_TREG_B:
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r = temp & 0x7;
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fprintf_fn (stream, "tr%d", r);
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break;
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/* A signed 6-bit number. */
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case A_IMMS6:
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imm = temp & 0x3f;
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if (imm & (unsigned long) 0x20)
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imm |= ~(unsigned long) 0x3f;
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fprintf_fn (stream, "%ld", imm);
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break;
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/* A signed 6-bit number, multiplied by 32 when used. */
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case A_IMMS6BY32:
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imm = temp & 0x3f;
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if (imm & (unsigned long) 0x20)
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imm |= ~(unsigned long) 0x3f;
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fprintf_fn (stream, "%ld", imm * 32);
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break;
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/* A signed 10-bit number, multiplied by 8 when used. */
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case A_IMMS10BY8:
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by_number++;
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/* Fall through. */
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/* A signed 10-bit number, multiplied by 4 when used. */
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case A_IMMS10BY4:
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by_number++;
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/* Fall through. */
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/* A signed 10-bit number, multiplied by 2 when used. */
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case A_IMMS10BY2:
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by_number++;
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/* Fall through. */
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/* A signed 10-bit number. */
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case A_IMMS10:
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case A_IMMS10BY1:
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imm = temp & 0x3ff;
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if (imm & (unsigned long) 0x200)
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imm |= ~(unsigned long) 0x3ff;
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imm <<= by_number;
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fprintf_fn (stream, "%ld", imm);
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break;
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/* A signed 16-bit number. */
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case A_IMMS16:
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imm = temp & 0xffff;
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if (imm & (unsigned long) 0x8000)
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imm |= ~((unsigned long) 0xffff);
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fprintf_fn (stream, "%ld", imm);
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break;
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/* A PC-relative signed 16-bit number, multiplied by 4 when
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used. */
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case A_PCIMMS16BY4:
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imm = temp & 0xffff; /* 16 bits */
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if (imm & (unsigned long) 0x8000)
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imm |= ~(unsigned long) 0xffff;
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imm <<= 2;
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disp_pc_addr = (bfd_vma) imm + memaddr;
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(*info->print_address_func) (disp_pc_addr, info);
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break;
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/* An unsigned 5-bit number. */
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case A_IMMU5:
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imm = temp & 0x1f;
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fprintf_fn (stream, "%ld", imm);
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break;
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/* An unsigned 6-bit number. */
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case A_IMMU6:
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imm = temp & 0x3f;
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fprintf_fn (stream, "%ld", imm);
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break;
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/* An unsigned 16-bit number. */
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case A_IMMU16:
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imm = temp & 0xffff;
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fprintf_fn (stream, "%ld", imm);
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break;
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default:
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abort ();
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break;
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}
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}
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/* FIXME: Looks like 32-bit values only are handled.
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FIXME: PC-relative numbers aren't handled correctly. */
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if (op->opcode_base == (unsigned long) SHMEDIA_SHORI_OPC
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&& SAVED_MOVI_R (info) == r)
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{
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asection *section = info->section;
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/* Most callers do not set the section field correctly yet. Revert
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to getting the section from symbols, if any. */
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if (section == NULL
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&& info->symbols != NULL
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&& bfd_asymbol_flavour (info->symbols[0]) == bfd_target_elf_flavour
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&& ! bfd_is_und_section (bfd_get_section (info->symbols[0]))
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&& ! bfd_is_abs_section (bfd_get_section (info->symbols[0])))
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section = bfd_get_section (info->symbols[0]);
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/* Only guess addresses when the contents of this section is fully
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relocated. Otherwise, the value will be zero or perhaps even
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bogus. */
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if (section == NULL
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|| section->owner == NULL
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|| elf_elfheader (section->owner)->e_type == ET_EXEC)
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{
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bfd_signed_vma shori_addr;
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shori_addr = SAVED_MOVI_IMM (info) << 16;
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shori_addr |= imm;
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fprintf_fn (stream, "\t! 0x");
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(*info->print_address_func) (shori_addr, info);
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}
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}
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if (op->opcode_base == SHMEDIA_MOVI_OPC)
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{
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SAVED_MOVI_IMM (info) = imm;
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SAVED_MOVI_R (info) = r;
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}
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else
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{
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SAVED_MOVI_IMM (info) = 0;
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SAVED_MOVI_R (info) = 255;
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}
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return 4;
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}
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/* Check the type of contents about to be disassembled. This is like
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sh64_get_contents_type (which may be called from here), except that it
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takes the same arguments as print_insn_* and does what can be done if
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no section is available. */
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static enum sh64_elf_cr_type
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sh64_get_contents_type_disasm (bfd_vma memaddr, struct disassemble_info *info)
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{
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struct sh64_disassemble_info *sh64_infop = info->private_data;
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/* Perhaps we have a region from a previous probe and it still counts
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for this address? */
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if (sh64_infop->crange.cr_type != CRT_NONE
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&& memaddr >= sh64_infop->crange.cr_addr
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&& memaddr < sh64_infop->crange.cr_addr + sh64_infop->crange.cr_size)
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return sh64_infop->crange.cr_type;
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/* If we have a section, try and use it. */
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if (info->section
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&& bfd_get_flavour (info->section->owner) == bfd_target_elf_flavour)
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{
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enum sh64_elf_cr_type cr_type
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= sh64_get_contents_type (info->section, memaddr,
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&sh64_infop->crange);
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if (cr_type != CRT_NONE)
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return cr_type;
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}
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/* If we have symbols, we can try and get at a section from *that*. */
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if (info->symbols != NULL
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&& bfd_asymbol_flavour (info->symbols[0]) == bfd_target_elf_flavour
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&& ! bfd_is_und_section (bfd_get_section (info->symbols[0]))
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&& ! bfd_is_abs_section (bfd_get_section (info->symbols[0])))
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{
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enum sh64_elf_cr_type cr_type
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= sh64_get_contents_type (bfd_get_section (info->symbols[0]),
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memaddr, &sh64_infop->crange);
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if (cr_type != CRT_NONE)
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return cr_type;
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}
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/* We can make a reasonable guess based on the st_other field of a
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symbol; for a BranchTarget this is marked as STO_SH5_ISA32 and then
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it's most probably code there. */
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if (info->symbols
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&& bfd_asymbol_flavour (info->symbols[0]) == bfd_target_elf_flavour
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&& elf_symbol_from (bfd_asymbol_bfd (info->symbols[0]),
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info->symbols[0])->internal_elf_sym.st_other
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== STO_SH5_ISA32)
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return CRT_SH5_ISA32;
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/* If all else fails, guess this is code and guess on the low bit set. */
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return (memaddr & 1) == 1 ? CRT_SH5_ISA32 : CRT_SH5_ISA16;
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}
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/* Initialize static and dynamic disassembly state. */
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static bfd_boolean
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init_sh64_disasm_info (struct disassemble_info *info)
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{
|
|
struct sh64_disassemble_info *sh64_infop
|
|
= calloc (sizeof (*sh64_infop), 1);
|
|
|
|
if (sh64_infop == NULL)
|
|
return FALSE;
|
|
|
|
info->private_data = sh64_infop;
|
|
|
|
SAVED_MOVI_IMM (info) = 0;
|
|
SAVED_MOVI_R (info) = 255;
|
|
|
|
if (shmedia_opcode_mask_table == NULL)
|
|
initialize_shmedia_opcode_mask_table ();
|
|
|
|
return TRUE;
|
|
}
|
|
|
|
/* Main entry to disassemble SHmedia instructions, given an endian set in
|
|
INFO. Note that the simulator uses this as the main entry and does not
|
|
use any of the functions further below. */
|
|
|
|
int
|
|
print_insn_sh64x_media (bfd_vma memaddr, struct disassemble_info *info)
|
|
{
|
|
if (info->private_data == NULL && ! init_sh64_disasm_info (info))
|
|
return -1;
|
|
|
|
/* Make reasonable output. */
|
|
info->bytes_per_line = 4;
|
|
info->bytes_per_chunk = 4;
|
|
|
|
return print_insn_shmedia (memaddr, info);
|
|
}
|
|
|
|
/* Main entry to disassemble SHmedia insns.
|
|
If we see an SHcompact instruction, return -2. */
|
|
|
|
int
|
|
print_insn_sh64 (bfd_vma memaddr, struct disassemble_info *info)
|
|
{
|
|
enum bfd_endian endian = info->endian;
|
|
enum sh64_elf_cr_type cr_type;
|
|
|
|
if (info->private_data == NULL && ! init_sh64_disasm_info (info))
|
|
return -1;
|
|
|
|
cr_type = sh64_get_contents_type_disasm (memaddr, info);
|
|
if (cr_type != CRT_SH5_ISA16)
|
|
{
|
|
int length = 4 - (memaddr % 4);
|
|
info->display_endian = endian;
|
|
|
|
/* If we got an uneven address to indicate SHmedia, adjust it. */
|
|
if (cr_type == CRT_SH5_ISA32 && length == 3)
|
|
memaddr--, length = 4;
|
|
|
|
/* Only disassemble on four-byte boundaries. Addresses that are not
|
|
a multiple of four can happen after a data region. */
|
|
if (cr_type == CRT_SH5_ISA32 && length == 4)
|
|
return print_insn_sh64x_media (memaddr, info);
|
|
|
|
/* We get CRT_DATA *only* for data regions in a mixed-contents
|
|
section. For sections with data only, we get indication of one
|
|
of the ISA:s. You may think that we shouldn't disassemble
|
|
section with only data if we can figure that out. However, the
|
|
disassembly function is by default not called for data-only
|
|
sections, so if the user explicitly specified disassembly of a
|
|
data section, that's what we should do. */
|
|
if (cr_type == CRT_DATA || length != 4)
|
|
{
|
|
int status;
|
|
unsigned char data[4];
|
|
struct sh64_disassemble_info *sh64_infop = info->private_data;
|
|
|
|
if (length == 4
|
|
&& sh64_infop->crange.cr_type != CRT_NONE
|
|
&& memaddr >= sh64_infop->crange.cr_addr
|
|
&& memaddr < (sh64_infop->crange.cr_addr
|
|
+ sh64_infop->crange.cr_size))
|
|
length
|
|
= (sh64_infop->crange.cr_addr
|
|
+ sh64_infop->crange.cr_size - memaddr);
|
|
|
|
status
|
|
= (*info->read_memory_func) (memaddr, data,
|
|
length >= 4 ? 4 : length, info);
|
|
|
|
if (status == 0 && length >= 4)
|
|
{
|
|
(*info->fprintf_func) (info->stream, ".long 0x%08lx",
|
|
endian == BFD_ENDIAN_BIG
|
|
? (long) (bfd_getb32 (data))
|
|
: (long) (bfd_getl32 (data)));
|
|
return 4;
|
|
}
|
|
else
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < length; i++)
|
|
{
|
|
status = info->read_memory_func (memaddr + i, data, 1, info);
|
|
if (status != 0)
|
|
break;
|
|
(*info->fprintf_func) (info->stream, "%s0x%02x",
|
|
i == 0 ? ".byte " : ", ",
|
|
data[0]);
|
|
}
|
|
|
|
return i ? i : -1;
|
|
}
|
|
}
|
|
}
|
|
|
|
/* SH1 .. SH4 instruction, let caller handle it. */
|
|
return -2;
|
|
}
|