469 lines
15 KiB
Plaintext
469 lines
15 KiB
Plaintext
@c Copyright (C) 2016-2020 Free Software Foundation, Inc.
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@c This is part of the GAS anual.
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@c For copying conditions, see the file as.texinfo
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@c man end
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@ifset GENERIC
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@page
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@node RISC-V-Dependent
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@chapter RISC-V Dependent Features
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@end ifset
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@ifclear GENERIC
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@node Machine Dependencies
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@chapter RISC-V Dependent Features
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@end ifclear
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@cindex RISC-V support
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@menu
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* RISC-V-Options:: RISC-V Options
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* RISC-V-Directives:: RISC-V Directives
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* RISC-V-Formats:: RISC-V Instruction Formats
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* RISC-V-ATTRIBUTE:: RISC-V Object Attribute
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@end menu
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@node RISC-V-Options
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@section RISC-V Options
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The following table lists all available RISC-V specific options.
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@c man begin OPTIONS
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@table @gcctabopt
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@cindex @samp{-fpic} option, RISC-V
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@item -fpic
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@itemx -fPIC
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Generate position-independent code
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@cindex @samp{-fno-pic} option, RISC-V
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@item -fno-pic
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Don't generate position-independent code (default)
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@cindex @samp{-march=ISA} option, RISC-V
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@item -march=ISA
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Select the base isa, as specified by ISA. For example -march=rv32ima.
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@cindex @samp{-mabi=ABI} option, RISC-V
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@item -mabi=ABI
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Selects the ABI, which is either "ilp32" or "lp64", optionally followed
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by "f", "d", or "q" to indicate single-precision, double-precision, or
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quad-precision floating-point calling convention, or none to indicate
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the soft-float calling convention. Also, "ilp32" can optionally be followed
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by "e" to indicate the RVE ABI, which is always soft-float.
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@cindex @samp{-mrelax} option, RISC-V
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@item -mrelax
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Take advantage of linker relaxations to reduce the number of instructions
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required to materialize symbol addresses. (default)
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@cindex @samp{-mno-relax} option, RISC-V
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@item -mno-relax
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Don't do linker relaxations.
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@end table
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@c man end
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@node RISC-V-Directives
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@section RISC-V Directives
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@cindex machine directives, RISC-V
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@cindex RISC-V machine directives
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The following table lists all available RISC-V specific directives.
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@table @code
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@cindex @code{align} directive
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@item .align @var{size-log-2}
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Align to the given boundary, with the size given as log2 the number of bytes to
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align to.
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@cindex Data directives
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@item .half @var{value}
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@itemx .word @var{value}
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@itemx .dword @var{value}
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Emits a half-word, word, or double-word value at the current position.
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@cindex DTP-relative data directives
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@item .dtprelword @var{value}
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@itemx .dtpreldword @var{value}
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Emits a DTP-relative word (or double-word) at the current position. This is
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meant to be used by the compiler in shared libraries for DWARF debug info for
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thread local variables.
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@cindex BSS directive
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@item .bss
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Sets the current section to the BSS section.
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@cindex LEB128 directives
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@item .uleb128 @var{value}
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@itemx .sleb128 @var{value}
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Emits a signed or unsigned LEB128 value at the current position. This only
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accepts constant expressions, because symbol addresses can change with
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relaxation, and we don't support relocations to modify LEB128 values at link
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time.
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@cindex Option directive
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@cindex @code{option} directive
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@item .option @var{argument}
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Modifies RISC-V specific assembler options inline with the assembly code.
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This is used when particular instruction sequences must be assembled with a
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specific set of options. For example, since we relax addressing sequences to
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shorter GP-relative sequences when possible the initial load of GP must not be
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relaxed and should be emitted as something like
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@smallexample
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.option push
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.option norelax
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la gp, __global_pointer$
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.option pop
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@end smallexample
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in order to produce after linker relaxation the expected
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@smallexample
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auipc gp, %pcrel_hi(__global_pointer$)
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addi gp, gp, %pcrel_lo(__global_pointer$)
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@end smallexample
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instead of just
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@smallexample
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addi gp, gp, 0
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@end smallexample
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It's not expected that options are changed in this manner during regular use,
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but there are a handful of esoteric cases like the one above where users need
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to disable particular features of the assembler for particular code sequences.
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The complete list of option arguments is shown below:
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@table @code
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@item push
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@itemx pop
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Pushes or pops the current option stack. These should be used whenever
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changing an option in line with assembly code in order to ensure the user's
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command-line options are respected for the bulk of the file being assembled.
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@item rvc
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@itemx norvc
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Enables or disables the generation of compressed instructions. Instructions
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are opportunistically compressed by the RISC-V assembler when possible, but
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sometimes this behavior is not desirable.
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@item pic
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@itemx nopic
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Enables or disables position-independent code generation. Unless you really
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know what you're doing, this should only be at the top of a file.
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@item relax
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@itemx norelax
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Enables or disables relaxation. The RISC-V assembler and linker
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opportunistically relax some code sequences, but sometimes this behavior is not
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desirable.
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@end table
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@cindex INSN directives
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@item .insn @var{value}
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@itemx .insn @var{value}
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This directive permits the numeric representation of an instructions
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and makes the assembler insert the operands according to one of the
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instruction formats for @samp{.insn} (@ref{RISC-V-Formats}).
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For example, the instruction @samp{add a0, a1, a2} could be written as
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@samp{.insn r 0x33, 0, 0, a0, a1, a2}.
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@cindex @code{.attribute} directive, RISC-V
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@item .attribute @var{tag}, @var{value}
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Set the object attribute @var{tag} to @var{value}.
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The @var{tag} is either an attribute number, or one of the following:
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@code{Tag_RISCV_arch}, @code{Tag_RISCV_stack_align},
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@code{Tag_RISCV_unaligned_access}, @code{Tag_RISCV_priv_spec},
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@code{Tag_RISCV_priv_spec_minor}, @code{Tag_RISCV_priv_spec_revision}.
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@end table
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@node RISC-V-Formats
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@section Instruction Formats
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@cindex instruction formats, risc-v
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@cindex RISC-V instruction formats
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The RISC-V Instruction Set Manual Volume I: User-Level ISA lists 12
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instruction formats where some of the formats have multiple variants.
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For the @samp{.insn} pseudo directive the assembler recognizes some
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of the formats.
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Typically, the most general variant of the instruction format is used
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by the @samp{.insn} directive.
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The following table lists the abbreviations used in the table of
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instruction formats:
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@display
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@multitable @columnfractions .15 .40
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@item opcode @tab Unsigned immediate or opcode name for 7-bits opcode.
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@item opcode2 @tab Unsigned immediate or opcode name for 2-bits opcode.
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@item func7 @tab Unsigned immediate for 7-bits function code.
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@item func6 @tab Unsigned immediate for 6-bits function code.
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@item func4 @tab Unsigned immediate for 4-bits function code.
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@item func3 @tab Unsigned immediate for 3-bits function code.
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@item func2 @tab Unsigned immediate for 2-bits function code.
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@item rd @tab Destination register number for operand x, can be GPR or FPR.
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@item rd' @tab Destination register number for operand x,
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only accept s0-s1, a0-a5, fs0-fs1 and fa0-fa5.
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@item rs1 @tab First source register number for operand x, can be GPR or FPR.
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@item rs1' @tab First source register number for operand x,
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only accept s0-s1, a0-a5, fs0-fs1 and fa0-fa5.
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@item rs2 @tab Second source register number for operand x, can be GPR or FPR.
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@item rs2' @tab Second source register number for operand x,
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only accept s0-s1, a0-a5, fs0-fs1 and fa0-fa5.
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@item simm12 @tab Sign-extended 12-bit immediate for operand x.
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@item simm20 @tab Sign-extended 20-bit immediate for operand x.
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@item simm6 @tab Sign-extended 6-bit immediate for operand x.
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@item uimm8 @tab Unsigned 8-bit immediate for operand x.
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@item symbol @tab Symbol or lable reference for operand x.
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@end multitable
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@end display
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The following table lists all available opcode name:
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@table @code
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@item C0
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@item C1
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@item C2
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Opcode space for compressed instructions.
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@item LOAD
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Opcode space for load instructions.
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@item LOAD_FP
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Opcode space for floating-point load instructions.
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@item STORE
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Opcode space for store instructions.
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@item STORE_FP
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Opcode space for floating-point store instructions.
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@item AUIPC
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Opcode space for auipc instruction.
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@item LUI
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Opcode space for lui instruction.
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@item BRANCH
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Opcode space for branch instructions.
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@item JAL
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Opcode space for jal instruction.
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@item JALR
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Opcode space for jalr instruction.
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@item OP
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Opcode space for ALU instructions.
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@item OP_32
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Opcode space for 32-bits ALU instructions.
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@item OP_IMM
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Opcode space for ALU with immediate instructions.
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@item OP_IMM_32
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Opcode space for 32-bits ALU with immediate instructions.
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@item OP_FP
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Opcode space for floating-point operation instructions.
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@item MADD
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Opcode space for madd instruction.
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@item MSUB
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Opcode space for msub instruction.
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@item NMADD
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Opcode space for nmadd instruction.
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@item NMSUB
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Opcode space for msub instruction.
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@item AMO
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Opcode space for atomic memory operation instructions.
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@item MISC_MEM
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Opcode space for misc instructions.
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@item SYSTEM
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Opcode space for system instructions.
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@item CUSTOM_0
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@item CUSTOM_1
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@item CUSTOM_2
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@item CUSTOM_3
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Opcode space for customize instructions.
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@end table
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An instruction is two or four bytes in length and must be aligned
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on a 2 byte boundary. The first two bits of the instruction specify the
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length of the instruction, 00, 01 and 10 indicates a two byte instruction,
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11 indicates a four byte instruction.
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The following table lists the RISC-V instruction formats that are available
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with the @samp{.insn} pseudo directive:
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@table @code
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@item R type: .insn r opcode, func3, func7, rd, rs1, rs2
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@verbatim
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+-------+-----+-----+-------+----+-------------+
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| func7 | rs2 | rs1 | func3 | rd | opcode |
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+-------+-----+-----+-------+----+-------------+
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31 25 20 15 12 7 0
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@end verbatim
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@item R type with 4 register operands: .insn r opcode, func3, func2, rd, rs1, rs2, rs3
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@itemx R4 type: .insn r4 opcode, func3, func2, rd, rs1, rs2, rs3
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@verbatim
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+-----+-------+-----+-----+-------+----+-------------+
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| rs3 | func2 | rs2 | rs1 | func3 | rd | opcode |
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+-----+-------+-----+-----+-------+----+-------------+
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31 27 25 20 15 12 7 0
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@end verbatim
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@item I type: .insn i opcode, func3, rd, rs1, simm12
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@verbatim
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+-------------+-----+-------+----+-------------+
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| simm12 | rs1 | func3 | rd | opcode |
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+-------------+-----+-------+----+-------------+
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31 20 15 12 7 0
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@end verbatim
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@item S type: .insn s opcode, func3, rd, rs1, simm12
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@verbatim
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+--------------+-----+-----+-------+-------------+-------------+
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| simm12[11:5] | rs2 | rs1 | func3 | simm12[4:0] | opcode |
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+--------------+-----+-----+-------+-------------+-------------+
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31 25 20 15 12 7 0
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@end verbatim
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@item SB type: .insn sb opcode, func3, rd, rs1, symbol
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@itemx SB type: .insn sb opcode, func3, rd, simm12(rs1)
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@itemx B type: .insn s opcode, func3, rd, rs1, symbol
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@itemx B type: .insn s opcode, func3, rd, simm12(rs1)
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@verbatim
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+------------+--------------+-----+-----+-------+-------------+-------------+--------+
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| simm12[12] | simm12[10:5] | rs2 | rs1 | func3 | simm12[4:1] | simm12[11]] | opcode |
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+------------+--------------+-----+-----+-------+-------------+-------------+--------+
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31 30 25 20 15 12 7 0
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@end verbatim
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@item U type: .insn u opcode, rd, simm20
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@verbatim
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+---------------------------+----+-------------+
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| simm20 | rd | opcode |
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+---------------------------+----+-------------+
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31 12 7 0
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@end verbatim
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@item UJ type: .insn uj opcode, rd, symbol
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@itemx J type: .insn j opcode, rd, symbol
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@verbatim
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+------------+--------------+------------+---------------+----+-------------+
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| simm20[20] | simm20[10:1] | simm20[11] | simm20[19:12] | rd | opcode |
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+------------+--------------+------------+---------------+----+-------------+
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31 30 21 20 12 7 0
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@end verbatim
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@item CR type: .insn cr opcode2, func4, rd, rs2
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@verbatim
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+---------+--------+-----+---------+
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| func4 | rd/rs1 | rs2 | opcode2 |
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+---------+--------+-----+---------+
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15 12 7 2 0
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@end verbatim
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@item CI type: .insn ci opcode2, func3, rd, simm6
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@verbatim
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+---------+-----+--------+-----+---------+
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| func3 | imm | rd/rs1 | imm | opcode2 |
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+---------+-----+--------+-----+---------+
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15 13 12 7 2 0
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@end verbatim
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@item CIW type: .insn ciw opcode2, func3, rd, uimm8
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@verbatim
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+---------+--------------+-----+---------+
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| func3 | imm | rd' | opcode2 |
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+---------+--------------+-----+---------+
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15 13 7 2 0
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@end verbatim
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@item CA type: .insn ca opcode2, func6, func2, rd, rs2
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@verbatim
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+---------+----------+-------+------+--------+
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| func6 | rd'/rs1' | func2 | rs2' | opcode |
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+---------+----------+-------+------+--------+
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15 10 7 5 2 0
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@end verbatim
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@item CB type: .insn cb opcode2, func3, rs1, symbol
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@verbatim
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+---------+--------+------+--------+---------+
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| func3 | offset | rs1' | offset | opcode2 |
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+---------+--------+------+--------+---------+
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15 13 10 7 2 0
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@end verbatim
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@item CJ type: .insn cj opcode2, symbol
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@verbatim
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+---------+--------------------+---------+
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| func3 | jump target | opcode2 |
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+---------+--------------------+---------+
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15 13 7 2 0
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@end verbatim
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@end table
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For the complete list of all instruction format variants see
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The RISC-V Instruction Set Manual Volume I: User-Level ISA.
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@node RISC-V-ATTRIBUTE
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@section RISC-V Object Attribute
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@cindex Object Attribute, RISC-V
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RISC-V attributes have a string value if the tag number is odd and an integer
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value if the tag number is even.
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@table @r
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@item Tag_RISCV_stack_align (4)
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Tag_RISCV_strict_align records the N-byte stack alignment for this object. The
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default value is 16 for RV32I or RV64I, and 4 for RV32E.
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The smallest value will be used if object files with different
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Tag_RISCV_stack_align values are merged.
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@item Tag_RISCV_arch (5)
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Tag_RISCV_arch contains a string for the target architecture taken from the
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option @option{-march}. Different architectures will be integrated into a
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superset when object files are merged.
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Note that the version information of the target architecture must be presented
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explicitly in the attribute and abbreviations must be expanded. The version
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information, if not given by @option{-march}, must be in accordance with the
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default specified by the tool. For example, the architecture @code{RV32I} has
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to be recorded in the attribute as @code{RV32I2P0} in which @code{2P0} stands
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for the default version of its base ISA. On the other hand, the architecture
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@code{RV32G} has to be presented as @code{RV32I2P0_M2P0_A2P0_F2P0_D2P0} in
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which the abbreviation @code{G} is expanded to the @code{IMAFD} combination
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with default versions of the standard extensions.
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@item Tag_RISCV_unaligned_access (6)
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Tag_RISCV_unaligned_access is 0 for files that do not allow any unaligned
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memory accesses, and 1 for files that do allow unaligned memory accesses.
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@item Tag_RISCV_priv_spec (8)
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@item Tag_RISCV_priv_spec_minor (10)
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@item Tag_RISCV_priv_spec_revision (12)
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Tag_RISCV_priv_spec contains the major/minor/revision version information of
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the privileged specification. It will report errors if object files of
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different privileged specification versions are merged.
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@end table
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