730 lines
20 KiB
C
730 lines
20 KiB
C
/* ARC target-dependent stuff.
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Copyright 1995, 1996, 1999, 2000, 2001 Free Software Foundation, Inc.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place - Suite 330,
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Boston, MA 02111-1307, USA. */
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#include "defs.h"
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#include "frame.h"
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#include "inferior.h"
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#include "gdbcore.h"
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#include "target.h"
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#include "floatformat.h"
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#include "symtab.h"
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#include "gdbcmd.h"
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#include "regcache.h"
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/* Local functions */
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static int arc_set_cpu_type (char *str);
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/* Current CPU, set with the "set cpu" command. */
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static int arc_bfd_mach_type;
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char *arc_cpu_type;
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char *tmp_arc_cpu_type;
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/* Table of cpu names. */
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struct
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{
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char *name;
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int value;
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}
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arc_cpu_type_table[] =
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{
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{ "arc5", bfd_mach_arc_5 },
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{ "arc6", bfd_mach_arc_6 },
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{ "arc7", bfd_mach_arc_7 },
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{ "arc8", bfd_mach_arc_8 },
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{ NULL, 0 }
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};
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/* Used by simulator. */
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int display_pipeline_p;
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int cpu_timer;
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/* This one must have the same type as used in the emulator.
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It's currently an enum so this should be ok for now. */
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int debug_pipeline_p;
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#define ARC_CALL_SAVED_REG(r) ((r) >= 16 && (r) < 24)
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#define OPMASK 0xf8000000
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/* Instruction field accessor macros.
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See the Programmer's Reference Manual. */
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#define X_OP(i) (((i) >> 27) & 0x1f)
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#define X_A(i) (((i) >> 21) & 0x3f)
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#define X_B(i) (((i) >> 15) & 0x3f)
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#define X_C(i) (((i) >> 9) & 0x3f)
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#define X_D(i) ((((i) & 0x1ff) ^ 0x100) - 0x100)
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#define X_L(i) (((((i) >> 5) & 0x3ffffc) ^ 0x200000) - 0x200000)
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#define X_N(i) (((i) >> 5) & 3)
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#define X_Q(i) ((i) & 0x1f)
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/* Return non-zero if X is a short immediate data indicator. */
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#define SHIMM_P(x) ((x) == 61 || (x) == 63)
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/* Return non-zero if X is a "long" (32 bit) immediate data indicator. */
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#define LIMM_P(x) ((x) == 62)
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/* Build a simple instruction. */
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#define BUILD_INSN(op, a, b, c, d) \
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((((op) & 31) << 27) \
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| (((a) & 63) << 21) \
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| (((b) & 63) << 15) \
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| (((c) & 63) << 9) \
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| ((d) & 511))
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/* Codestream stuff. */
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static void codestream_read (unsigned int *, int);
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static void codestream_seek (CORE_ADDR);
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static unsigned int codestream_fill (int);
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#define CODESTREAM_BUFSIZ 16
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static CORE_ADDR codestream_next_addr;
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static CORE_ADDR codestream_addr;
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/* FIXME assumes sizeof (int) == 32? */
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static unsigned int codestream_buf[CODESTREAM_BUFSIZ];
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static int codestream_off;
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static int codestream_cnt;
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#define codestream_tell() \
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(codestream_addr + codestream_off * sizeof (codestream_buf[0]))
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#define codestream_peek() \
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(codestream_cnt == 0 \
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? codestream_fill (1) \
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: codestream_buf[codestream_off])
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#define codestream_get() \
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(codestream_cnt-- == 0 \
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? codestream_fill (0) \
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: codestream_buf[codestream_off++])
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static unsigned int
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codestream_fill (int peek_flag)
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{
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codestream_addr = codestream_next_addr;
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codestream_next_addr += CODESTREAM_BUFSIZ * sizeof (codestream_buf[0]);
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codestream_off = 0;
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codestream_cnt = CODESTREAM_BUFSIZ;
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read_memory (codestream_addr, (char *) codestream_buf,
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CODESTREAM_BUFSIZ * sizeof (codestream_buf[0]));
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/* FIXME: check return code? */
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/* Handle byte order differences -> convert to host byte ordering. */
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{
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int i;
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for (i = 0; i < CODESTREAM_BUFSIZ; i++)
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codestream_buf[i] =
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extract_unsigned_integer (&codestream_buf[i],
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sizeof (codestream_buf[i]));
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}
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if (peek_flag)
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return codestream_peek ();
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else
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return codestream_get ();
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}
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static void
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codestream_seek (CORE_ADDR place)
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{
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codestream_next_addr = place / CODESTREAM_BUFSIZ;
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codestream_next_addr *= CODESTREAM_BUFSIZ;
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codestream_cnt = 0;
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codestream_fill (1);
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while (codestream_tell () != place)
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codestream_get ();
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}
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/* This function is currently unused but leave in for now. */
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static void
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codestream_read (unsigned int *buf, int count)
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{
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unsigned int *p;
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int i;
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p = buf;
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for (i = 0; i < count; i++)
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*p++ = codestream_get ();
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}
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/* Set up prologue scanning and return the first insn. */
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static unsigned int
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setup_prologue_scan (CORE_ADDR pc)
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{
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unsigned int insn;
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codestream_seek (pc);
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insn = codestream_get ();
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return insn;
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}
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/*
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* Find & return amount a local space allocated, and advance codestream to
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* first register push (if any).
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* If entry sequence doesn't make sense, return -1, and leave
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* codestream pointer random.
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*/
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static long
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arc_get_frame_setup (CORE_ADDR pc)
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{
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unsigned int insn;
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/* Size of frame or -1 if unrecognizable prologue. */
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int frame_size = -1;
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/* An initial "sub sp,sp,N" may or may not be for a stdarg fn. */
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int maybe_stdarg_decr = -1;
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insn = setup_prologue_scan (pc);
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/* The authority for what appears here is the home-grown ABI.
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The most recent version is 1.2. */
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/* First insn may be "sub sp,sp,N" if stdarg fn. */
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if ((insn & BUILD_INSN (-1, -1, -1, -1, 0))
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== BUILD_INSN (10, SP_REGNUM, SP_REGNUM, SHIMM_REGNUM, 0))
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{
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maybe_stdarg_decr = X_D (insn);
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insn = codestream_get ();
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}
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if ((insn & BUILD_INSN (-1, 0, -1, -1, -1)) /* st blink,[sp,4] */
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== BUILD_INSN (2, 0, SP_REGNUM, BLINK_REGNUM, 4))
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{
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insn = codestream_get ();
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/* Frame may not be necessary, even though blink is saved.
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At least this is something we recognize. */
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frame_size = 0;
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}
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if ((insn & BUILD_INSN (-1, 0, -1, -1, -1)) /* st fp,[sp] */
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== BUILD_INSN (2, 0, SP_REGNUM, FP_REGNUM, 0))
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{
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insn = codestream_get ();
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if ((insn & BUILD_INSN (-1, -1, -1, -1, 0))
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!= BUILD_INSN (12, FP_REGNUM, SP_REGNUM, SP_REGNUM, 0))
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return -1;
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/* Check for stack adjustment sub sp,sp,N. */
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insn = codestream_peek ();
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if ((insn & BUILD_INSN (-1, -1, -1, 0, 0))
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== BUILD_INSN (10, SP_REGNUM, SP_REGNUM, 0, 0))
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{
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if (LIMM_P (X_C (insn)))
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frame_size = codestream_get ();
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else if (SHIMM_P (X_C (insn)))
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frame_size = X_D (insn);
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else
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return -1;
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if (frame_size < 0)
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return -1;
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codestream_get ();
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/* This sequence is used to get the address of the return
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buffer for a function that returns a structure. */
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insn = codestream_peek ();
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if ((insn & OPMASK) == 0x60000000)
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codestream_get ();
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}
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/* Frameless fn. */
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else
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{
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frame_size = 0;
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}
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}
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/* If we found a "sub sp,sp,N" and nothing else, it may or may not be a
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stdarg fn. The stdarg decrement is not treated as part of the frame size,
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so we have a dilemma: what do we return? For now, if we get a
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"sub sp,sp,N" and nothing else assume this isn't a stdarg fn. One way
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to fix this completely would be to add a bit to the function descriptor
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that says the function is a stdarg function. */
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if (frame_size < 0 && maybe_stdarg_decr > 0)
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return maybe_stdarg_decr;
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return frame_size;
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}
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/* Given a pc value, skip it forward past the function prologue by
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disassembling instructions that appear to be a prologue.
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If FRAMELESS_P is set, we are only testing to see if the function
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is frameless. If it is a frameless function, return PC unchanged.
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This allows a quicker answer. */
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CORE_ADDR
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arc_skip_prologue (CORE_ADDR pc, int frameless_p)
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{
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unsigned int insn;
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int i, frame_size;
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if ((frame_size = arc_get_frame_setup (pc)) < 0)
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return (pc);
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if (frameless_p)
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return frame_size == 0 ? pc : codestream_tell ();
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/* Skip over register saves. */
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for (i = 0; i < 8; i++)
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{
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insn = codestream_peek ();
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if ((insn & BUILD_INSN (-1, 0, -1, 0, 0))
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!= BUILD_INSN (2, 0, SP_REGNUM, 0, 0))
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break; /* not st insn */
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if (!ARC_CALL_SAVED_REG (X_C (insn)))
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break;
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codestream_get ();
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}
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return codestream_tell ();
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}
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/* Return the return address for a frame.
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This is used to implement FRAME_SAVED_PC.
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This is taken from frameless_look_for_prologue. */
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CORE_ADDR
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arc_frame_saved_pc (struct frame_info *frame)
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{
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CORE_ADDR func_start;
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unsigned int insn;
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func_start = get_pc_function_start (frame->pc) + FUNCTION_START_OFFSET;
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if (func_start == 0)
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{
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/* Best guess. */
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return ARC_PC_TO_REAL_ADDRESS (read_memory_integer (FRAME_FP (frame) + 4, 4));
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}
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/* The authority for what appears here is the home-grown ABI.
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The most recent version is 1.2. */
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insn = setup_prologue_scan (func_start);
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/* First insn may be "sub sp,sp,N" if stdarg fn. */
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if ((insn & BUILD_INSN (-1, -1, -1, -1, 0))
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== BUILD_INSN (10, SP_REGNUM, SP_REGNUM, SHIMM_REGNUM, 0))
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insn = codestream_get ();
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/* If the next insn is "st blink,[sp,4]" we can get blink from there.
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Otherwise this is a leaf function and we can use blink. Note that
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this still allows for the case where a leaf function saves/clobbers/
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restores blink. */
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if ((insn & BUILD_INSN (-1, 0, -1, -1, -1)) /* st blink,[sp,4] */
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!= BUILD_INSN (2, 0, SP_REGNUM, BLINK_REGNUM, 4))
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return ARC_PC_TO_REAL_ADDRESS (read_register (BLINK_REGNUM));
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else
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return ARC_PC_TO_REAL_ADDRESS (read_memory_integer (FRAME_FP (frame) + 4, 4));
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}
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/*
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* Parse the first few instructions of the function to see
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* what registers were stored.
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*
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* The startup sequence can be at the start of the function.
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* 'st blink,[sp+4], st fp,[sp], mov fp,sp'
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*
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* Local space is allocated just below by sub sp,sp,nnn.
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* Next, the registers used by this function are stored (as offsets from sp).
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*/
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void
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frame_find_saved_regs (struct frame_info *fip, struct frame_saved_regs *fsrp)
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{
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long locals;
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unsigned int insn;
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CORE_ADDR dummy_bottom;
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CORE_ADDR adr;
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int i, regnum, offset;
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memset (fsrp, 0, sizeof *fsrp);
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/* If frame is the end of a dummy, compute where the beginning would be. */
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dummy_bottom = fip->frame - 4 - REGISTER_BYTES - CALL_DUMMY_LENGTH;
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/* Check if the PC is in the stack, in a dummy frame. */
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if (dummy_bottom <= fip->pc && fip->pc <= fip->frame)
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{
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/* all regs were saved by push_call_dummy () */
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adr = fip->frame;
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for (i = 0; i < NUM_REGS; i++)
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{
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adr -= REGISTER_RAW_SIZE (i);
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fsrp->regs[i] = adr;
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}
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return;
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}
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locals = arc_get_frame_setup (get_pc_function_start (fip->pc));
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if (locals >= 0)
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{
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/* Set `adr' to the value of `sp'. */
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adr = fip->frame - locals;
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for (i = 0; i < 8; i++)
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{
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insn = codestream_get ();
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if ((insn & BUILD_INSN (-1, 0, -1, 0, 0))
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!= BUILD_INSN (2, 0, SP_REGNUM, 0, 0))
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break;
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regnum = X_C (insn);
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offset = X_D (insn);
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fsrp->regs[regnum] = adr + offset;
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}
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}
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fsrp->regs[PC_REGNUM] = fip->frame + 4;
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fsrp->regs[FP_REGNUM] = fip->frame;
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}
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void
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arc_push_dummy_frame (void)
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{
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CORE_ADDR sp = read_register (SP_REGNUM);
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int regnum;
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char regbuf[MAX_REGISTER_RAW_SIZE];
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read_register_gen (PC_REGNUM, regbuf);
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write_memory (sp + 4, regbuf, REGISTER_SIZE);
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read_register_gen (FP_REGNUM, regbuf);
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write_memory (sp, regbuf, REGISTER_SIZE);
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write_register (FP_REGNUM, sp);
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for (regnum = 0; regnum < NUM_REGS; regnum++)
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{
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read_register_gen (regnum, regbuf);
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sp = push_bytes (sp, regbuf, REGISTER_RAW_SIZE (regnum));
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}
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sp += (2 * REGISTER_SIZE);
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write_register (SP_REGNUM, sp);
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}
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void
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arc_pop_frame (void)
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{
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struct frame_info *frame = get_current_frame ();
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CORE_ADDR fp;
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int regnum;
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struct frame_saved_regs fsr;
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char regbuf[MAX_REGISTER_RAW_SIZE];
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fp = FRAME_FP (frame);
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get_frame_saved_regs (frame, &fsr);
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for (regnum = 0; regnum < NUM_REGS; regnum++)
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{
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CORE_ADDR adr;
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adr = fsr.regs[regnum];
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if (adr)
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{
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read_memory (adr, regbuf, REGISTER_RAW_SIZE (regnum));
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write_register_bytes (REGISTER_BYTE (regnum), regbuf,
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REGISTER_RAW_SIZE (regnum));
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}
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}
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write_register (FP_REGNUM, read_memory_integer (fp, 4));
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write_register (PC_REGNUM, read_memory_integer (fp + 4, 4));
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write_register (SP_REGNUM, fp + 8);
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flush_cached_frames ();
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}
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/* Simulate single-step. */
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typedef enum
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{
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NORMAL4, /* a normal 4 byte insn */
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NORMAL8, /* a normal 8 byte insn */
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BRANCH4, /* a 4 byte branch insn, including ones without delay slots */
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BRANCH8, /* an 8 byte branch insn, including ones with delay slots */
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}
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insn_type;
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/* Return the type of INSN and store in TARGET the destination address of a
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branch if this is one. */
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/* ??? Need to verify all cases are properly handled. */
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static insn_type
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get_insn_type (unsigned long insn, CORE_ADDR pc, CORE_ADDR *target)
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{
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unsigned long limm;
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switch (insn >> 27)
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{
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case 0:
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case 1:
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case 2: /* load/store insns */
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if (LIMM_P (X_A (insn))
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|| LIMM_P (X_B (insn))
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|| LIMM_P (X_C (insn)))
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return NORMAL8;
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return NORMAL4;
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case 4:
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case 5:
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case 6: /* branch insns */
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*target = pc + 4 + X_L (insn);
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/* ??? It isn't clear that this is always the right answer.
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The problem occurs when the next insn is an 8 byte insn. If the
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branch is conditional there's no worry as there shouldn't be an 8
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byte insn following. The programmer may be cheating if s/he knows
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the branch will never be taken, but we don't deal with that.
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Note that the programmer is also allowed to play games by putting
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an insn with long immediate data in the delay slot and then duplicate
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the long immediate data at the branch target. Ugh! */
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if (X_N (insn) == 0)
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return BRANCH4;
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return BRANCH8;
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case 7: /* jump insns */
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if (LIMM_P (X_B (insn)))
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{
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limm = read_memory_integer (pc + 4, 4);
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*target = ARC_PC_TO_REAL_ADDRESS (limm);
|
||
return BRANCH8;
|
||
}
|
||
if (SHIMM_P (X_B (insn)))
|
||
*target = ARC_PC_TO_REAL_ADDRESS (X_D (insn));
|
||
else
|
||
*target = ARC_PC_TO_REAL_ADDRESS (read_register (X_B (insn)));
|
||
if (X_Q (insn) == 0 && X_N (insn) == 0)
|
||
return BRANCH4;
|
||
return BRANCH8;
|
||
default: /* arithmetic insns, etc. */
|
||
if (LIMM_P (X_A (insn))
|
||
|| LIMM_P (X_B (insn))
|
||
|| LIMM_P (X_C (insn)))
|
||
return NORMAL8;
|
||
return NORMAL4;
|
||
}
|
||
}
|
||
|
||
/* single_step() is called just before we want to resume the inferior, if we
|
||
want to single-step it but there is no hardware or kernel single-step
|
||
support. We find all the possible targets of the coming instruction and
|
||
breakpoint them.
|
||
|
||
single_step is also called just after the inferior stops. If we had
|
||
set up a simulated single-step, we undo our damage. */
|
||
|
||
void
|
||
arc_software_single_step (enum target_signal ignore, /* sig but we don't need it */
|
||
int insert_breakpoints_p)
|
||
{
|
||
static CORE_ADDR next_pc, target;
|
||
static int brktrg_p;
|
||
typedef char binsn_quantum[BREAKPOINT_MAX];
|
||
static binsn_quantum break_mem[2];
|
||
|
||
if (insert_breakpoints_p)
|
||
{
|
||
insn_type type;
|
||
CORE_ADDR pc;
|
||
unsigned long insn;
|
||
|
||
pc = read_register (PC_REGNUM);
|
||
insn = read_memory_integer (pc, 4);
|
||
type = get_insn_type (insn, pc, &target);
|
||
|
||
/* Always set a breakpoint for the insn after the branch. */
|
||
next_pc = pc + ((type == NORMAL8 || type == BRANCH8) ? 8 : 4);
|
||
target_insert_breakpoint (next_pc, break_mem[0]);
|
||
|
||
brktrg_p = 0;
|
||
|
||
if ((type == BRANCH4 || type == BRANCH8)
|
||
/* Watch out for branches to the following location.
|
||
We just stored a breakpoint there and another call to
|
||
target_insert_breakpoint will think the real insn is the
|
||
breakpoint we just stored there. */
|
||
&& target != next_pc)
|
||
{
|
||
brktrg_p = 1;
|
||
target_insert_breakpoint (target, break_mem[1]);
|
||
}
|
||
|
||
}
|
||
else
|
||
{
|
||
/* Remove breakpoints. */
|
||
target_remove_breakpoint (next_pc, break_mem[0]);
|
||
|
||
if (brktrg_p)
|
||
target_remove_breakpoint (target, break_mem[1]);
|
||
|
||
/* Fix the pc. */
|
||
stop_pc -= DECR_PC_AFTER_BREAK;
|
||
write_pc (stop_pc);
|
||
}
|
||
}
|
||
|
||
/* Because of Multi-arch, GET_LONGJMP_TARGET is always defined. So test
|
||
for a definition of JB_PC. */
|
||
#ifdef JB_PC
|
||
/* Figure out where the longjmp will land. Slurp the args out of the stack.
|
||
We expect the first arg to be a pointer to the jmp_buf structure from which
|
||
we extract the pc (JB_PC) that we will land at. The pc is copied into PC.
|
||
This routine returns true on success. */
|
||
|
||
int
|
||
get_longjmp_target (CORE_ADDR *pc)
|
||
{
|
||
char buf[TARGET_PTR_BIT / TARGET_CHAR_BIT];
|
||
CORE_ADDR sp, jb_addr;
|
||
|
||
sp = read_register (SP_REGNUM);
|
||
|
||
if (target_read_memory (sp + SP_ARG0, /* Offset of first arg on stack */
|
||
buf,
|
||
TARGET_PTR_BIT / TARGET_CHAR_BIT))
|
||
return 0;
|
||
|
||
jb_addr = extract_address (buf, TARGET_PTR_BIT / TARGET_CHAR_BIT);
|
||
|
||
if (target_read_memory (jb_addr + JB_PC * JB_ELEMENT_SIZE, buf,
|
||
TARGET_PTR_BIT / TARGET_CHAR_BIT))
|
||
return 0;
|
||
|
||
*pc = extract_address (buf, TARGET_PTR_BIT / TARGET_CHAR_BIT);
|
||
|
||
return 1;
|
||
}
|
||
#endif /* GET_LONGJMP_TARGET */
|
||
|
||
/* Disassemble one instruction. */
|
||
|
||
static int
|
||
arc_print_insn (bfd_vma vma, disassemble_info *info)
|
||
{
|
||
static int current_mach;
|
||
static int current_endian;
|
||
static disassembler_ftype current_disasm;
|
||
|
||
if (current_disasm == NULL
|
||
|| arc_bfd_mach_type != current_mach
|
||
|| TARGET_BYTE_ORDER != current_endian)
|
||
{
|
||
current_mach = arc_bfd_mach_type;
|
||
current_endian = TARGET_BYTE_ORDER;
|
||
current_disasm = arc_get_disassembler (NULL);
|
||
}
|
||
|
||
return (*current_disasm) (vma, info);
|
||
}
|
||
|
||
/* Command to set cpu type. */
|
||
|
||
void
|
||
arc_set_cpu_type_command (char *args, int from_tty)
|
||
{
|
||
int i;
|
||
|
||
if (tmp_arc_cpu_type == NULL || *tmp_arc_cpu_type == '\0')
|
||
{
|
||
printf_unfiltered ("The known ARC cpu types are as follows:\n");
|
||
for (i = 0; arc_cpu_type_table[i].name != NULL; ++i)
|
||
printf_unfiltered ("%s\n", arc_cpu_type_table[i].name);
|
||
|
||
/* Restore the value. */
|
||
tmp_arc_cpu_type = xstrdup (arc_cpu_type);
|
||
|
||
return;
|
||
}
|
||
|
||
if (!arc_set_cpu_type (tmp_arc_cpu_type))
|
||
{
|
||
error ("Unknown cpu type `%s'.", tmp_arc_cpu_type);
|
||
/* Restore its value. */
|
||
tmp_arc_cpu_type = xstrdup (arc_cpu_type);
|
||
}
|
||
}
|
||
|
||
static void
|
||
arc_show_cpu_type_command (char *args, int from_tty)
|
||
{
|
||
}
|
||
|
||
/* Modify the actual cpu type.
|
||
Result is a boolean indicating success. */
|
||
|
||
static int
|
||
arc_set_cpu_type (char *str)
|
||
{
|
||
int i, j;
|
||
|
||
if (str == NULL)
|
||
return 0;
|
||
|
||
for (i = 0; arc_cpu_type_table[i].name != NULL; ++i)
|
||
{
|
||
if (strcasecmp (str, arc_cpu_type_table[i].name) == 0)
|
||
{
|
||
arc_cpu_type = str;
|
||
arc_bfd_mach_type = arc_cpu_type_table[i].value;
|
||
return 1;
|
||
}
|
||
}
|
||
|
||
return 0;
|
||
}
|
||
|
||
void
|
||
_initialize_arc_tdep (void)
|
||
{
|
||
struct cmd_list_element *c;
|
||
|
||
c = add_set_cmd ("cpu", class_support, var_string_noescape,
|
||
(char *) &tmp_arc_cpu_type,
|
||
"Set the type of ARC cpu in use.\n\
|
||
This command has two purposes. In a multi-cpu system it lets one\n\
|
||
change the cpu being debugged. It also gives one access to\n\
|
||
cpu-type-specific registers and recognize cpu-type-specific instructions.\
|
||
",
|
||
&setlist);
|
||
set_cmd_cfunc (c, arc_set_cpu_type_command);
|
||
c = add_show_from_set (c, &showlist);
|
||
set_cmd_cfunc (c, arc_show_cpu_type_command);
|
||
|
||
/* We have to use xstrdup() here because the `set' command frees it
|
||
before setting a new value. */
|
||
tmp_arc_cpu_type = xstrdup (DEFAULT_ARC_CPU_TYPE);
|
||
arc_set_cpu_type (tmp_arc_cpu_type);
|
||
|
||
c = add_set_cmd ("displaypipeline", class_support, var_zinteger,
|
||
(char *) &display_pipeline_p,
|
||
"Set pipeline display (simulator only).\n\
|
||
When enabled, the state of the pipeline after each cycle is displayed.",
|
||
&setlist);
|
||
c = add_show_from_set (c, &showlist);
|
||
|
||
c = add_set_cmd ("debugpipeline", class_support, var_zinteger,
|
||
(char *) &debug_pipeline_p,
|
||
"Set pipeline debug display (simulator only).\n\
|
||
When enabled, debugging information about the pipeline is displayed.",
|
||
&setlist);
|
||
c = add_show_from_set (c, &showlist);
|
||
|
||
c = add_set_cmd ("cputimer", class_support, var_zinteger,
|
||
(char *) &cpu_timer,
|
||
"Set maximum cycle count (simulator only).\n\
|
||
Control will return to gdb if the timer expires.\n\
|
||
A negative value disables the timer.",
|
||
&setlist);
|
||
c = add_show_from_set (c, &showlist);
|
||
|
||
tm_print_insn = arc_print_insn;
|
||
}
|