616 lines
19 KiB
C
616 lines
19 KiB
C
/* Disassembly routines for TMS320C54X architecture
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Copyright (C) 1999,2000 Free Software Foundation, Inc.
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Contributed by Timothy Wall (twall@cygnus.com)
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
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02111-1307, USA. */
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#include <errno.h>
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#include <math.h>
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#include <stdlib.h>
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#include "sysdep.h"
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#include "dis-asm.h"
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#include "opcode/tic54x.h"
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#include "coff/tic54x.h"
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typedef struct _instruction {
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int parallel;
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template *tm;
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partemplate *ptm;
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} instruction;
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static int get_insn_size PARAMS ((unsigned short, instruction *));
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static int get_instruction PARAMS ((disassemble_info *, bfd_vma,
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unsigned short, instruction *));
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static int print_instruction PARAMS ((disassemble_info *, bfd_vma,
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unsigned short, char *,
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enum optype [], int, int));
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static int print_parallel_instruction PARAMS ((disassemble_info *, bfd_vma,
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unsigned short, partemplate *,
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int));
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static int sprint_dual_address (disassemble_info *,char [],
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unsigned short);
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static int sprint_indirect_address (disassemble_info *,char [],
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unsigned short);
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static int sprint_direct_address (disassemble_info *,char [],
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unsigned short);
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static int sprint_mmr (disassemble_info *,char [],int);
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static int sprint_condition (disassemble_info *,char *,unsigned short);
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static int sprint_cc2 (disassemble_info *,char *,unsigned short);
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int
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print_insn_tic54x(memaddr, info)
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bfd_vma memaddr;
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disassemble_info *info;
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{
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bfd_byte opbuf[2];
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unsigned short opcode;
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int status, size;
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instruction insn;
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status = (*info->read_memory_func) (memaddr, opbuf, 2, info);
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if (status != 0)
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{
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(*info->memory_error_func)(status, memaddr, info);
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return -1;
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}
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opcode = bfd_getl16(opbuf);
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if (!get_instruction (info, memaddr, opcode, &insn))
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return -1;
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size = get_insn_size (opcode, &insn);
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info->bytes_per_line = 2;
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info->bytes_per_chunk = 2;
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info->octets_per_byte = 2;
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info->display_endian = BFD_ENDIAN_LITTLE;
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if (insn.parallel)
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{
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if (!print_parallel_instruction (info, memaddr, opcode, insn.ptm, size))
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return -1;
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}
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else
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{
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if (!print_instruction (info, memaddr, opcode,
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(char *)insn.tm->name,
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insn.tm->operand_types,
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size, (insn.tm->flags & FL_EXT)))
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return -1;
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}
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return size*2;
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}
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static int
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has_lkaddr(opcode, tm)
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unsigned short opcode;
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template *tm;
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{
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return IS_LKADDR(opcode) &&
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(OPTYPE(tm->operand_types[0]) == OP_Smem ||
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OPTYPE(tm->operand_types[1]) == OP_Smem ||
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OPTYPE(tm->operand_types[2]) == OP_Smem ||
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OPTYPE(tm->operand_types[1]) == OP_Sind);
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}
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/* always returns 1 (whether an insn template was found) since we provide an
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"unknown instruction" template */
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static int
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get_instruction (info, addr, opcode, insn)
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disassemble_info *info;
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bfd_vma addr;
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unsigned short opcode;
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instruction *insn;
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{
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template * tm;
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partemplate * ptm;
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insn->parallel = 0;
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for (tm = (template *)tic54x_optab; tm->name; tm++)
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{
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if (tm->opcode == (opcode & tm->mask))
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{
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/* a few opcodes span two words */
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if (tm->flags & FL_EXT)
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{
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/* if lk addressing is used, the second half of the opcode gets
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pushed one word later */
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bfd_byte opbuf[2];
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bfd_vma addr2 = addr + 1 + has_lkaddr(opcode, tm);
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int status = (*info->read_memory_func)(addr2, opbuf, 2, info);
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if (status == 0)
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{
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unsigned short opcode2 = bfd_getl16(opbuf);
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if (tm->opcode2 == (opcode2 & tm->mask2))
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{
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insn->tm = tm;
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return 1;
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}
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}
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}
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else
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{
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insn->tm = tm;
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return 1;
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}
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}
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}
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for (ptm = (partemplate *)tic54x_paroptab; ptm->name; ptm++)
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{
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if (ptm->opcode == (opcode & ptm->mask))
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{
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insn->parallel = 1;
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insn->ptm = ptm;
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return 1;
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}
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}
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insn->tm = (template *)&tic54x_unknown_opcode;
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return 1;
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}
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static int
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get_insn_size (opcode, insn)
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unsigned short opcode;
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instruction *insn;
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{
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int size;
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if (insn->parallel)
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{
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/* only non-parallel instructions support lk addressing */
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size = insn->ptm->words;
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}
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else
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{
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size = insn->tm->words + has_lkaddr(opcode, insn->tm);
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}
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return size;
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}
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int
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print_instruction (info, memaddr, opcode, tm_name, tm_operands, size, ext)
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disassemble_info *info;
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bfd_vma memaddr;
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unsigned short opcode;
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char *tm_name;
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enum optype tm_operands[];
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int size;
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int ext;
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{
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static int n;
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/* string storage for multiple operands */
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char operand[4][64] = { {0},{0},{0},{0}, };
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bfd_byte buf[2];
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unsigned long opcode2, lkaddr;
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enum optype src = OP_None;
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enum optype dst = OP_None;
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int i, shift;
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char *comma = "";
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info->fprintf_func (info->stream, "%-7s", tm_name);
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if (size > 1)
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{
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int status = (*info->read_memory_func) (memaddr+1, buf, 2, info);
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if (status != 0)
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return 0;
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lkaddr = opcode2 = bfd_getl16(buf);
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if (size > 2)
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{
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status = (*info->read_memory_func) (memaddr+2, buf, 2, info);
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if (status != 0)
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return 0;
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opcode2 = bfd_getl16(buf);
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}
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}
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for (i=0;i < MAX_OPERANDS && OPTYPE(tm_operands[i]) != OP_None;i++)
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{
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char *next_comma = ",";
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int optional = (tm_operands[i] & OPT) != 0;
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switch (OPTYPE(tm_operands[i]))
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{
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case OP_Xmem:
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sprint_dual_address (info, operand[i], XMEM(opcode));
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info->fprintf_func (info->stream, "%s%s", comma, operand[i]);
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break;
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case OP_Ymem:
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sprint_dual_address (info, operand[i], YMEM(opcode));
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info->fprintf_func (info->stream, "%s%s", comma, operand[i]);
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break;
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case OP_Smem:
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case OP_Sind:
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case OP_Lmem:
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info->fprintf_func (info->stream, "%s", comma);
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if (INDIRECT(opcode))
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{
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if (MOD(opcode) >= 12)
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{
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bfd_vma addr = lkaddr;
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int arf = ARF(opcode);
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int mod = MOD(opcode);
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if (mod == 15)
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info->fprintf_func (info->stream, "*(");
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else
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info->fprintf_func (info->stream, "*%sar%d(",
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(mod == 13 || mod == 14 ? "+" : ""),
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arf);
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(*(info->print_address_func))((bfd_vma)addr, info);
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info->fprintf_func (info->stream, ")%s",
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mod == 14 ? "%" : "");
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}
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else
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{
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sprint_indirect_address (info, operand[i], opcode);
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info->fprintf_func (info->stream, "%s", operand[i]);
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}
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}
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else
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{
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/* FIXME -- use labels (print_address_func) */
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/* in order to do this, we need to guess what DP is */
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sprint_direct_address (info, operand[i], opcode);
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info->fprintf_func (info->stream, "%s", operand[i]);
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}
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break;
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case OP_dmad:
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info->fprintf_func (info->stream, "%s", comma);
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(*(info->print_address_func))((bfd_vma)opcode2, info);
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break;
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case OP_xpmad:
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/* upper 7 bits of address are in the opcode */
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opcode2 += ((unsigned long)opcode & 0x7F) << 16;
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/* fall through */
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case OP_pmad:
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info->fprintf_func (info->stream, "%s", comma);
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(*(info->print_address_func))((bfd_vma)opcode2, info);
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break;
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case OP_MMRX:
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sprint_mmr (info, operand[i], MMRX(opcode));
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info->fprintf_func (info->stream, "%s%s", comma, operand[i]);
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break;
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case OP_MMRY:
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sprint_mmr (info, operand[i], MMRY(opcode));
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info->fprintf_func (info->stream, "%s%s", comma, operand[i]);
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break;
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case OP_MMR:
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sprint_mmr (info, operand[i], MMR(opcode));
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info->fprintf_func (info->stream, "%s%s", comma, operand[i]);
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break;
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case OP_PA:
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sprintf (operand[i], "pa%d", (unsigned)opcode2);
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info->fprintf_func (info->stream, "%s%s", comma, operand[i]);
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break;
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case OP_SRC:
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src = SRC(ext ? opcode2 : opcode) ? OP_B : OP_A;
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sprintf (operand[i], (src == OP_B) ? "b" : "a");
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info->fprintf_func (info->stream, "%s%s", comma, operand[i]);
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break;
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case OP_SRC1:
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src = SRC1(ext ? opcode2 : opcode) ? OP_B : OP_A;
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sprintf (operand[i], (src == OP_B) ? "b" : "a");
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info->fprintf_func (info->stream, "%s%s", comma, operand[i]);
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break;
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case OP_RND:
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dst = DST(opcode) ? OP_B : OP_A;
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sprintf (operand[i], (dst == OP_B) ? "a" : "b");
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info->fprintf_func (info->stream, "%s%s", comma, operand[i]);
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break;
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case OP_DST:
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dst = DST(ext ? opcode2 : opcode) ? OP_B : OP_A;
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if (!optional || dst != src)
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{
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sprintf (operand[i], (dst == OP_B) ? "b" : "a");
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info->fprintf_func (info->stream, "%s%s", comma, operand[i]);
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}
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else
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next_comma = comma;
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break;
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case OP_B:
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sprintf (operand[i], "b");
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info->fprintf_func (info->stream, "%s%s", comma, operand[i]);
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break;
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case OP_A:
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sprintf (operand[i], "a");
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info->fprintf_func (info->stream, "%s%s", comma, operand[i]);
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break;
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case OP_ARX:
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sprintf (operand[i],"ar%d", (int)ARX(opcode));
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info->fprintf_func (info->stream, "%s%s", comma, operand[i]);
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break;
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case OP_SHIFT:
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shift = SHIFT(ext ? opcode2 : opcode);
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if (!optional || shift != 0)
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{
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sprintf (operand[i],"%d", shift);
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info->fprintf_func (info->stream, "%s%s", comma, operand[i]);
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}
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else
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next_comma = comma;
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break;
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case OP_SHFT:
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shift = SHFT(opcode);
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if (!optional || shift != 0)
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{
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sprintf (operand[i],"%d", (unsigned)shift);
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info->fprintf_func (info->stream, "%s%s", comma, operand[i]);
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}
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else
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next_comma = comma;
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break;
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case OP_lk:
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sprintf (operand[i],"#%d", (int)(short)opcode2);
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info->fprintf_func (info->stream, "%s%s", comma, operand[i]);
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break;
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case OP_T:
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sprintf (operand[i], "t");
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info->fprintf_func (info->stream, "%s%s", comma, operand[i]);
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break;
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case OP_TS:
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sprintf (operand[i], "ts");
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info->fprintf_func (info->stream, "%s%s", comma, operand[i]);
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break;
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case OP_k8:
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sprintf (operand[i], "%d", (int)((signed char)(opcode & 0xFF)));
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info->fprintf_func (info->stream, "%s%s", comma, operand[i]);
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break;
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case OP_16:
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sprintf (operand[i], "16");
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info->fprintf_func (info->stream, "%s%s", comma, operand[i]);
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break;
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case OP_ASM:
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sprintf (operand[i], "asm");
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info->fprintf_func (info->stream, "%s%s", comma, operand[i]);
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break;
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case OP_BITC:
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sprintf (operand[i], "%d", (int)(opcode & 0xF));
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info->fprintf_func (info->stream, "%s%s", comma, operand[i]);
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break;
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case OP_CC:
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/* put all CC operands in the same operand */
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sprint_condition (info, operand[i], opcode);
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info->fprintf_func (info->stream, "%s%s", comma, operand[i]);
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i = MAX_OPERANDS;
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break;
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case OP_CC2:
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sprint_cc2 (info, operand[i], opcode);
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info->fprintf_func (info->stream, "%s%s", comma, operand[i]);
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break;
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case OP_CC3:
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{
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const char *code[] = { "eq", "lt", "gt", "neq" };
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sprintf (operand[i], code[CC3(opcode)]);
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info->fprintf_func (info->stream, "%s%s", comma, operand[i]);
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break;
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}
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case OP_123:
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{
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int code = (opcode>>8) & 0x3;
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sprintf (operand[i], "%d", (code == 0) ? 1 : (code == 2) ? 2 : 3);
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info->fprintf_func (info->stream, "%s%s", comma, operand[i]);
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break;
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}
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case OP_k5:
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sprintf (operand[i], "#%d",
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(int)(((signed char)opcode & 0x1F) << 3)>>3);
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info->fprintf_func (info->stream, "%s%s", comma, operand[i]);
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break;
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case OP_k8u:
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sprintf (operand[i], "#%d", (unsigned)(opcode & 0xFF));
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info->fprintf_func (info->stream, "%s%s", comma, operand[i]);
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break;
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case OP_k3:
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sprintf (operand[i], "#%d", (int)(opcode & 0x7));
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info->fprintf_func (info->stream, "%s%s", comma, operand[i]);
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break;
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case OP_lku:
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sprintf (operand[i], "#%d", (unsigned)opcode2);
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info->fprintf_func (info->stream, "%s%s", comma, operand[i]);
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break;
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case OP_N:
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n = (opcode >> 9) & 0x1;
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sprintf (operand[i], "st%d", n);
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info->fprintf_func (info->stream, "%s%s", comma, operand[i]);
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break;
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case OP_SBIT:
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{
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const char *status0[] = {
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"0", "1", "2", "3", "4", "5", "6", "7", "8",
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"ovb", "ova", "c", "tc", "13", "14", "15"
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};
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const char *status1[] = {
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"0", "1", "2", "3", "4",
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"cmpt", "frct", "c16", "sxm", "ovm", "10",
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"intm", "hm", "xf", "cpl", "braf"
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};
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sprintf (operand[i], "%s",
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n ? status1[SBIT(opcode)] : status0[SBIT(opcode)]);
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info->fprintf_func (info->stream, "%s%s", comma, operand[i]);
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break;
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}
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case OP_12:
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sprintf (operand[i], "%d", (int)((opcode >> 9)&1) + 1);
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info->fprintf_func (info->stream, "%s%s", comma, operand[i]);
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break;
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case OP_TRN:
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sprintf (operand[i], "trn");
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info->fprintf_func (info->stream, "%s%s", comma, operand[i]);
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break;
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case OP_DP:
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sprintf (operand[i], "dp");
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info->fprintf_func (info->stream, "%s%s", comma, operand[i]);
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break;
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case OP_k9:
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/* FIXME-- this is DP, print the original address? */
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sprintf (operand[i], "#%d", (int)(opcode & 0x1FF));
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info->fprintf_func (info->stream, "%s%s", comma, operand[i]);
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break;
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case OP_ARP:
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sprintf (operand[i], "arp");
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info->fprintf_func (info->stream, "%s%s", comma, operand[i]);
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break;
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case OP_031:
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sprintf (operand[i], "%d", (int)(opcode & 0x1F));
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info->fprintf_func (info->stream, "%s%s", comma, operand[i]);
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break;
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default:
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sprintf (operand[i], "??? (0x%x)", tm_operands[i]);
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info->fprintf_func (info->stream, "%s%s", comma, operand[i]);
|
|
break;
|
|
}
|
|
comma = next_comma;
|
|
}
|
|
return 1;
|
|
}
|
|
|
|
static int
|
|
print_parallel_instruction (info, memaddr, opcode, ptm, size)
|
|
disassemble_info *info;
|
|
bfd_vma memaddr;
|
|
unsigned short opcode;
|
|
partemplate *ptm;
|
|
int size;
|
|
{
|
|
print_instruction (info, memaddr, opcode,
|
|
ptm->name, ptm->operand_types, size, 0);
|
|
info->fprintf_func (info->stream, " || ");
|
|
return print_instruction (info, memaddr, opcode,
|
|
ptm->parname, ptm->paroperand_types, size, 0);
|
|
}
|
|
|
|
static int
|
|
sprint_dual_address (info, buf, code)
|
|
disassemble_info *info;
|
|
char buf[];
|
|
unsigned short code;
|
|
{
|
|
const char *formats[] = {
|
|
"*ar%d",
|
|
"*ar%d-",
|
|
"*ar%d+",
|
|
"*ar%d+0%%",
|
|
};
|
|
return sprintf (buf, formats[XMOD(code)], XARX(code));
|
|
}
|
|
|
|
static int
|
|
sprint_indirect_address (info, buf, opcode)
|
|
disassemble_info *info;
|
|
char buf[];
|
|
unsigned short opcode;
|
|
{
|
|
const char *formats[] = {
|
|
"*ar%d",
|
|
"*ar%d-",
|
|
"*ar%d+",
|
|
"*+ar%d",
|
|
"*ar%d-0B",
|
|
"*ar%d-0",
|
|
"*ar%d+0",
|
|
"*ar%d+0B",
|
|
"*ar%d-%%",
|
|
"*ar%d-0%%",
|
|
"*ar%d+%%",
|
|
"*ar%d+0%%",
|
|
};
|
|
return sprintf (buf, formats[MOD(opcode)], ARF(opcode));
|
|
}
|
|
|
|
static int
|
|
sprint_direct_address (info, buf, opcode)
|
|
disassemble_info *info;
|
|
char buf[];
|
|
unsigned short opcode;
|
|
{
|
|
/* FIXME -- look up relocation if available */
|
|
return sprintf (buf, "0x??%02x", (int)(opcode & 0x7F));
|
|
}
|
|
|
|
static int
|
|
sprint_mmr (info, buf, mmr)
|
|
disassemble_info *info;
|
|
char buf[];
|
|
int mmr;
|
|
{
|
|
symbol *reg = (symbol *)mmregs;
|
|
while (reg->name != NULL)
|
|
{
|
|
if (mmr == reg->value)
|
|
{
|
|
sprintf (buf, "%s", (reg+1)->name);
|
|
return 1;
|
|
}
|
|
++reg;
|
|
}
|
|
sprintf (buf, "MMR(%d)", mmr); /* FIXME -- different targets. */
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
sprint_cc2 (info, buf, opcode)
|
|
disassemble_info *info;
|
|
char *buf;
|
|
unsigned short opcode;
|
|
{
|
|
const char *cc2[] = {
|
|
"??", "??", "ageq", "alt", "aneq", "aeq", "agt", "aleq",
|
|
"??", "??", "bgeq", "blt", "bneq", "beq", "bgt", "bleq",
|
|
};
|
|
return sprintf (buf, "%s", cc2[opcode & 0xF]);
|
|
}
|
|
|
|
static int
|
|
sprint_condition (info, buf, opcode)
|
|
disassemble_info *info;
|
|
char *buf;
|
|
unsigned short opcode;
|
|
{
|
|
char *start = buf;
|
|
const char *cmp[] = {
|
|
"??", "??", "geq", "lt", "neq", "eq", "gt", "leq"
|
|
};
|
|
if (opcode & 0x40)
|
|
{
|
|
char acc = (opcode & 0x8) ? 'b' : 'a';
|
|
if (opcode & 0x7)
|
|
buf += sprintf (buf, "%c%s%s", acc, cmp[(opcode&0x7)],
|
|
(opcode&0x20) ? ", " : "");
|
|
if (opcode & 0x20)
|
|
buf += sprintf (buf, "%c%s", acc, (opcode&0x10) ? "ov" : "nov");
|
|
}
|
|
else if (opcode & 0x3F)
|
|
{
|
|
if (opcode & 0x30)
|
|
buf += sprintf (buf, "%s%s",
|
|
((opcode & 0x30) == 0x30) ? "tc" : "ntc",
|
|
(opcode & 0x0F) ? ", " : "");
|
|
if (opcode & 0x0C)
|
|
buf += sprintf (buf, "%s%s",
|
|
((opcode & 0x0C) == 0x0C) ? "c" : "nc",
|
|
(opcode & 0x03) ? ", " : "");
|
|
if (opcode & 0x03)
|
|
buf += sprintf (buf, "%s",
|
|
((opcode & 0x03) == 0x03) ? "bio" : "nbio");
|
|
}
|
|
else
|
|
buf += sprintf (buf, "unc");
|
|
|
|
return buf - start;
|
|
}
|