414 lines
11 KiB
C
414 lines
11 KiB
C
/* This file is part of the program GDB, the GNU debugger.
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Copyright (C) 1998 Free Software Foundation, Inc.
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Contributed by Cygnus Solutions.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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#include "sim-main.h"
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#include "hw-main.h"
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/* DEVICE
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tx3904irc - tx3904 interrupt controller
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DESCRIPTION
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Implements the tx3904 interrupt controller described in the tx3904
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user guide. It does not include the interrupt detection circuit
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that preprocesses the eight external interrupts, so assumes that
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each event on an input interrupt port signals a new interrupt.
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That is, it implements edge- rather than level-triggered
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interrupts.
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This implementation does not support multiple concurrent
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interrupts.
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PROPERTIES
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reg <base> <length>
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Base of IRC control register bank. <length> must equal 0x20.
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Registers offsets: 0: ISR: interrupt status register
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4: IMR: interrupt mask register
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16: ILR0: interrupt level register 3..0
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20: ILR1: interrupt level register 7..4
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24: ILR2: interrupt level register 11..8
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28: ILR3: interrupt level register 15..12
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PORTS
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ip (output)
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Interrupt priority port. An event is generated when an interrupt
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of a sufficient priority is passed through the IRC. The value
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associated with the event is the interrupt level (16-31), as given
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for bits IP[5:0] in the book TMPR3904F Rev. 2.0, pg. 11-3. Note
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that even though INT[0] is tied externally to IP[5], we simulate
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it as passing through the controller.
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An output level of zero signals the clearing of a level interrupt.
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int0-7 (input)
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External interrupts. Level = 0 -> level interrupt cleared.
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dmac0-3 (input)
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DMA internal interrupts, correspond to DMA channels 0-3. Level = 0 -> level interrupt cleared.
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sio0-1 (input)
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SIO internal interrupts. Level = 0 -> level interrupt cleared.
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tmr0-2 (input)
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Timer internal interrupts. Level = 0 -> level interrupt cleared.
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*/
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/* register numbers; each is one word long */
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enum
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{
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ISR_REG = 0,
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IMR_REG = 1,
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ILR0_REG = 4,
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ILR1_REG = 5,
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ILR2_REG = 6,
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ILR3_REG = 7,
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};
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/* port ID's */
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enum
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{
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/* inputs, ordered to correspond to interrupt sources 0..15 */
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INT1_PORT = 0, INT2_PORT, INT3_PORT, INT4_PORT, INT5_PORT, INT6_PORT, INT7_PORT,
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DMAC3_PORT, DMAC2_PORT, DMAC1_PORT, DMAC0_PORT, SIO0_PORT, SIO1_PORT,
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TMR0_PORT, TMR1_PORT, TMR2_PORT,
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/* special INT[0] port */
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INT0_PORT,
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/* reset */
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RESET_PORT,
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/* output */
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IP_PORT
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};
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static const struct hw_port_descriptor tx3904irc_ports[] = {
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/* interrupt output */
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{ "ip", IP_PORT, 0, output_port, },
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/* interrupt inputs (as names) */
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/* in increasing order of level number */
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{ "int1", INT1_PORT, 0, input_port, },
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{ "int2", INT2_PORT, 0, input_port, },
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{ "int3", INT3_PORT, 0, input_port, },
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{ "int4", INT4_PORT, 0, input_port, },
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{ "int5", INT5_PORT, 0, input_port, },
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{ "int6", INT6_PORT, 0, input_port, },
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{ "int7", INT7_PORT, 0, input_port, },
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{ "dmac3", DMAC3_PORT, 0, input_port, },
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{ "dmac2", DMAC2_PORT, 0, input_port, },
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{ "dmac1", DMAC1_PORT, 0, input_port, },
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{ "dmac0", DMAC0_PORT, 0, input_port, },
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{ "sio0", SIO0_PORT, 0, input_port, },
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{ "sio1", SIO1_PORT, 0, input_port, },
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{ "tmr0", TMR0_PORT, 0, input_port, },
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{ "tmr1", TMR1_PORT, 0, input_port, },
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{ "tmr2", TMR2_PORT, 0, input_port, },
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{ "reset", RESET_PORT, 0, input_port, },
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{ "int0", INT0_PORT, 0, input_port, },
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{ NULL, },
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};
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#define NR_SOURCES (TMR3_PORT - INT1_PORT + 1) /* 16: number of interrupt sources */
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/* The interrupt controller register internal state. Note that we
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store state using the control register images, in host endian
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order. */
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struct tx3904irc {
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address_word base_address; /* control register base */
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unsigned_4 isr;
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#define ISR_SET(c,s) ((c)->isr &= ~ (1 << (s)))
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unsigned_4 imr;
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#define IMR_GET(c) ((c)->imr)
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unsigned_4 ilr[4];
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#define ILR_GET(c,s) LSEXTRACTED32((c)->ilr[(s)/4], (s) % 4 * 8 + 2, (s) % 4 * 8)
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};
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/* Finish off the partially created hw device. Attach our local
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callbacks. Wire up our port names etc */
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static hw_io_read_buffer_method tx3904irc_io_read_buffer;
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static hw_io_write_buffer_method tx3904irc_io_write_buffer;
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static hw_port_event_method tx3904irc_port_event;
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static void
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attach_tx3904irc_regs (struct hw *me,
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struct tx3904irc *controller)
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{
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unsigned_word attach_address;
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int attach_space;
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unsigned attach_size;
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reg_property_spec reg;
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if (hw_find_property (me, "reg") == NULL)
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hw_abort (me, "Missing \"reg\" property");
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if (!hw_find_reg_array_property (me, "reg", 0, ®))
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hw_abort (me, "\"reg\" property must contain one addr/size entry");
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hw_unit_address_to_attach_address (hw_parent (me),
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®.address,
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&attach_space,
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&attach_address,
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me);
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hw_unit_size_to_attach_size (hw_parent (me),
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®.size,
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&attach_size, me);
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hw_attach_address (hw_parent (me), 0,
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attach_space, attach_address, attach_size,
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me);
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controller->base_address = attach_address;
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}
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static void
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tx3904irc_finish (struct hw *me)
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{
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struct tx3904irc *controller;
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controller = HW_ZALLOC (me, struct tx3904irc);
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set_hw_data (me, controller);
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set_hw_io_read_buffer (me, tx3904irc_io_read_buffer);
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set_hw_io_write_buffer (me, tx3904irc_io_write_buffer);
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set_hw_ports (me, tx3904irc_ports);
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set_hw_port_event (me, tx3904irc_port_event);
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/* Attach ourself to our parent bus */
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attach_tx3904irc_regs (me, controller);
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/* Initialize to reset state */
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controller->isr = 0x0000ffff;
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controller->imr = 0;
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controller->ilr[0] =
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controller->ilr[1] =
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controller->ilr[2] =
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controller->ilr[3] = 0;
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}
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/* An event arrives on an interrupt port */
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static void
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tx3904irc_port_event (struct hw *me,
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int my_port,
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struct hw *source_dev,
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int source_port,
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int level)
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{
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struct tx3904irc *controller = hw_data (me);
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/* handle deactivated interrupt */
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if(level == 0)
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{
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HW_TRACE ((me, "interrupt cleared on port %d", my_port));
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hw_port_event(me, IP_PORT, 0);
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return;
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}
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switch (my_port)
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{
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case INT0_PORT:
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{
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int ip_number = 32; /* compute IP[5:0] */
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HW_TRACE ((me, "port-event INT[0]"));
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hw_port_event(me, IP_PORT, ip_number);
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break;
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}
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case INT1_PORT: case INT2_PORT: case INT3_PORT: case INT4_PORT:
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case INT5_PORT: case INT6_PORT: case INT7_PORT: case DMAC3_PORT:
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case DMAC2_PORT: case DMAC1_PORT: case DMAC0_PORT: case SIO0_PORT:
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case SIO1_PORT: case TMR0_PORT: case TMR1_PORT: case TMR2_PORT:
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{
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int source = my_port - INT1_PORT;
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HW_TRACE ((me, "interrupt asserted on port %d", source));
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ISR_SET(controller, source);
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if(ILR_GET(controller, source) > IMR_GET(controller))
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{
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int ip_number = 16 + source; /* compute IP[4:0] */
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HW_TRACE ((me, "interrupt level %d", ILR_GET(controller,source)));
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hw_port_event(me, IP_PORT, ip_number);
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}
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break;
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}
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case RESET_PORT:
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{
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HW_TRACE ((me, "reset"));
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controller->isr = 0x0000ffff;
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controller->imr = 0;
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controller->ilr[0] =
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controller->ilr[1] =
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controller->ilr[2] =
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controller->ilr[3] = 0;
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break;
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}
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case IP_PORT:
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hw_abort (me, "Event on output port %d", my_port);
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break;
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default:
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hw_abort (me, "Event on unknown port %d", my_port);
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break;
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}
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}
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/* generic read/write */
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static unsigned
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tx3904irc_io_read_buffer (struct hw *me,
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void *dest,
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int space,
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unsigned_word base,
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unsigned nr_bytes)
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{
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struct tx3904irc *controller = hw_data (me);
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unsigned byte;
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HW_TRACE ((me, "read 0x%08lx %d", (long) base, (int) nr_bytes));
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for (byte = 0; byte < nr_bytes; byte++)
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{
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address_word address = base + byte;
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int reg_number = (address - controller->base_address) / 4;
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int reg_offset = (address - controller->base_address) % 4;
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unsigned_4 register_value; /* in target byte order */
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/* fill in entire register_value word */
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switch (reg_number)
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{
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case ISR_REG: register_value = controller->isr; break;
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case IMR_REG: register_value = controller->imr; break;
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case ILR0_REG: register_value = controller->ilr[0]; break;
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case ILR1_REG: register_value = controller->ilr[1]; break;
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case ILR2_REG: register_value = controller->ilr[2]; break;
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case ILR3_REG: register_value = controller->ilr[3]; break;
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default: register_value = 0;
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}
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/* write requested byte out */
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register_value = H2T_4(register_value);
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memcpy ((char*) dest + byte, ((char*)& register_value)+reg_offset, 1);
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}
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return nr_bytes;
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}
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static unsigned
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tx3904irc_io_write_buffer (struct hw *me,
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const void *source,
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int space,
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unsigned_word base,
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unsigned nr_bytes)
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{
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struct tx3904irc *controller = hw_data (me);
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unsigned byte;
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HW_TRACE ((me, "write 0x%08lx %d", (long) base, (int) nr_bytes));
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for (byte = 0; byte < nr_bytes; byte++)
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{
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address_word address = base + byte;
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int reg_number = (address - controller->base_address) / 4;
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int reg_offset = (address - controller->base_address) % 4;
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unsigned_4* register_ptr;
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unsigned_4 register_value;
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/* fill in entire register_value word */
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switch (reg_number)
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{
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case ISR_REG: register_ptr = & controller->isr; break;
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case IMR_REG: register_ptr = & controller->imr; break;
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case ILR0_REG: register_ptr = & controller->ilr[0]; break;
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case ILR1_REG: register_ptr = & controller->ilr[1]; break;
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case ILR2_REG: register_ptr = & controller->ilr[2]; break;
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case ILR3_REG: register_ptr = & controller->ilr[3]; break;
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default: register_ptr = & register_value; /* used as a dummy */
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}
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/* HW_TRACE ((me, "reg %d pre: %08lx", reg_number, (long) *register_ptr)); */
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/* overwrite requested byte */
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register_value = H2T_4(* register_ptr);
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memcpy (((char*)®ister_value)+reg_offset, (const char*)source + byte, 1);
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* register_ptr = T2H_4(register_value);
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/* HW_TRACE ((me, "post: %08lx", (long) *register_ptr)); */
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}
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return nr_bytes;
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}
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const struct hw_descriptor dv_tx3904irc_descriptor[] = {
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{ "tx3904irc", tx3904irc_finish, },
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{ NULL },
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};
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