538 lines
13 KiB
C
538 lines
13 KiB
C
/* Altera Nios II disassemble routines
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Copyright (C) 2012-2015 Free Software Foundation, Inc.
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Contributed by Nigel Gray (ngray@altera.com).
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Contributed by Mentor Graphics, Inc.
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This file is part of the GNU opcodes library.
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This library is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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It is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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License for more details.
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You should have received a copy of the GNU General Public License
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along with this file; see the file COPYING. If not, write to the
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Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
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MA 02110-1301, USA. */
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#include "sysdep.h"
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#include "dis-asm.h"
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#include "opcode/nios2.h"
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#include "libiberty.h"
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#include <string.h>
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#include <assert.h>
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/* No symbol table is available when this code runs out in an embedded
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system as when it is used for disassembler support in a monitor. */
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#if !defined(EMBEDDED_ENV)
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#define SYMTAB_AVAILABLE 1
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#include "elf-bfd.h"
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#include "elf/nios2.h"
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#endif
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/* Default length of Nios II instruction in bytes. */
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#define INSNLEN 4
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/* Data structures used by the opcode hash table. */
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typedef struct _nios2_opcode_hash
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{
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const struct nios2_opcode *opcode;
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struct _nios2_opcode_hash *next;
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} nios2_opcode_hash;
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/* Hash table size. */
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#define OPCODE_HASH_SIZE (IW_R1_OP_UNSHIFTED_MASK + 1)
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/* Extract the opcode from an instruction word. */
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static unsigned int
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nios2_r1_extract_opcode (unsigned int x)
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{
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return GET_IW_R1_OP (x);
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}
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/* Pseudo-ops are stored in a different table than regular instructions. */
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typedef struct _nios2_disassembler_state
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{
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const struct nios2_opcode *opcodes;
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const int *num_opcodes;
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unsigned int (*extract_opcode) (unsigned int);
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nios2_opcode_hash *hash[OPCODE_HASH_SIZE];
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nios2_opcode_hash *ps_hash[OPCODE_HASH_SIZE];
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const struct nios2_opcode *nop;
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bfd_boolean init;
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} nios2_disassembler_state;
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static nios2_disassembler_state
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nios2_r1_disassembler_state = {
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nios2_r1_opcodes,
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&nios2_num_r1_opcodes,
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nios2_r1_extract_opcode,
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{},
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{},
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NULL,
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0
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};
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/* Function to initialize the opcode hash table. */
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static void
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nios2_init_opcode_hash (nios2_disassembler_state *state)
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{
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unsigned int i;
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register const struct nios2_opcode *op;
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for (i = 0; i < OPCODE_HASH_SIZE; i++)
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for (op = state->opcodes; op < &state->opcodes[*(state->num_opcodes)]; op++)
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{
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nios2_opcode_hash *new_hash;
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nios2_opcode_hash **bucket = NULL;
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if ((op->pinfo & NIOS2_INSN_MACRO) == NIOS2_INSN_MACRO)
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{
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if (i == state->extract_opcode (op->match)
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&& (op->pinfo & (NIOS2_INSN_MACRO_MOV | NIOS2_INSN_MACRO_MOVI)
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& 0x7fffffff))
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{
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bucket = &(state->ps_hash[i]);
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if (strcmp (op->name, "nop") == 0)
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state->nop = op;
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}
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}
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else if (i == state->extract_opcode (op->match))
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bucket = &(state->hash[i]);
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if (bucket)
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{
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new_hash =
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(nios2_opcode_hash *) malloc (sizeof (nios2_opcode_hash));
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if (new_hash == NULL)
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{
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fprintf (stderr,
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"error allocating memory...broken disassembler\n");
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abort ();
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}
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new_hash->opcode = op;
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new_hash->next = NULL;
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while (*bucket)
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bucket = &((*bucket)->next);
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*bucket = new_hash;
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}
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}
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state->init = 1;
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#ifdef DEBUG_HASHTABLE
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for (i = 0; i < OPCODE_HASH_SIZE; ++i)
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{
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nios2_opcode_hash *tmp_hash = state->hash[i];
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printf ("index: 0x%02X ops: ", i);
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while (tmp_hash != NULL)
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{
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printf ("%s ", tmp_hash->opcode->name);
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tmp_hash = tmp_hash->next;
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}
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printf ("\n");
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}
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for (i = 0; i < OPCODE_HASH_SIZE; ++i)
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{
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nios2_opcode_hash *tmp_hash = state->ps_hash[i];
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printf ("index: 0x%02X ops: ", i);
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while (tmp_hash != NULL)
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{
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printf ("%s ", tmp_hash->opcode->name);
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tmp_hash = tmp_hash->next;
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}
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printf ("\n");
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}
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#endif /* DEBUG_HASHTABLE */
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}
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/* Return a pointer to an nios2_opcode struct for a given instruction
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word OPCODE for bfd machine MACH, or NULL if there is an error. */
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const struct nios2_opcode *
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nios2_find_opcode_hash (unsigned long opcode,
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unsigned long mach ATTRIBUTE_UNUSED)
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{
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nios2_opcode_hash *entry;
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nios2_disassembler_state *state;
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state = &nios2_r1_disassembler_state;
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/* Build a hash table to shorten the search time. */
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if (!state->init)
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nios2_init_opcode_hash (state);
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/* Check for NOP first. Both NOP and MOV are macros that expand into
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an ADD instruction, and we always want to give priority to NOP. */
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if (state->nop->match == (opcode & state->nop->mask))
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return state->nop;
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/* First look in the pseudo-op hashtable. */
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for (entry = state->ps_hash[state->extract_opcode (opcode)];
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entry; entry = entry->next)
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if (entry->opcode->match == (opcode & entry->opcode->mask))
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return entry->opcode;
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/* Otherwise look in the main hashtable. */
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for (entry = state->hash[state->extract_opcode (opcode)];
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entry; entry = entry->next)
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if (entry->opcode->match == (opcode & entry->opcode->mask))
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return entry->opcode;
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return NULL;
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}
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/* There are 32 regular registers, 32 coprocessor registers,
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and 32 control registers. */
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#define NUMREGNAMES 32
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/* Return a pointer to the base of the coprocessor register name array. */
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static struct nios2_reg *
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nios2_coprocessor_regs (void)
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{
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static struct nios2_reg *cached = NULL;
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if (!cached)
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{
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int i;
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for (i = NUMREGNAMES; i < nios2_num_regs; i++)
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if (!strcmp (nios2_regs[i].name, "c0"))
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{
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cached = nios2_regs + i;
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break;
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}
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assert (cached);
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}
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return cached;
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}
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/* Return a pointer to the base of the control register name array. */
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static struct nios2_reg *
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nios2_control_regs (void)
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{
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static struct nios2_reg *cached = NULL;
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if (!cached)
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{
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int i;
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for (i = NUMREGNAMES; i < nios2_num_regs; i++)
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if (!strcmp (nios2_regs[i].name, "status"))
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{
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cached = nios2_regs + i;
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break;
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}
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assert (cached);
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}
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return cached;
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}
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/* Helper routine to report internal errors. */
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static void
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bad_opcode (const struct nios2_opcode *op)
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{
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fprintf (stderr, "Internal error: broken opcode descriptor for `%s %s'\n",
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op->name, op->args);
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abort ();
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}
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/* The function nios2_print_insn_arg uses the character pointed
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to by ARGPTR to determine how it print the next token or separator
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character in the arguments to an instruction. */
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static int
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nios2_print_insn_arg (const char *argptr,
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unsigned long opcode, bfd_vma address,
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disassemble_info *info,
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const struct nios2_opcode *op)
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{
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unsigned long i = 0;
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struct nios2_reg *reg_base;
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switch (*argptr)
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{
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case ',':
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case '(':
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case ')':
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(*info->fprintf_func) (info->stream, "%c", *argptr);
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break;
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case 'd':
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switch (op->format)
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{
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case iw_r_type:
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i = GET_IW_R_C (opcode);
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reg_base = nios2_regs;
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break;
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case iw_custom_type:
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i = GET_IW_CUSTOM_C (opcode);
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if (GET_IW_CUSTOM_READC (opcode) == 0)
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reg_base = nios2_coprocessor_regs ();
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else
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reg_base = nios2_regs;
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break;
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default:
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bad_opcode (op);
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}
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if (i < NUMREGNAMES)
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(*info->fprintf_func) (info->stream, "%s", reg_base[i].name);
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else
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(*info->fprintf_func) (info->stream, "unknown");
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break;
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case 's':
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switch (op->format)
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{
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case iw_r_type:
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i = GET_IW_R_A (opcode);
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reg_base = nios2_regs;
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break;
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case iw_i_type:
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i = GET_IW_I_A (opcode);
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reg_base = nios2_regs;
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break;
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case iw_custom_type:
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i = GET_IW_CUSTOM_A (opcode);
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if (GET_IW_CUSTOM_READA (opcode) == 0)
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reg_base = nios2_coprocessor_regs ();
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else
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reg_base = nios2_regs;
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break;
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default:
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bad_opcode (op);
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}
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if (i < NUMREGNAMES)
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(*info->fprintf_func) (info->stream, "%s", reg_base[i].name);
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else
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(*info->fprintf_func) (info->stream, "unknown");
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break;
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case 't':
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switch (op->format)
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{
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case iw_r_type:
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i = GET_IW_R_B (opcode);
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reg_base = nios2_regs;
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break;
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case iw_i_type:
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i = GET_IW_I_B (opcode);
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reg_base = nios2_regs;
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break;
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case iw_custom_type:
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i = GET_IW_CUSTOM_B (opcode);
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if (GET_IW_CUSTOM_READB (opcode) == 0)
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reg_base = nios2_coprocessor_regs ();
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else
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reg_base = nios2_regs;
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break;
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default:
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bad_opcode (op);
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}
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if (i < NUMREGNAMES)
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(*info->fprintf_func) (info->stream, "%s", reg_base[i].name);
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else
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(*info->fprintf_func) (info->stream, "unknown");
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break;
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case 'i':
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/* 16-bit signed immediate. */
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switch (op->format)
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{
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case iw_i_type:
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i = (signed) (GET_IW_I_IMM16 (opcode) << 16) >> 16;
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break;
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default:
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bad_opcode (op);
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}
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(*info->fprintf_func) (info->stream, "%ld", i);
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break;
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case 'u':
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/* 16-bit unsigned immediate. */
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switch (op->format)
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{
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case iw_i_type:
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i = GET_IW_I_IMM16 (opcode);
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break;
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default:
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bad_opcode (op);
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}
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(*info->fprintf_func) (info->stream, "%ld", i);
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break;
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case 'o':
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/* 16-bit signed immediate address offset. */
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switch (op->format)
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{
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case iw_i_type:
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i = (signed) (GET_IW_I_IMM16 (opcode) << 16) >> 16;
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break;
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default:
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bad_opcode (op);
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}
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address = address + 4 + i;
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(*info->print_address_func) (address, info);
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break;
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case 'j':
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/* 5-bit unsigned immediate. */
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switch (op->format)
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{
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case iw_r_type:
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i = GET_IW_R_IMM5 (opcode);
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break;
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default:
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bad_opcode (op);
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}
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(*info->fprintf_func) (info->stream, "%ld", i);
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break;
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case 'l':
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/* 8-bit unsigned immediate. */
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switch (op->format)
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{
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case iw_custom_type:
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i = GET_IW_CUSTOM_N (opcode);
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break;
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default:
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bad_opcode (op);
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}
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(*info->fprintf_func) (info->stream, "%lu", i);
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break;
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case 'm':
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/* 26-bit unsigned immediate. */
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switch (op->format)
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{
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case iw_j_type:
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i = GET_IW_J_IMM26 (opcode);
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break;
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default:
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bad_opcode (op);
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}
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/* This translates to an address because it's only used in call
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instructions. */
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address = (address & 0xf0000000) | (i << 2);
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(*info->print_address_func) (address, info);
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break;
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case 'c':
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/* Control register index. */
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switch (op->format)
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{
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case iw_r_type:
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i = GET_IW_R_IMM5 (opcode);
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break;
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default:
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bad_opcode (op);
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}
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reg_base = nios2_control_regs ();
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(*info->fprintf_func) (info->stream, "%s", reg_base[i].name);
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break;
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default:
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(*info->fprintf_func) (info->stream, "unknown");
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break;
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}
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return 0;
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}
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/* nios2_disassemble does all the work of disassembling a Nios II
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instruction opcode. */
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static int
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nios2_disassemble (bfd_vma address, unsigned long opcode,
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disassemble_info *info)
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{
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const struct nios2_opcode *op;
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info->bytes_per_line = INSNLEN;
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info->bytes_per_chunk = INSNLEN;
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info->display_endian = info->endian;
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info->insn_info_valid = 1;
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info->branch_delay_insns = 0;
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info->data_size = 0;
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info->insn_type = dis_nonbranch;
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info->target = 0;
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info->target2 = 0;
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/* Find the major opcode and use this to disassemble
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the instruction and its arguments. */
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op = nios2_find_opcode_hash (opcode, info->mach);
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if (op != NULL)
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{
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const char *argstr = op->args;
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(*info->fprintf_func) (info->stream, "%s", op->name);
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if (argstr != NULL && *argstr != '\0')
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{
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(*info->fprintf_func) (info->stream, "\t");
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while (*argstr != '\0')
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{
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nios2_print_insn_arg (argstr, opcode, address, info, op);
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++argstr;
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}
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}
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/* Tell the caller how far to advance the program counter. */
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info->bytes_per_chunk = op->size;
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return op->size;
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}
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else
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{
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/* Handle undefined instructions. */
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info->insn_type = dis_noninsn;
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(*info->fprintf_func) (info->stream, "0x%lx", opcode);
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return INSNLEN;
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}
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}
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/* print_insn_nios2 is the main disassemble function for Nios II.
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The function diassembler(abfd) (source in disassemble.c) returns a
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pointer to this either print_insn_big_nios2 or
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print_insn_little_nios2, which in turn call this function when the
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bfd machine type is Nios II. print_insn_nios2 reads the
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instruction word at the address given, and prints the disassembled
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instruction on the stream info->stream using info->fprintf_func. */
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static int
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print_insn_nios2 (bfd_vma address, disassemble_info *info,
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enum bfd_endian endianness)
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{
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bfd_byte buffer[INSNLEN];
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int status;
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status = (*info->read_memory_func) (address, buffer, INSNLEN, info);
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if (status == 0)
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{
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unsigned long insn;
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if (endianness == BFD_ENDIAN_BIG)
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insn = (unsigned long) bfd_getb32 (buffer);
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else
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insn = (unsigned long) bfd_getl32 (buffer);
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status = nios2_disassemble (address, insn, info);
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}
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else
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{
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(*info->memory_error_func) (status, address, info);
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status = -1;
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}
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return status;
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}
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/* These two functions are the main entry points, accessed from
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disassemble.c. */
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int
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print_insn_big_nios2 (bfd_vma address, disassemble_info *info)
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{
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|
return print_insn_nios2 (address, info, BFD_ENDIAN_BIG);
|
|
}
|
|
|
|
int
|
|
print_insn_little_nios2 (bfd_vma address, disassemble_info *info)
|
|
{
|
|
return print_insn_nios2 (address, info, BFD_ENDIAN_LITTLE);
|
|
}
|