61baf725ec
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369 lines
8.2 KiB
C
369 lines
8.2 KiB
C
// -*- C -*-
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// Simulator definition for the MIPS16e instructions.
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// Copyright (C) 2005-2017 Free Software Foundation, Inc.
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// Contributed by Nigel Stephens (nigel@mips.com) and
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// David Ung (davidu@mips.com) of MIPS Technologies.
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//
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// This file is part of GDB, the GNU debugger.
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//
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// This program is free software; you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation; either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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11101,3.RX,100,10001:RR:16::SEB
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"seb r<TRX>"
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*mips16e:
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{
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TRACE_ALU_INPUT1 (GPR[TRX]);
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GPR[TRX] = EXTEND8 (GPR[TRX]);
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TRACE_ALU_RESULT (GPR[TRX]);
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}
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11101,3.RX,101,10001:RR:16::SEH
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"seh r<TRX>"
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*mips16e:
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{
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TRACE_ALU_INPUT1 (GPR[TRX]);
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GPR[TRX] = EXTEND16 (GPR[TRX]);
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TRACE_ALU_RESULT (GPR[TRX]);
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}
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11101,3.RX,110,10001:RR:16::SEW
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"sew r<TRX>"
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*mips16e:
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{
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check_u64 (SD_, instruction_0);
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TRACE_ALU_INPUT1 (GPR[TRX]);
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GPR[TRX] = EXTEND32 (GPR[TRX]);
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TRACE_ALU_RESULT (GPR[TRX]);
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}
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11101,3.RX,000,10001:RR:16::ZEB
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"zeb r<TRX>"
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*mips16e:
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{
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TRACE_ALU_INPUT1 (GPR[TRX]);
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GPR[TRX] = (unsigned_word)(unsigned8)(GPR[TRX]);
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TRACE_ALU_RESULT (GPR[TRX]);
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}
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11101,3.RX,001,10001:RR:16::ZEH
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"zeh r<TRX>"
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*mips16e:
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{
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TRACE_ALU_INPUT1 (GPR[TRX]);
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GPR[TRX] = (unsigned_word)(unsigned16)(GPR[TRX]);
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TRACE_ALU_RESULT (GPR[TRX]);
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}
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11101,3.RX,010,10001:RR:16::ZEW
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"zew r<TRX>"
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*mips16e:
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{
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check_u64 (SD_, instruction_0);
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TRACE_ALU_INPUT1 (GPR[TRX]);
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GPR[TRX] = (unsigned_word)(unsigned32)(GPR[TRX]);
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TRACE_ALU_RESULT (GPR[TRX]);
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}
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11101,3.RX,100,00000:RR:16::JRC
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"jrc r<TRX>"
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*mips16e:
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{
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NIA = GPR[TRX];
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}
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11101,000,101,00000:RR:16::JRCRA
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"jrc ra"
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*mips16e:
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{
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NIA = RA;
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}
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11101,3.RX,110,00000:RR:16::JALRC
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"jalrc r<TRX>"
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*mips16e:
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{
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RA = NIA;
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NIA = GPR[TRX];
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}
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// format routines for save/restore
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:%s::::RAS:int ras
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*mips16e
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{
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static char buf[10];
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buf[0] = '\0';
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if (ras & 4)
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strcat (buf,"ra,");
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if (ras & 2)
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strcat (buf,"s0,");
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if (ras & 1)
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strcat (buf,"s1,");
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return (buf);
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}
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:%s::::XSREGS:int xsregs
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*mips16e
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{
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if (xsregs > 6)
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return "s2,s3,s4,s5,s6,s7,s8,";
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if (xsregs > 5)
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return "s2,s3,s4,s5,s6,s7,";
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if (xsregs > 4)
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return "s2,s3,s4,s5,s6,";
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if (xsregs > 3)
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return "s2,s3,s4,s5,";
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if (xsregs > 2)
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return "s2,s3,s4,";
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if (xsregs > 1)
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return "s2,s3,";
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if (xsregs > 0)
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return "s2,";
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return "";
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}
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:%s::::AREGS:int aregs
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*mips16e
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{
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// Fixme: how is the arg/static distinction made by the assembler?
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static const char * const aregstr[16] = {
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"",
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"A3,",
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"A2,A3,",
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"A1,A2,A3,",
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"A0,A1,A2,A3,",
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"a0,",
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"a0,A3,",
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"a0,A2,A3,",
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"a0,A1,A2,A3,",
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"a0,a1,",
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"a0,a1,A3,",
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"a0,a1,A2,A3,",
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"a0,a1,a2,",
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"a0,a1,a2,A3,",
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"?,"
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};
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return aregstr[aregs];
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}
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:compute:::int:SFRAME:FS:((FS == 0) ? 128 \: (FS << 3))
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:compute:::int:BFRAME:FSHI,FSLO:(((FSHI << 4) | FSLO) << 3)
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:function:::void:do_save:int xsregs, int aregs, int ras0s1, int framesize
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{
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unsigned_word temp;
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int args, astatic;
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temp = GPR[29];
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/* writes are in the same order as the hardware description... */
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switch (aregs) {
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case 0: case 1: case 2: case 3: case 11:
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args = 0;
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break;
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case 4: case 5: case 6: case 7:
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args = 1;
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break;
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case 8: case 9: case 10:
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args = 2;
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break;
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case 12: case 13:
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args = 3;
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break;
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case 14:
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args = 4;
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break;
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default:
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sim_engine_abort (SD, CPU, CIA, "save: aregs=%d causes unpredictable results\n", aregs);
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}
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if (args > 0) {
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do_store (SD_, AccessLength_WORD, temp, 0, GPR[4]);
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if (args > 1) {
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do_store (SD_,AccessLength_WORD, temp, 4 , GPR[5]);
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if (args > 2) {
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do_store (SD_,AccessLength_WORD, temp, 8 , GPR[6]);
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if (args > 3) {
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do_store (SD_,AccessLength_WORD, temp, 12, GPR[7]);
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}
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}
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}
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}
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if (ras0s1 & 4)
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do_store (SD_,AccessLength_WORD, temp -= 4, 0, GPR[31]);
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switch (xsregs) {
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case 7:
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do_store (SD_,AccessLength_WORD, temp -= 4, 0, GPR[30]);
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case 6:
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do_store (SD_,AccessLength_WORD, temp -= 4, 0, GPR[23]);
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case 5:
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do_store (SD_,AccessLength_WORD, temp -= 4, 0, GPR[22]);
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case 4:
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do_store (SD_,AccessLength_WORD, temp -= 4, 0, GPR[21]);
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case 3:
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do_store (SD_,AccessLength_WORD, temp -= 4, 0, GPR[20]);
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case 2:
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do_store (SD_,AccessLength_WORD, temp -= 4, 0, GPR[19]);
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case 1:
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do_store (SD_,AccessLength_WORD, temp -= 4, 0, GPR[18]);
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}
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if (ras0s1 & 1)
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do_store (SD_,AccessLength_WORD, temp -= 4, 0, GPR[17]);
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if (ras0s1 & 2)
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do_store (SD_,AccessLength_WORD, temp -= 4, 0, GPR[16]);
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switch (aregs) {
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case 0: case 4: case 8: case 12: case 14:
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astatic = 0;
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break;
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case 1: case 5: case 9: case 13:
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astatic = 1;
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break;
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case 2: case 6: case 10:
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astatic = 2;
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break;
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case 3: case 7:
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astatic = 3;
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break;
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case 11:
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astatic = 4;
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break;
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default:
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sim_engine_abort (SD, CPU, CIA, "save: aregs=%d causes unpredictable results\n", aregs);
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}
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if (astatic > 0) {
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do_store (SD_, AccessLength_WORD, temp -= 4, 0, GPR[7]);
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if (astatic > 1) {
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do_store (SD_, AccessLength_WORD, temp -= 4, 0, GPR[6]);
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if (astatic > 2) {
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do_store (SD_, AccessLength_WORD, temp -= 4, 0, GPR[5]);
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if (astatic > 3) {
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do_store (SD_, AccessLength_WORD, temp -= 4, 0, GPR[4]);
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}
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}
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}
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}
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GPR[29] -= framesize;
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}
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01100,100,1,3.RAS,4.FS:I8:16::SAVE
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"save %s<RAS>,<SFRAME>"
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*mips16e
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{
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do_save (SD_, 0, 0, RAS, SFRAME);
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}
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11110,3.XSREGS,4.FSHI,4.AREGS + 01100,100,1,3.RAS,4.FSLO:EXT-I8:16::SAVE
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"save %s<RAS>%s<XSREGS>%s<AREGS><BFRAME>"
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*mips16e
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{
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do_save (SD_, XSREGS, AREGS, RAS, BFRAME);
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}
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:function:::void:do_restore:int xsregs, int aregs, int ras0s1, int framesize
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*mips16e
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{
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unsigned_word temp, temp2;
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int astatic;
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temp = GPR[29] + framesize;
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temp2 = temp;
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/* reads are in the same order as the hardware description... */
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if (ras0s1 & 4)
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GPR[31] = EXTEND32 (do_load(SD_, AccessLength_WORD, temp -= 4, 0));
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switch (xsregs) {
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case 7:
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GPR[30] = EXTEND32 (do_load (SD_,AccessLength_WORD, temp -= 4, 0));
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case 6:
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GPR[23] = EXTEND32 (do_load (SD_,AccessLength_WORD, temp -= 4, 0));
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case 5:
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GPR[22] = EXTEND32 (do_load (SD_,AccessLength_WORD, temp -= 4, 0));
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case 4:
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GPR[21] = EXTEND32 (do_load (SD_,AccessLength_WORD, temp -= 4, 0));
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case 3:
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GPR[20] = EXTEND32 (do_load (SD_,AccessLength_WORD, temp -= 4, 0));
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case 2:
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GPR[19] = EXTEND32 (do_load (SD_,AccessLength_WORD, temp -= 4, 0));
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case 1:
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GPR[18] = EXTEND32 (do_load (SD_,AccessLength_WORD, temp -= 4, 0));
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}
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if (ras0s1 & 1)
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GPR[17] = EXTEND32 (do_load (SD_,AccessLength_WORD, temp -= 4, 0));
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if (ras0s1 & 2)
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GPR[16] = EXTEND32 (do_load (SD_,AccessLength_WORD, temp -= 4, 0));
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switch (aregs) {
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case 0: case 4: case 8: case 12: case 14:
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astatic = 0;
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break;
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case 1: case 5: case 9: case 13:
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astatic = 1;
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break;
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case 2: case 6: case 10:
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astatic = 2;
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break;
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case 3: case 7:
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astatic = 3;
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break;
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case 11:
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astatic = 4;
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break;
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default:
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sim_engine_abort (SD, CPU, CIA, "save: aregs=%d causes unpredictable results\n", aregs);
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}
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if (astatic > 0) {
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GPR[7] = EXTEND32 (do_load (SD_,AccessLength_WORD, temp -= 4, 0));
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if (astatic > 1) {
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GPR[6] = EXTEND32 (do_load (SD_,AccessLength_WORD, temp -= 4, 0));
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if (astatic > 2) {
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GPR[5] = EXTEND32 (do_load (SD_,AccessLength_WORD, temp -= 4, 0));
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if (astatic > 3) {
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GPR[4] = EXTEND32 (do_load (SD_,AccessLength_WORD, temp -= 4, 0));
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}
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}
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}
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}
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GPR[29] = temp2;
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}
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01100,100,0,3.RAS,4.FS:I8:16::RESTORE
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"restore %s<RAS>,<SFRAME>"
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*mips16e
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{
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do_restore (SD_,0,0,RAS,SFRAME);
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}
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11110,3.XSREGS,4.FSHI,4.AREGS + 01100,100,0,3.RAS,4.FSLO:EXT-I8:16::RESTORE
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"restore %s<RAS>%s<XSREGS>%s<AREGS><BFRAME>"
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*mips16e
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{
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do_restore (SD_,XSREGS,AREGS,RAS,BFRAME);
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}
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