471b9d1507
Implement MIPS target support for passing options to the disassembler,
complementing commit 65b48a8140
("GDB: Add support for the new
set/show disassembler-options commands.").
This includes options that expect an argument, so adjust the generic
code and data structures used so as to handle such options. So as to
give backends syntax flexibility no specific delimiter has been defined
to separate options from their respective arguments, so it has to be
included as the last character of the option name. Completion code
however has not been adjusted and consequently option arguments cannot
be completed at this time.
Also the MIPS target has non-empty defaults for the options, so that ABI
names for the general-purpose registers respect our `set mips abi ...'
setting rather than always being determined from the ELF headers of the
binary file selected. Handle these defaults as implicit options, never
shown to the user and always prepended to the user-specified options, so
that the latters can override the defaults.
The resulting output for the MIPS target is as follows:
(gdb) show disassembler-options
The current disassembler options are ''
The following disassembler options are supported for use with the
'set disassembler-options <option>[,<option>...]' command:
no-aliases Use canonical instruction forms.
msa Recognize MSA instructions.
virt Recognize the virtualization ASE instructions.
xpa Recognize the eXtended Physical Address (XPA) ASE
instructions.
ginv Recognize the Global INValidate (GINV) ASE instructions.
gpr-names=ABI Print GPR names according to specified ABI.
Default: based on binary being disassembled.
fpr-names=ABI Print FPR names according to specified ABI.
Default: numeric.
cp0-names=ARCH Print CP0 register names according to specified architecture.
Default: based on binary being disassembled.
hwr-names=ARCH Print HWR names according to specified architecture.
Default: based on binary being disassembled.
reg-names=ABI Print GPR and FPR names according to specified ABI.
reg-names=ARCH Print CP0 register and HWR names according to specified
architecture.
For the options above, the following values are supported for "ABI":
numeric 32 n32 64
For the options above, the following values are supported for "ARCH":
numeric r3000 r3900 r4000 r4010 vr4100 vr4111 vr4120 r4300 r4400 r4600
r4650 r5000 vr5400 vr5500 r5900 r6000 rm7000 rm9000 r8000 r10000 r12000
r14000 r16000 mips5 mips32 mips32r2 mips32r3 mips32r5 mips32r6 mips64
mips64r2 mips64r3 mips64r5 mips64r6 interaptiv-mr2 sb1 loongson2e
loongson2f loongson3a octeon octeon+ octeon2 octeon3 xlr xlp
(gdb)
which corresponds to what `objdump --help' used to print for the MIPS
target, with minor formatting changes, most notably option argument
lists being wrapped, but also the amount of white space separating
options from the respective descriptions. The relevant part the new
code is now also used by `objdump --help', which means these formatting
changes apply to both outputs, except for argument list wrapping, which
is GDB-specific.
This also adds a separating new line between the heading and option
lists where descriptions are provided, hence:
(gdb) set architecture s390:31-bit
(gdb) show disassembler-options
The current disassembler options are ''
The following disassembler options are supported for use with the
'set disassembler-options <option>[,<option>...]' command:
esa Disassemble in ESA architecture mode
zarch Disassemble in z/Architecture mode
insnlength Print unknown instructions according to length from first two bits
(gdb)
but:
(gdb) set architecture powerpc:common
(gdb) show disassembler-options
The current disassembler options are ''
The following disassembler options are supported for use with the
'set disassembler-options <option>[,<option>...]' command:
403, 405, 440, 464, 476, 601, 603, 604, 620, 7400, 7410, 7450, 7455, 750cl,
821, 850, 860, a2, altivec, any, booke, booke32, cell, com, e200z4, e300,
e500, e500mc, e500mc64, e5500, e6500, e500x2, efs, efs2, power4, power5,
power6, power7, power8, power9, ppc, ppc32, 32, ppc64, 64, ppc64bridge,
ppcps, pwr, pwr2, pwr4, pwr5, pwr5x, pwr6, pwr7, pwr8, pwr9, pwrx, raw, spe,
spe2, titan, vle, vsx
(gdb)
Existing affected target backends have been adjusted accordingly.
This has been verified manually with:
(gdb) set architecture arm
(gdb) set architecture powerpc:common
(gdb) set architecture s390:31-bit
to cause no issues with the `show disassembler-options' and `set
disassembler-options' commands. A test case for the MIPS target has
also been provided, covering the default settings with ABI overrides as
well as disassembler option overrides.
2018-07-02 Maciej W. Rozycki <macro@mips.com>
Simon Marchi <simon.marchi@polymtl.ca>
include/
PR tdep/8282
* dis-asm.h (disasm_option_arg_t): New typedef.
(disasm_options_and_args_t): Likewise.
(disasm_options_t): Add `arg' member, document members.
(disassembler_options_mips): New prototype.
(disassembler_options_arm, disassembler_options_powerpc)
(disassembler_options_s390): Update prototypes.
opcodes/
PR tdep/8282
* mips-dis.c (mips_option_arg_t): New enumeration.
(mips_options): New variable.
(disassembler_options_mips): New function.
(print_mips_disassembler_options): Reimplement in terms of
`disassembler_options_mips'.
* arm-dis.c (disassembler_options_arm): Adapt to using the
`disasm_options_and_args_t' structure.
* ppc-dis.c (disassembler_options_powerpc): Likewise.
* s390-dis.c (disassembler_options_s390): Likewise.
gdb/
PR tdep/8282
* disasm.h (gdb_disassembler): Add
`m_disassembler_options_holder'. member
* disasm.c (get_all_disassembler_options): New function.
(gdb_disassembler::gdb_disassembler): Use it.
(gdb_buffered_insn_length_init_dis): Likewise.
(gdb_buffered_insn_length): Adjust accordingly.
(set_disassembler_options): Handle options with arguments.
(show_disassembler_options_sfunc): Likewise. Add a leading new
line if showing options with descriptions.
(disassembler_options_completer): Adapt to using the
`disasm_options_and_args_t' structure.
* mips-tdep.c (mips_disassembler_options): New variable.
(mips_disassembler_options_o32): Likewise.
(mips_disassembler_options_n32): Likewise.
(mips_disassembler_options_n64): Likewise.
(gdb_print_insn_mips): Don't set `disassembler_options'.
(gdb_print_insn_mips_n32, gdb_print_insn_mips_n64): Remove
functions.
(mips_gdbarch_init): Always set `gdbarch_print_insn' to
`gdb_print_insn_mips'. Set `gdbarch_disassembler_options',
`gdbarch_disassembler_options_implicit' and
`gdbarch_valid_disassembler_options'.
* arm-tdep.c (_initialize_arm_tdep): Adapt to using the
`disasm_options_and_args_t' structure.
* gdbarch.sh (disassembler_options_implicit): New `gdbarch'
method.
(valid_disassembler_options): Switch from `disasm_options_t' to
the `disasm_options_and_args_t' structure.
* NEWS: Document `set disassembler-options' support for the MIPS
target.
* gdbarch.h: Regenerate.
* gdbarch.c: Regenerate.
gdb/doc/
PR tdep/8282
* gdb.texinfo (Source and Machine Code): Document `set
disassembler-options' support for the MIPS target.
gdb/testsuite/
PR tdep/8282
* gdb.arch/mips-disassembler-options.exp: New test.
* gdb.arch/mips-disassembler-options.s: New test source.
433 lines
12 KiB
C
433 lines
12 KiB
C
/* s390-dis.c -- Disassemble S390 instructions
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Copyright (C) 2000-2018 Free Software Foundation, Inc.
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Contributed by Martin Schwidefsky (schwidefsky@de.ibm.com).
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This file is part of the GNU opcodes library.
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This library is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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It is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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License for more details.
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You should have received a copy of the GNU General Public License
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along with this file; see the file COPYING. If not, write to the
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Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
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MA 02110-1301, USA. */
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#include "sysdep.h"
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#include <stdio.h>
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#include "ansidecl.h"
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#include "disassemble.h"
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#include "opintl.h"
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#include "opcode/s390.h"
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#include "libiberty.h"
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static int opc_index[256];
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static int current_arch_mask = 0;
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static int option_use_insn_len_bits_p = 0;
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typedef struct
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{
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const char *name;
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const char *description;
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} s390_options_t;
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static const s390_options_t options[] =
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{
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{ "esa" , N_("Disassemble in ESA architecture mode") },
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{ "zarch", N_("Disassemble in z/Architecture mode") },
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{ "insnlength", N_("Print unknown instructions according to "
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"length from first two bits") }
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};
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/* Set up index table for first opcode byte. */
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void
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disassemble_init_s390 (struct disassemble_info *info)
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{
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int i;
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const char *p;
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memset (opc_index, 0, sizeof (opc_index));
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/* Reverse order, such that each opc_index ends up pointing to the
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first matching entry instead of the last. */
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for (i = s390_num_opcodes; i--; )
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opc_index[s390_opcodes[i].opcode[0]] = i;
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current_arch_mask = 1 << S390_OPCODE_ZARCH;
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option_use_insn_len_bits_p = 0;
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for (p = info->disassembler_options; p != NULL; )
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{
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if (CONST_STRNEQ (p, "esa"))
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current_arch_mask = 1 << S390_OPCODE_ESA;
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else if (CONST_STRNEQ (p, "zarch"))
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current_arch_mask = 1 << S390_OPCODE_ZARCH;
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else if (CONST_STRNEQ (p, "insnlength"))
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option_use_insn_len_bits_p = 1;
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else
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/* xgettext:c-format */
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opcodes_error_handler (_("unknown S/390 disassembler option: %s"), p);
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p = strchr (p, ',');
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if (p != NULL)
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p++;
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}
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}
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/* Derive the length of an instruction from its first byte. */
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static inline int
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s390_insn_length (const bfd_byte *buffer)
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{
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/* 00xxxxxx -> 2, 01xxxxxx/10xxxxxx -> 4, 11xxxxxx -> 6. */
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return ((buffer[0] >> 6) + 3) & ~1U;
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}
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/* Match the instruction in BUFFER against the given OPCODE, excluding
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the first byte. */
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static inline int
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s390_insn_matches_opcode (const bfd_byte *buffer,
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const struct s390_opcode *opcode)
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{
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return (buffer[1] & opcode->mask[1]) == opcode->opcode[1]
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&& (buffer[2] & opcode->mask[2]) == opcode->opcode[2]
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&& (buffer[3] & opcode->mask[3]) == opcode->opcode[3]
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&& (buffer[4] & opcode->mask[4]) == opcode->opcode[4]
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&& (buffer[5] & opcode->mask[5]) == opcode->opcode[5];
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}
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union operand_value
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{
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int i;
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unsigned int u;
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};
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/* Extracts an operand value from an instruction. */
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/* We do not perform the shift operation for larl-type address
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operands here since that would lead to an overflow of the 32 bit
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integer value. Instead the shift operation is done when printing
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the operand. */
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static inline union operand_value
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s390_extract_operand (const bfd_byte *insn,
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const struct s390_operand *operand)
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{
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union operand_value ret;
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unsigned int val;
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int bits;
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const bfd_byte *orig_insn = insn;
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/* Extract fragments of the operand byte for byte. */
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insn += operand->shift / 8;
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bits = (operand->shift & 7) + operand->bits;
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val = 0;
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do
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{
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val <<= 8;
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val |= (unsigned int) *insn++;
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bits -= 8;
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}
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while (bits > 0);
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val >>= -bits;
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val &= ((1U << (operand->bits - 1)) << 1) - 1;
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/* Check for special long displacement case. */
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if (operand->bits == 20 && operand->shift == 20)
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val = (val & 0xff) << 12 | (val & 0xfff00) >> 8;
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/* Sign extend value if the operand is signed or pc relative. Avoid
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integer overflows. */
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if (operand->flags & (S390_OPERAND_SIGNED | S390_OPERAND_PCREL))
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{
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unsigned int m = 1U << (operand->bits - 1);
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if (val >= m)
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ret.i = (int) (val - m) - 1 - (int) (m - 1U);
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else
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ret.i = (int) val;
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}
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else if (operand->flags & S390_OPERAND_LENGTH)
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/* Length x in an instruction has real length x + 1. */
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ret.u = val + 1;
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else if (operand->flags & S390_OPERAND_VR)
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{
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/* Extract the extra bits for a vector register operand stored
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in the RXB field. */
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unsigned vr = operand->shift == 32 ? 3
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: (unsigned) operand->shift / 4 - 2;
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ret.u = val | ((orig_insn[4] & (1 << (3 - vr))) << (vr + 1));
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}
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else
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ret.u = val;
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return ret;
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}
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/* Print the S390 instruction in BUFFER, assuming that it matches the
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given OPCODE. */
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static void
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s390_print_insn_with_opcode (bfd_vma memaddr,
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struct disassemble_info *info,
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const bfd_byte *buffer,
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const struct s390_opcode *opcode)
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{
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const unsigned char *opindex;
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char separator;
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/* Mnemonic. */
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info->fprintf_func (info->stream, "%s", opcode->name);
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/* Operands. */
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separator = '\t';
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for (opindex = opcode->operands; *opindex != 0; opindex++)
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{
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const struct s390_operand *operand = s390_operands + *opindex;
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union operand_value val = s390_extract_operand (buffer, operand);
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unsigned long flags = operand->flags;
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if ((flags & S390_OPERAND_INDEX) && val.u == 0)
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continue;
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if ((flags & S390_OPERAND_BASE) &&
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val.u == 0 && separator == '(')
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{
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separator = ',';
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continue;
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}
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/* For instructions with a last optional operand don't print it
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if zero. */
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if ((opcode->flags & (S390_INSTR_FLAG_OPTPARM | S390_INSTR_FLAG_OPTPARM2))
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&& val.u == 0
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&& opindex[1] == 0)
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break;
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if ((opcode->flags & S390_INSTR_FLAG_OPTPARM2)
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&& val.u == 0 && opindex[1] != 0 && opindex[2] == 0)
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{
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union operand_value next_op_val =
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s390_extract_operand (buffer, s390_operands + opindex[1]);
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if (next_op_val.u == 0)
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break;
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}
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if (flags & S390_OPERAND_GPR)
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info->fprintf_func (info->stream, "%c%%r%u", separator, val.u);
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else if (flags & S390_OPERAND_FPR)
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info->fprintf_func (info->stream, "%c%%f%u", separator, val.u);
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else if (flags & S390_OPERAND_VR)
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info->fprintf_func (info->stream, "%c%%v%i", separator, val.u);
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else if (flags & S390_OPERAND_AR)
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info->fprintf_func (info->stream, "%c%%a%u", separator, val.u);
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else if (flags & S390_OPERAND_CR)
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info->fprintf_func (info->stream, "%c%%c%u", separator, val.u);
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else if (flags & S390_OPERAND_PCREL)
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{
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info->fprintf_func (info->stream, "%c", separator);
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info->print_address_func (memaddr + val.i + val.i, info);
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}
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else if (flags & S390_OPERAND_SIGNED)
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info->fprintf_func (info->stream, "%c%i", separator, val.i);
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else
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{
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if (flags & S390_OPERAND_OR1)
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val.u &= ~1;
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if (flags & S390_OPERAND_OR2)
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val.u &= ~2;
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if (flags & S390_OPERAND_OR8)
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val.u &= ~8;
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if ((opcode->flags & S390_INSTR_FLAG_OPTPARM)
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&& val.u == 0
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&& opindex[1] == 0)
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break;
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info->fprintf_func (info->stream, "%c%u", separator, val.u);
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}
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if (flags & S390_OPERAND_DISP)
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separator = '(';
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else if (flags & S390_OPERAND_BASE)
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{
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info->fprintf_func (info->stream, ")");
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separator = ',';
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}
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else
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separator = ',';
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}
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}
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/* Check whether opcode A's mask is more specific than that of B. */
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static int
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opcode_mask_more_specific (const struct s390_opcode *a,
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const struct s390_opcode *b)
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{
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return (((int) a->mask[0] + a->mask[1] + a->mask[2]
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+ a->mask[3] + a->mask[4] + a->mask[5])
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> ((int) b->mask[0] + b->mask[1] + b->mask[2]
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+ b->mask[3] + b->mask[4] + b->mask[5]));
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}
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/* Print a S390 instruction. */
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int
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print_insn_s390 (bfd_vma memaddr, struct disassemble_info *info)
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{
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bfd_byte buffer[6];
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const struct s390_opcode *opcode = NULL;
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unsigned int value;
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int status, opsize, bufsize, bytes_to_dump, i;
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/* The output looks better if we put 6 bytes on a line. */
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info->bytes_per_line = 6;
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/* Every S390 instruction is max 6 bytes long. */
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memset (buffer, 0, 6);
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status = info->read_memory_func (memaddr, buffer, 6, info);
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if (status != 0)
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{
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for (bufsize = 0; bufsize < 6; bufsize++)
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if (info->read_memory_func (memaddr, buffer, bufsize + 1, info) != 0)
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break;
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if (bufsize <= 0)
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{
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info->memory_error_func (status, memaddr, info);
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return -1;
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}
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opsize = s390_insn_length (buffer);
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status = opsize > bufsize;
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}
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else
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{
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bufsize = 6;
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opsize = s390_insn_length (buffer);
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}
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if (status == 0)
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{
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const struct s390_opcode *op;
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/* Find the "best match" in the opcode table. */
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for (op = s390_opcodes + opc_index[buffer[0]];
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op != s390_opcodes + s390_num_opcodes
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&& op->opcode[0] == buffer[0];
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op++)
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{
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if ((op->modes & current_arch_mask)
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&& s390_insn_matches_opcode (buffer, op)
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&& (opcode == NULL
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|| opcode_mask_more_specific (op, opcode)))
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opcode = op;
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}
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if (opcode != NULL)
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{
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/* The instruction is valid. Print it and return its size. */
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s390_print_insn_with_opcode (memaddr, info, buffer, opcode);
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return opsize;
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}
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}
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/* For code sections it makes sense to skip unknown instructions
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according to their length bits. */
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if (status == 0
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&& option_use_insn_len_bits_p
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&& info->section != NULL
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&& (info->section->flags & SEC_CODE))
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bytes_to_dump = opsize;
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else
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/* By default unknown instructions are printed as .long's/.short'
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depending on how many bytes are available. */
|
|
bytes_to_dump = bufsize >= 4 ? 4 : bufsize;
|
|
|
|
if (bytes_to_dump == 0)
|
|
return 0;
|
|
|
|
/* Fall back to hex print. */
|
|
switch (bytes_to_dump)
|
|
{
|
|
case 4:
|
|
value = (unsigned int) buffer[0];
|
|
value = (value << 8) + (unsigned int) buffer[1];
|
|
value = (value << 8) + (unsigned int) buffer[2];
|
|
value = (value << 8) + (unsigned int) buffer[3];
|
|
info->fprintf_func (info->stream, ".long\t0x%08x", value);
|
|
return 4;
|
|
case 2:
|
|
value = (unsigned int) buffer[0];
|
|
value = (value << 8) + (unsigned int) buffer[1];
|
|
info->fprintf_func (info->stream, ".short\t0x%04x", value);
|
|
return 2;
|
|
default:
|
|
info->fprintf_func (info->stream, ".byte\t0x%02x",
|
|
(unsigned int) buffer[0]);
|
|
for (i = 1; i < bytes_to_dump; i++)
|
|
info->fprintf_func (info->stream, ",0x%02x",
|
|
(unsigned int) buffer[i]);
|
|
return bytes_to_dump;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
const disasm_options_and_args_t *
|
|
disassembler_options_s390 (void)
|
|
{
|
|
static disasm_options_and_args_t *opts_and_args;
|
|
|
|
if (opts_and_args == NULL)
|
|
{
|
|
size_t i, num_options = ARRAY_SIZE (options);
|
|
disasm_options_t *opts;
|
|
|
|
opts_and_args = XNEW (disasm_options_and_args_t);
|
|
opts_and_args->args = NULL;
|
|
|
|
opts = &opts_and_args->options;
|
|
opts->name = XNEWVEC (const char *, num_options + 1);
|
|
opts->description = XNEWVEC (const char *, num_options + 1);
|
|
opts->arg = NULL;
|
|
for (i = 0; i < num_options; i++)
|
|
{
|
|
opts->name[i] = options[i].name;
|
|
opts->description[i] = _(options[i].description);
|
|
}
|
|
/* The array we return must be NULL terminated. */
|
|
opts->name[i] = NULL;
|
|
opts->description[i] = NULL;
|
|
}
|
|
|
|
return opts_and_args;
|
|
}
|
|
|
|
void
|
|
print_s390_disassembler_options (FILE *stream)
|
|
{
|
|
unsigned int i, max_len = 0;
|
|
fprintf (stream, _("\n\
|
|
The following S/390 specific disassembler options are supported for use\n\
|
|
with the -M switch (multiple options should be separated by commas):\n"));
|
|
|
|
for (i = 0; i < ARRAY_SIZE (options); i++)
|
|
{
|
|
unsigned int len = strlen (options[i].name);
|
|
if (max_len < len)
|
|
max_len = len;
|
|
}
|
|
|
|
for (i = 0, max_len++; i < ARRAY_SIZE (options); i++)
|
|
fprintf (stream, " %s%*c %s\n",
|
|
options[i].name,
|
|
(int)(max_len - strlen (options[i].name)), ' ',
|
|
_(options[i].description));
|
|
}
|