8699fc3e88
This commit introduces the nps400 machine type as a variant of arc. There's a new flag in the assembler to select this machine type. All other changes are just adding handling of the new machine type into the relevant places. The nps400 is an arc700 variant with some vendor specific instructions added into the instruction set. This commit does not add any of the new instructions, this is just laying the groundwork for future commits. However, in preparation for these new instructions a new opcode define for nps400 has been added to include/opcode/arc.h, this new opcode define is used in the assembler and disassembler along with the existing define for arc700 such that when assembling and disassembling for nps400 the user will have access to all arc700 instructions and all the nps400 vendor extension instructions. bfd/ChangeLog: * archures.c (bfd_mach_arc_nps400): Define. * bfd-in2.h: Regenerate. * cpu-arc.c (arch_info_struct): New entry for nps400, renumber some existing entries to make space. * elf32-arc.c (arc_elf_object_p): Add nps400 case. (arc_elf_final_write_processing): Likewise. binutils/ChangeLog: * readelf.c (decode_ARC_machine_flags): Handle nps400. gas/ChangeLog: * config/tc-arc.c (cpu_types): Add nps400 entry. (check_zol): Handle nps400. include/ChangeLog: * elf/arc.h (E_ARC_MACH_NPS400): Define. * opcode/arc.h (ARC_OPCODE_NPS400): Define. opcodes/ChangeLog: * arc-dis.c (print_insn_arc): Handle nps400.
168 lines
4.5 KiB
Plaintext
168 lines
4.5 KiB
Plaintext
2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
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* arc-dis.c (print_insn_arc): Handle nps400.
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2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
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* arc-opc.c (BASE): Delete.
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2016-03-18 Nick Clifton <nickc@redhat.com>
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PR target/19721
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* aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
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of MOV insn that aliases an ORR insn.
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2016-03-16 Jiong Wang <jiong.wang@arm.com>
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* arm-dis.c (neon_opcodes): Support new FP16 instructions.
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2016-03-07 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
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* mcore-opc.h: Add const qualifiers.
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* microblaze-opc.h (struct op_code_struct): Likewise.
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* sh-opc.h: Likewise.
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* tic4x-dis.c (tic4x_print_indirect): Likewise.
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(tic4x_print_op): Likewise.
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2016-03-02 Alan Modra <amodra@gmail.com>
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* or1k-desc.h: Regenerate.
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* fr30-ibld.c: Regenerate.
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* rl78-decode.c: Regenerate.
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2016-03-01 Nick Clifton <nickc@redhat.com>
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PR target/19747
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* rl78-dis.c (print_insn_rl78_common): Fix typo.
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2016-02-24 Renlin Li <renlin.li@arm.com>
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* arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
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(print_insn_coprocessor): Support fp16 instructions.
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2016-02-24 Renlin Li <renlin.li@arm.com>
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* arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
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vminnm, vrint(mpna).
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2016-02-24 Renlin Li <renlin.li@arm.com>
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* arm-dis.c (print_insn_coprocessor): Check co-processor number for
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cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
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2016-02-15 H.J. Lu <hongjiu.lu@intel.com>
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* i386-dis.c (print_insn): Parenthesize expression to prevent
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truncated addresses.
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(OP_J): Likewise.
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2016-02-10 Claudiu Zissulescu <claziss@synopsys.com>
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Janek van Oirschot <jvanoirs@synopsys.com>
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* arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
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variable.
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2016-02-04 Nick Clifton <nickc@redhat.com>
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PR target/19561
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* msp430-dis.c (print_insn_msp430): Add a special case for
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decoding an RRC instruction with the ZC bit set in the extension
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word.
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2016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
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* cgen-ibld.in (insert_normal): Rework calculation of shift.
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* epiphany-ibld.c: Regenerate.
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* fr30-ibld.c: Regenerate.
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* frv-ibld.c: Regenerate.
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* ip2k-ibld.c: Regenerate.
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* iq2000-ibld.c: Regenerate.
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* lm32-ibld.c: Regenerate.
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* m32c-ibld.c: Regenerate.
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* m32r-ibld.c: Regenerate.
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* mep-ibld.c: Regenerate.
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* mt-ibld.c: Regenerate.
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* or1k-ibld.c: Regenerate.
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* xc16x-ibld.c: Regenerate.
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* xstormy16-ibld.c: Regenerate.
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2016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
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* epiphany-dis.c: Regenerated from latest cpu files.
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2016-02-01 Michael McConville <mmcco@mykolab.com>
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* cgen-dis.c (count_decodable_bits): Use unsigned value for mask
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test bit.
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2016-01-25 Renlin Li <renlin.li@arm.com>
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* arm-dis.c (mapping_symbol_for_insn): New function.
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(find_ifthen_state): Call mapping_symbol_for_insn().
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2016-01-20 Matthew Wahab <matthew.wahab@arm.com>
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* aarch64-opc.c (operand_general_constraint_met_p): Check validity
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of MSR UAO immediate operand.
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2016-01-18 Maciej W. Rozycki <macro@imgtec.com>
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* mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
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instruction support.
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2016-01-17 Alan Modra <amodra@gmail.com>
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* configure: Regenerate.
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2016-01-14 Nick Clifton <nickc@redhat.com>
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* rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
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instructions that can support stack pointer operations.
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* rl78-decode.c: Regenerate.
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* rl78-dis.c: Fix display of stack pointer in MOVW based
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instructions.
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2016-01-14 Matthew Wahab <matthew.wahab@arm.com>
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* aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
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testing for RAS support. Add checks for erxfr_el1, erxctlr_el1,
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erxtatus_el1 and erxaddr_el1.
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2016-01-12 Matthew Wahab <matthew.wahab@arm.com>
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* arm-dis.c (arm_opcodes): Add "esb".
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(thumb_opcodes): Likewise.
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2016-01-11 Peter Bergner <bergner@vnet.ibm.com>
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* ppc-opc.c <xscmpnedp>: Delete.
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<xvcmpnedp>: Likewise.
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<xvcmpnedp.>: Likewise.
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<xvcmpnesp>: Likewise.
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<xvcmpnesp.>: Likewise.
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2016-01-08 Andreas Schwab <schwab@linux-m68k.org>
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PR gas/13050
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* m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
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addition to ISA_A.
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2016-01-01 Alan Modra <amodra@gmail.com>
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Update year range in copyright notice of all files.
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For older changes see ChangeLog-2015
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Copyright (C) 2016 Free Software Foundation, Inc.
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Copying and distribution of this file, with or without modification,
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are permitted in any medium without royalty provided the copyright
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notice and this notice are preserved.
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Local Variables:
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mode: change-log
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left-margin: 8
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fill-column: 74
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version-control: never
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End:
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