141 lines
4.1 KiB
C
141 lines
4.1 KiB
C
/* Ravenscar RISC-V target support.
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Copyright (C) 2019-2020 Free Software Foundation, Inc.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#include "defs.h"
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#include "gdbarch.h"
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#include "gdbcore.h"
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#include "regcache.h"
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#include "riscv-tdep.h"
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#include "inferior.h"
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#include "ravenscar-thread.h"
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#include "riscv-ravenscar-thread.h"
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struct riscv_ravenscar_ops : public ravenscar_arch_ops
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{
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void fetch_registers (struct regcache *regcache, int regnum) override;
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void store_registers (struct regcache *regcache, int regnum) override;
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private:
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/* Return the offset of the register in the context buffer. */
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int register_offset (struct gdbarch *arch, int regnum);
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};
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int
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riscv_ravenscar_ops::register_offset (struct gdbarch *arch, int regnum)
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{
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int offset;
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if (regnum == RISCV_RA_REGNUM || regnum == RISCV_PC_REGNUM)
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offset = 0;
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else if (regnum == RISCV_SP_REGNUM)
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offset = 1;
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else if (regnum == RISCV_ZERO_REGNUM + 8) /* S0 */
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offset = 2;
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else if (regnum == RISCV_ZERO_REGNUM + 9) /* S1 */
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offset = 3;
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else if (regnum >= RISCV_ZERO_REGNUM + 19
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&& regnum <= RISCV_ZERO_REGNUM + 27) /* S2..S11 */
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offset = regnum - (RISCV_ZERO_REGNUM + 19) + 4;
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else if (regnum >= RISCV_FIRST_FP_REGNUM
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&& regnum <= RISCV_FIRST_FP_REGNUM + 11)
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offset = regnum - RISCV_FIRST_FP_REGNUM + 14; /* FS0..FS11 */
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else
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{
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/* Not saved. */
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return -1;
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}
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int size = register_size (arch, regnum);
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return offset * size;
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}
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/* Supply register REGNUM, which has been saved on REGISTER_ADDR, to the
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regcache. */
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static void
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supply_register_at_address (struct regcache *regcache, int regnum,
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CORE_ADDR register_addr)
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{
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struct gdbarch *gdbarch = regcache->arch ();
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int buf_size = register_size (gdbarch, regnum);
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gdb_byte *buf;
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buf = (gdb_byte *) alloca (buf_size);
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read_memory (register_addr, buf, buf_size);
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regcache->raw_supply (regnum, buf);
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}
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void
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riscv_ravenscar_ops::fetch_registers (struct regcache *regcache, int regnum)
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{
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struct gdbarch *gdbarch = regcache->arch ();
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const int num_regs = gdbarch_num_regs (gdbarch);
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int current_regnum;
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CORE_ADDR current_address;
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CORE_ADDR thread_descriptor_address;
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/* The tid is the thread_id field, which is a pointer to the thread. */
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thread_descriptor_address = (CORE_ADDR) inferior_ptid.tid ();
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/* Read registers. */
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for (current_regnum = 0; current_regnum < num_regs; current_regnum++)
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{
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int offset = register_offset (gdbarch, current_regnum);
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if (offset != -1)
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{
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current_address = thread_descriptor_address + offset;
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supply_register_at_address (regcache, current_regnum,
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current_address);
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}
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}
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}
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void
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riscv_ravenscar_ops::store_registers (struct regcache *regcache, int regnum)
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{
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struct gdbarch *gdbarch = regcache->arch ();
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int buf_size = register_size (gdbarch, regnum);
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gdb_byte buf[buf_size];
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CORE_ADDR register_address;
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int offset = register_offset (gdbarch, regnum);
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if (offset != -1)
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{
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register_address = inferior_ptid.tid () + offset;
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regcache->raw_collect (regnum, buf);
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write_memory (register_address,
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buf,
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buf_size);
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}
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}
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/* The ravenscar_arch_ops vector for most RISC-V targets. */
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static struct riscv_ravenscar_ops riscv_ravenscar_ops;
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/* Register riscv_ravenscar_ops in GDBARCH. */
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void
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register_riscv_ravenscar_ops (struct gdbarch *gdbarch)
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{
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set_gdbarch_ravenscar_ops (gdbarch, &riscv_ravenscar_ops);
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}
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