497 lines
20 KiB
C
497 lines
20 KiB
C
/* OBSOLETE /* This file is part of the program psim. */
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/* OBSOLETE */
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/* OBSOLETE Copyright (C) 1994-1997, Andrew Cagney <cagney@highland.com.au> */
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/* OBSOLETE Copyright (C) 1996, 1997, Free Software Foundation */
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/* OBSOLETE */
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/* OBSOLETE This program is free software; you can redistribute it and/or modify */
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/* OBSOLETE it under the terms of the GNU General Public License as published by */
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/* OBSOLETE the Free Software Foundation; either version 2 of the License, or */
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/* OBSOLETE (at your option) any later version. */
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/* OBSOLETE */
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/* OBSOLETE This program is distributed in the hope that it will be useful, */
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/* OBSOLETE but WITHOUT ANY WARRANTY; without even the implied warranty of */
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/* OBSOLETE MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the */
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/* OBSOLETE GNU General Public License for more details. */
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/* OBSOLETE */
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/* OBSOLETE You should have received a copy of the GNU General Public License */
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/* OBSOLETE along with this program; if not, write to the Free Software */
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/* OBSOLETE Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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/* OBSOLETE */
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/* OBSOLETE */ */
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/* OBSOLETE */
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/* OBSOLETE */
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/* OBSOLETE #ifndef ENGINE_C */
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/* OBSOLETE #define ENGINE_C */
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/* OBSOLETE */
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/* OBSOLETE #include "sim-main.h" */
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/* OBSOLETE */
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/* OBSOLETE #include <stdio.h> */
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/* OBSOLETE #include <ctype.h> */
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/* OBSOLETE */
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/* OBSOLETE #ifdef HAVE_STDLIB_H */
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/* OBSOLETE #include <stdlib.h> */
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/* OBSOLETE #endif */
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/* OBSOLETE */
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/* OBSOLETE #ifdef HAVE_STRING_H */
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/* OBSOLETE #include <string.h> */
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/* OBSOLETE #else */
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/* OBSOLETE #ifdef HAVE_STRINGS_H */
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/* OBSOLETE #include <strings.h> */
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/* OBSOLETE #endif */
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/* OBSOLETE #endif */
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/* OBSOLETE */
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/* OBSOLETE static void */
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/* OBSOLETE do_stack_swap (SIM_DESC sd) */
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/* OBSOLETE { */
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/* OBSOLETE sim_cpu *cpu = STATE_CPU (sd, 0); */
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/* OBSOLETE unsigned new_sp = (PSW_VAL(PSW_SM) != 0); */
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/* OBSOLETE if (cpu->regs.current_sp != new_sp) */
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/* OBSOLETE { */
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/* OBSOLETE cpu->regs.sp[cpu->regs.current_sp] = SP; */
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/* OBSOLETE cpu->regs.current_sp = new_sp; */
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/* OBSOLETE SP = cpu->regs.sp[cpu->regs.current_sp]; */
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/* OBSOLETE } */
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/* OBSOLETE } */
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/* OBSOLETE */
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/* OBSOLETE #if WITH_TRACE */
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/* OBSOLETE /* Implement ALU tracing of 32-bit registers. */ */
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/* OBSOLETE static void */
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/* OBSOLETE trace_alu32 (SIM_DESC sd, */
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/* OBSOLETE sim_cpu *cpu, */
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/* OBSOLETE address_word cia, */
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/* OBSOLETE unsigned32 *ptr) */
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/* OBSOLETE { */
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/* OBSOLETE unsigned32 value = *ptr; */
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/* OBSOLETE */
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/* OBSOLETE if (ptr >= &GPR[0] && ptr <= &GPR[NR_GENERAL_PURPOSE_REGISTERS]) */
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/* OBSOLETE trace_one_insn (sd, cpu, cia, 1, "engine.c", __LINE__, "alu", */
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/* OBSOLETE "Set register r%-2d = 0x%.8lx (%ld)", */
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/* OBSOLETE ptr - &GPR[0], (long)value, (long)value); */
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/* OBSOLETE */
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/* OBSOLETE else if (ptr == &PSW || ptr == &bPSW || ptr == &DPSW) */
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/* OBSOLETE trace_one_insn (sd, cpu, cia, 1, "engine.c", __LINE__, "alu", */
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/* OBSOLETE "Set register %s = 0x%.8lx%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s", */
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/* OBSOLETE (ptr == &PSW) ? "psw" : ((ptr == &bPSW) ? "bpsw" : "dpsw"), */
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/* OBSOLETE (long)value, */
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/* OBSOLETE (value & (0x80000000 >> PSW_SM)) ? ", sm" : "", */
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/* OBSOLETE (value & (0x80000000 >> PSW_EA)) ? ", ea" : "", */
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/* OBSOLETE (value & (0x80000000 >> PSW_DB)) ? ", db" : "", */
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/* OBSOLETE (value & (0x80000000 >> PSW_DS)) ? ", ds" : "", */
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/* OBSOLETE (value & (0x80000000 >> PSW_IE)) ? ", ie" : "", */
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/* OBSOLETE (value & (0x80000000 >> PSW_RP)) ? ", rp" : "", */
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/* OBSOLETE (value & (0x80000000 >> PSW_MD)) ? ", md" : "", */
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/* OBSOLETE (value & (0x80000000 >> PSW_F0)) ? ", f0" : "", */
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/* OBSOLETE (value & (0x80000000 >> PSW_F1)) ? ", f1" : "", */
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/* OBSOLETE (value & (0x80000000 >> PSW_F2)) ? ", f2" : "", */
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/* OBSOLETE (value & (0x80000000 >> PSW_F3)) ? ", f3" : "", */
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/* OBSOLETE (value & (0x80000000 >> PSW_S)) ? ", s" : "", */
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/* OBSOLETE (value & (0x80000000 >> PSW_V)) ? ", v" : "", */
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/* OBSOLETE (value & (0x80000000 >> PSW_VA)) ? ", va" : "", */
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/* OBSOLETE (value & (0x80000000 >> PSW_C)) ? ", c" : ""); */
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/* OBSOLETE */
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/* OBSOLETE else if (ptr >= &CREG[0] && ptr <= &CREG[NR_CONTROL_REGISTERS]) */
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/* OBSOLETE trace_one_insn (sd, cpu, cia, 1, "engine.c", __LINE__, "alu", */
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/* OBSOLETE "Set register cr%d = 0x%.8lx (%ld)", */
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/* OBSOLETE ptr - &CREG[0], (long)value, (long)value); */
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/* OBSOLETE } */
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/* OBSOLETE */
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/* OBSOLETE /* Implement ALU tracing of 32-bit registers. */ */
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/* OBSOLETE static void */
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/* OBSOLETE trace_alu64 (SIM_DESC sd, */
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/* OBSOLETE sim_cpu *cpu, */
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/* OBSOLETE address_word cia, */
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/* OBSOLETE unsigned64 *ptr) */
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/* OBSOLETE { */
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/* OBSOLETE unsigned64 value = *ptr; */
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/* OBSOLETE */
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/* OBSOLETE if (ptr >= &ACC[0] && ptr <= &ACC[NR_ACCUMULATORS]) */
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/* OBSOLETE trace_one_insn (sd, cpu, cia, 1, "engine.c", __LINE__, "alu", */
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/* OBSOLETE "Set register a%-2d = 0x%.8lx 0x%.8lx", */
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/* OBSOLETE ptr - &ACC[0], */
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/* OBSOLETE (unsigned long)(unsigned32)(value >> 32), */
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/* OBSOLETE (unsigned long)(unsigned32)value); */
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/* OBSOLETE */
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/* OBSOLETE } */
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/* OBSOLETE #endif */
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/* OBSOLETE */
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/* OBSOLETE /* Process all of the queued up writes in order now */ */
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/* OBSOLETE void */
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/* OBSOLETE unqueue_writes (SIM_DESC sd, */
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/* OBSOLETE sim_cpu *cpu, */
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/* OBSOLETE address_word cia) */
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/* OBSOLETE { */
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/* OBSOLETE int i, num; */
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/* OBSOLETE int did_psw = 0; */
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/* OBSOLETE unsigned32 *psw_addr = &PSW; */
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/* OBSOLETE */
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/* OBSOLETE num = WRITE32_NUM; */
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/* OBSOLETE for (i = 0; i < num; i++) */
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/* OBSOLETE { */
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/* OBSOLETE unsigned32 mask = WRITE32_MASK (i); */
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/* OBSOLETE unsigned32 *ptr = WRITE32_PTR (i); */
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/* OBSOLETE unsigned32 value = (*ptr & ~mask) | (WRITE32_VALUE (i) & mask); */
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/* OBSOLETE int j; */
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/* OBSOLETE */
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/* OBSOLETE if (ptr == psw_addr) */
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/* OBSOLETE { */
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/* OBSOLETE /* If MU instruction was not a MVTSYS, resolve PSW */
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/* OBSOLETE contention in favour of IU. */ */
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/* OBSOLETE if(! STATE_CPU (sd, 0)->mvtsys_left_p) */
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/* OBSOLETE { */
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/* OBSOLETE /* Detect contention in parallel writes to the same PSW flags. */
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/* OBSOLETE The hardware allows the updates from IU to prevail over */
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/* OBSOLETE those from MU. */ */
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/* OBSOLETE */
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/* OBSOLETE unsigned32 flag_bits = */
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/* OBSOLETE BIT32 (PSW_F0) | BIT32 (PSW_F1) | */
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/* OBSOLETE BIT32 (PSW_F2) | BIT32 (PSW_F3) | */
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/* OBSOLETE BIT32 (PSW_S) | BIT32 (PSW_V) | */
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/* OBSOLETE BIT32 (PSW_VA) | BIT32 (PSW_C); */
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/* OBSOLETE unsigned32 my_flag_bits = mask & flag_bits; */
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/* OBSOLETE */
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/* OBSOLETE for (j = i + 1; j < num; j++) */
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/* OBSOLETE if (WRITE32_PTR (j) == psw_addr && /* write to PSW */ */
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/* OBSOLETE WRITE32_MASK (j) & my_flag_bits) /* some of the same flags */ */
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/* OBSOLETE { */
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/* OBSOLETE /* Recompute local mask & value, to suppress this */
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/* OBSOLETE earlier write to the same flag bits. */ */
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/* OBSOLETE */
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/* OBSOLETE unsigned32 new_mask = mask & ~(WRITE32_MASK (j) & my_flag_bits); */
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/* OBSOLETE */
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/* OBSOLETE /* There is a special case for the VA (accumulated */
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/* OBSOLETE overflow) flag, in that it is only included in the */
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/* OBSOLETE second instruction's mask if the overflow */
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/* OBSOLETE occurred. Yet the hardware still suppresses the */
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/* OBSOLETE first instruction's update to VA. So we kludge */
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/* OBSOLETE this by inferring PSW_V -> PSW_VA for the second */
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/* OBSOLETE instruction. */ */
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/* OBSOLETE */
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/* OBSOLETE if (WRITE32_MASK (j) & BIT32 (PSW_V)) */
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/* OBSOLETE { */
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/* OBSOLETE new_mask &= ~BIT32 (PSW_VA); */
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/* OBSOLETE } */
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/* OBSOLETE */
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/* OBSOLETE value = (*ptr & ~new_mask) | (WRITE32_VALUE (i) & new_mask); */
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/* OBSOLETE } */
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/* OBSOLETE } */
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/* OBSOLETE */
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/* OBSOLETE did_psw = 1; */
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/* OBSOLETE } */
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/* OBSOLETE */
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/* OBSOLETE *ptr = value; */
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/* OBSOLETE */
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/* OBSOLETE #if WITH_TRACE */
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/* OBSOLETE if (TRACE_ALU_P (cpu)) */
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/* OBSOLETE trace_alu32 (sd, cpu, cia, ptr); */
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/* OBSOLETE #endif */
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/* OBSOLETE } */
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/* OBSOLETE */
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/* OBSOLETE num = WRITE64_NUM; */
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/* OBSOLETE for (i = 0; i < num; i++) */
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/* OBSOLETE { */
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/* OBSOLETE unsigned64 *ptr = WRITE64_PTR (i); */
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/* OBSOLETE *ptr = WRITE64_VALUE (i); */
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/* OBSOLETE */
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/* OBSOLETE #if WITH_TRACE */
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/* OBSOLETE if (TRACE_ALU_P (cpu)) */
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/* OBSOLETE trace_alu64 (sd, cpu, cia, ptr); */
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/* OBSOLETE #endif */
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/* OBSOLETE } */
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/* OBSOLETE */
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/* OBSOLETE WRITE32_NUM = 0; */
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/* OBSOLETE WRITE64_NUM = 0; */
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/* OBSOLETE */
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/* OBSOLETE if (DID_TRAP == 1) /* ordinary trap */ */
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/* OBSOLETE { */
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/* OBSOLETE bPSW = PSW; */
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/* OBSOLETE PSW &= (BIT32 (PSW_DB) | BIT32 (PSW_SM)); */
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/* OBSOLETE did_psw = 1; */
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/* OBSOLETE } */
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/* OBSOLETE else if (DID_TRAP == 2) /* debug trap */ */
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/* OBSOLETE { */
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/* OBSOLETE DPSW = PSW; */
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/* OBSOLETE PSW &= BIT32 (PSW_DS); */
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/* OBSOLETE PSW |= BIT32 (PSW_DS); */
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/* OBSOLETE did_psw = 1; */
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/* OBSOLETE } */
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/* OBSOLETE DID_TRAP = 0; */
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/* OBSOLETE */
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/* OBSOLETE if (did_psw) */
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/* OBSOLETE do_stack_swap (sd); */
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/* OBSOLETE } */
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/* OBSOLETE */
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/* OBSOLETE */
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/* OBSOLETE /* SIMULATE INSTRUCTIONS, various different ways of achieving the same */
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/* OBSOLETE thing */ */
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/* OBSOLETE */
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/* OBSOLETE static address_word */
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/* OBSOLETE do_long (SIM_DESC sd, */
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/* OBSOLETE l_instruction_word instruction, */
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/* OBSOLETE address_word cia) */
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/* OBSOLETE { */
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/* OBSOLETE address_word nia = l_idecode_issue(sd, */
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/* OBSOLETE instruction, */
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/* OBSOLETE cia); */
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/* OBSOLETE */
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/* OBSOLETE unqueue_writes (sd, STATE_CPU (sd, 0), cia); */
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/* OBSOLETE return nia; */
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/* OBSOLETE } */
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/* OBSOLETE */
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/* OBSOLETE static address_word */
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/* OBSOLETE do_2_short (SIM_DESC sd, */
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/* OBSOLETE s_instruction_word insn1, */
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/* OBSOLETE s_instruction_word insn2, */
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/* OBSOLETE cpu_units unit, */
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/* OBSOLETE address_word cia) */
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/* OBSOLETE { */
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/* OBSOLETE address_word nia; */
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/* OBSOLETE */
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/* OBSOLETE /* run the first instruction */ */
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/* OBSOLETE STATE_CPU (sd, 0)->unit = unit; */
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/* OBSOLETE STATE_CPU (sd, 0)->left_kills_right_p = 0; */
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/* OBSOLETE STATE_CPU (sd, 0)->mvtsys_left_p = 0; */
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/* OBSOLETE nia = s_idecode_issue(sd, */
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/* OBSOLETE insn1, */
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/* OBSOLETE cia); */
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/* OBSOLETE */
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/* OBSOLETE unqueue_writes (sd, STATE_CPU (sd, 0), cia); */
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/* OBSOLETE */
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/* OBSOLETE /* Only do the second instruction if the PC has not changed */ */
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/* OBSOLETE if ((nia == INVALID_INSTRUCTION_ADDRESS) && */
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/* OBSOLETE (! STATE_CPU (sd, 0)->left_kills_right_p)) { */
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/* OBSOLETE STATE_CPU (sd, 0)->unit = any_unit; */
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/* OBSOLETE nia = s_idecode_issue (sd, */
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/* OBSOLETE insn2, */
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/* OBSOLETE cia); */
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/* OBSOLETE */
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/* OBSOLETE unqueue_writes (sd, STATE_CPU (sd, 0), cia); */
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/* OBSOLETE } */
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/* OBSOLETE */
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/* OBSOLETE STATE_CPU (sd, 0)->left_kills_right_p = 0; */
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/* OBSOLETE STATE_CPU (sd, 0)->mvtsys_left_p = 0; */
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/* OBSOLETE return nia; */
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/* OBSOLETE } */
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/* OBSOLETE */
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/* OBSOLETE static address_word */
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/* OBSOLETE do_parallel (SIM_DESC sd, */
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/* OBSOLETE s_instruction_word left_insn, */
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/* OBSOLETE s_instruction_word right_insn, */
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/* OBSOLETE address_word cia) */
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/* OBSOLETE { */
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/* OBSOLETE address_word nia_left; */
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/* OBSOLETE address_word nia_right; */
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/* OBSOLETE address_word nia; */
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/* OBSOLETE */
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/* OBSOLETE /* run the first instruction */ */
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/* OBSOLETE STATE_CPU (sd, 0)->unit = memory_unit; */
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/* OBSOLETE STATE_CPU (sd, 0)->left_kills_right_p = 0; */
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/* OBSOLETE STATE_CPU (sd, 0)->mvtsys_left_p = 0; */
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/* OBSOLETE nia_left = s_idecode_issue(sd, */
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/* OBSOLETE left_insn, */
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/* OBSOLETE cia); */
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/* OBSOLETE */
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/* OBSOLETE /* run the second instruction */ */
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/* OBSOLETE STATE_CPU (sd, 0)->unit = integer_unit; */
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/* OBSOLETE nia_right = s_idecode_issue(sd, */
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/* OBSOLETE right_insn, */
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/* OBSOLETE cia); */
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/* OBSOLETE */
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/* OBSOLETE /* merge the PC's */ */
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/* OBSOLETE if (nia_left == INVALID_INSTRUCTION_ADDRESS) { */
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/* OBSOLETE if (nia_right == INVALID_INSTRUCTION_ADDRESS) */
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/* OBSOLETE nia = INVALID_INSTRUCTION_ADDRESS; */
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/* OBSOLETE else */
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/* OBSOLETE nia = nia_right; */
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/* OBSOLETE } */
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/* OBSOLETE else { */
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/* OBSOLETE if (nia_right == INVALID_INSTRUCTION_ADDRESS) */
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/* OBSOLETE nia = nia_left; */
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/* OBSOLETE else { */
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/* OBSOLETE sim_engine_abort (sd, STATE_CPU (sd, 0), cia, "parallel jumps"); */
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/* OBSOLETE nia = INVALID_INSTRUCTION_ADDRESS; */
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/* OBSOLETE } */
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/* OBSOLETE } */
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/* OBSOLETE */
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/* OBSOLETE unqueue_writes (sd, STATE_CPU (sd, 0), cia); */
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/* OBSOLETE return nia; */
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/* OBSOLETE } */
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/* OBSOLETE */
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/* OBSOLETE */
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/* OBSOLETE typedef enum { */
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/* OBSOLETE p_insn = 0, */
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/* OBSOLETE long_insn = 3, */
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/* OBSOLETE l_r_insn = 1, */
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/* OBSOLETE r_l_insn = 2, */
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/* OBSOLETE } instruction_types; */
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/* OBSOLETE */
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/* OBSOLETE STATIC_INLINE instruction_types */
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/* OBSOLETE instruction_type(l_instruction_word insn) */
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/* OBSOLETE { */
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/* OBSOLETE int fm0 = MASKED64(insn, 0, 0) != 0; */
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/* OBSOLETE int fm1 = MASKED64(insn, 32, 32) != 0; */
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/* OBSOLETE return ((fm0 << 1) | fm1); */
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/* OBSOLETE } */
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/* OBSOLETE */
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/* OBSOLETE */
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/* OBSOLETE */
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/* OBSOLETE void */
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/* OBSOLETE sim_engine_run (SIM_DESC sd, */
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/* OBSOLETE int last_cpu_nr, */
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/* OBSOLETE int nr_cpus, */
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/* OBSOLETE int siggnal) */
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/* OBSOLETE { */
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/* OBSOLETE while (1) */
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/* OBSOLETE { */
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/* OBSOLETE address_word cia = PC; */
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/* OBSOLETE address_word nia; */
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/* OBSOLETE l_instruction_word insn = IMEM(cia); */
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/* OBSOLETE int rp_was_set; */
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/* OBSOLETE int rpt_c_was_nonzero; */
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/* OBSOLETE */
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/* OBSOLETE /* Before executing the instruction, we need to test whether or */
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/* OBSOLETE not RPT_C is greater than zero, and save that state for use */
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/* OBSOLETE after executing the instruction. In particular, we need to */
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/* OBSOLETE not care whether the instruction changes RPT_C itself. */ */
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/* OBSOLETE */
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/* OBSOLETE rpt_c_was_nonzero = (RPT_C > 0); */
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/* OBSOLETE */
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/* OBSOLETE /* Before executing the instruction, we need to check to see if */
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/* OBSOLETE we have to decrement RPT_C, the repeat count register. Do this */
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/* OBSOLETE if PC == RPT_E, but only if we are in an active repeat block. */ */
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/* OBSOLETE */
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/* OBSOLETE if (PC == RPT_E && */
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/* OBSOLETE (RPT_C > 0 || PSW_VAL (PSW_RP) != 0)) */
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/* OBSOLETE { */
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/* OBSOLETE RPT_C --; */
|
|
/* OBSOLETE } */
|
|
/* OBSOLETE */
|
|
/* OBSOLETE /* Now execute the instruction at PC */ */
|
|
/* OBSOLETE */
|
|
/* OBSOLETE switch (instruction_type (insn)) */
|
|
/* OBSOLETE { */
|
|
/* OBSOLETE case long_insn: */
|
|
/* OBSOLETE nia = do_long (sd, insn, cia); */
|
|
/* OBSOLETE break; */
|
|
/* OBSOLETE case r_l_insn: */
|
|
/* OBSOLETE /* L <- R */ */
|
|
/* OBSOLETE nia = do_2_short (sd, insn, insn >> 32, integer_unit, cia); */
|
|
/* OBSOLETE break; */
|
|
/* OBSOLETE case l_r_insn: */
|
|
/* OBSOLETE /* L -> R */ */
|
|
/* OBSOLETE nia = do_2_short (sd, insn >> 32, insn, memory_unit, cia); */
|
|
/* OBSOLETE break; */
|
|
/* OBSOLETE case p_insn: */
|
|
/* OBSOLETE nia = do_parallel (sd, insn >> 32, insn, cia); */
|
|
/* OBSOLETE break; */
|
|
/* OBSOLETE default: */
|
|
/* OBSOLETE sim_engine_abort (sd, STATE_CPU (sd, 0), cia, */
|
|
/* OBSOLETE "internal error - engine_run_until_stop - bad switch"); */
|
|
/* OBSOLETE nia = -1; */
|
|
/* OBSOLETE } */
|
|
/* OBSOLETE */
|
|
/* OBSOLETE if (TRACE_ACTION) */
|
|
/* OBSOLETE { */
|
|
/* OBSOLETE if (TRACE_ACTION & TRACE_ACTION_CALL) */
|
|
/* OBSOLETE call_occurred (sd, STATE_CPU (sd, 0), cia, nia); */
|
|
/* OBSOLETE */
|
|
/* OBSOLETE if (TRACE_ACTION & TRACE_ACTION_RETURN) */
|
|
/* OBSOLETE return_occurred (sd, STATE_CPU (sd, 0), cia, nia); */
|
|
/* OBSOLETE */
|
|
/* OBSOLETE TRACE_ACTION = 0; */
|
|
/* OBSOLETE } */
|
|
/* OBSOLETE */
|
|
/* OBSOLETE /* Check now to see if we need to reset the RP bit in the PSW. */
|
|
/* OBSOLETE There are three conditions for this, the RP bit is already */
|
|
/* OBSOLETE set (just a speed optimization), the instruction we just */
|
|
/* OBSOLETE executed is the last instruction in the loop, and the repeat */
|
|
/* OBSOLETE count is currently zero. */ */
|
|
/* OBSOLETE */
|
|
/* OBSOLETE rp_was_set = PSW_VAL (PSW_RP); */
|
|
/* OBSOLETE if (rp_was_set && (PC == RPT_E) && RPT_C == 0) */
|
|
/* OBSOLETE { */
|
|
/* OBSOLETE PSW_SET (PSW_RP, 0); */
|
|
/* OBSOLETE } */
|
|
/* OBSOLETE */
|
|
/* OBSOLETE /* Now update the PC. If we just executed a jump instruction, */
|
|
/* OBSOLETE that takes precedence over everything else. Next comes */
|
|
/* OBSOLETE branching back to RPT_S as a result of a loop. Finally, the */
|
|
/* OBSOLETE default is to simply advance to the next inline */
|
|
/* OBSOLETE instruction. */ */
|
|
/* OBSOLETE */
|
|
/* OBSOLETE if (nia != INVALID_INSTRUCTION_ADDRESS) */
|
|
/* OBSOLETE { */
|
|
/* OBSOLETE PC = nia; */
|
|
/* OBSOLETE } */
|
|
/* OBSOLETE else if (rp_was_set && rpt_c_was_nonzero && (PC == RPT_E)) */
|
|
/* OBSOLETE { */
|
|
/* OBSOLETE PC = RPT_S; */
|
|
/* OBSOLETE } */
|
|
/* OBSOLETE else */
|
|
/* OBSOLETE { */
|
|
/* OBSOLETE PC = cia + 8; */
|
|
/* OBSOLETE } */
|
|
/* OBSOLETE */
|
|
/* OBSOLETE /* Check for DDBT (debugger debug trap) condition. Do this after */
|
|
/* OBSOLETE the repeat block checks so the excursion to the trap handler does */
|
|
/* OBSOLETE not alter looping state. */ */
|
|
/* OBSOLETE */
|
|
/* OBSOLETE if (cia == IBA && PSW_VAL (PSW_DB)) */
|
|
/* OBSOLETE { */
|
|
/* OBSOLETE DPC = PC; */
|
|
/* OBSOLETE PSW_SET (PSW_EA, 1); */
|
|
/* OBSOLETE DPSW = PSW; */
|
|
/* OBSOLETE /* clear all bits in PSW except SM */ */
|
|
/* OBSOLETE PSW &= BIT32 (PSW_SM); */
|
|
/* OBSOLETE /* add DS bit */ */
|
|
/* OBSOLETE PSW |= BIT32 (PSW_DS); */
|
|
/* OBSOLETE /* dispatch to DDBT handler */ */
|
|
/* OBSOLETE PC = 0xfffff128; /* debugger_debug_trap_address */ */
|
|
/* OBSOLETE } */
|
|
/* OBSOLETE */
|
|
/* OBSOLETE /* process any events */ */
|
|
/* OBSOLETE /* FIXME - should L->R or L<-R insns count as two cycles? */ */
|
|
/* OBSOLETE if (sim_events_tick (sd)) */
|
|
/* OBSOLETE { */
|
|
/* OBSOLETE sim_events_process (sd); */
|
|
/* OBSOLETE } */
|
|
/* OBSOLETE } */
|
|
/* OBSOLETE } */
|
|
/* OBSOLETE */
|
|
/* OBSOLETE */
|
|
/* OBSOLETE /* d30v external interrupt handler. */
|
|
/* OBSOLETE */
|
|
/* OBSOLETE Note: This should be replaced by a proper interrupt delivery */
|
|
/* OBSOLETE mechanism. This interrupt mechanism discards later interrupts if */
|
|
/* OBSOLETE an earlier interrupt hasn't been delivered. */
|
|
/* OBSOLETE */
|
|
/* OBSOLETE Note: This interrupt mechanism does not reset its self when the */
|
|
/* OBSOLETE simulator is re-opened. */ */
|
|
/* OBSOLETE */
|
|
/* OBSOLETE void */
|
|
/* OBSOLETE d30v_interrupt_event (SIM_DESC sd, */
|
|
/* OBSOLETE void *data) */
|
|
/* OBSOLETE { */
|
|
/* OBSOLETE if (PSW_VAL (PSW_IE)) */
|
|
/* OBSOLETE /* interrupts not masked */ */
|
|
/* OBSOLETE { */
|
|
/* OBSOLETE /* scrub any pending interrupt */ */
|
|
/* OBSOLETE if (sd->pending_interrupt != NULL) */
|
|
/* OBSOLETE sim_events_deschedule (sd, sd->pending_interrupt); */
|
|
/* OBSOLETE /* deliver */ */
|
|
/* OBSOLETE bPSW = PSW; */
|
|
/* OBSOLETE bPC = PC; */
|
|
/* OBSOLETE PSW = 0; */
|
|
/* OBSOLETE PC = 0xfffff138; /* external interrupt */ */
|
|
/* OBSOLETE do_stack_swap (sd); */
|
|
/* OBSOLETE } */
|
|
/* OBSOLETE else if (sd->pending_interrupt == NULL) */
|
|
/* OBSOLETE /* interrupts masked and no interrupt pending */ */
|
|
/* OBSOLETE { */
|
|
/* OBSOLETE sd->pending_interrupt = sim_events_schedule (sd, 1, */
|
|
/* OBSOLETE d30v_interrupt_event, */
|
|
/* OBSOLETE data); */
|
|
/* OBSOLETE } */
|
|
/* OBSOLETE } */
|
|
/* OBSOLETE */
|
|
/* OBSOLETE #endif */
|