1204 lines
33 KiB
C
1204 lines
33 KiB
C
/* tc-iq2000.c -- Assembler for the Sitera IQ2000.
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Copyright (C) 2003 Free Software Foundation.
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This file is part of GAS, the GNU Assembler.
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GAS is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2, or (at your option)
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any later version.
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GAS is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with GAS; see the file COPYING. If not, write to
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the Free Software Foundation, 59 Temple Place - Suite 330,
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Boston, MA 02111-1307, USA. */
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#include <stdio.h>
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#include "as.h"
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#include "safe-ctype.h"
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#include "dwarf2dbg.h"
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#include "subsegs.h"
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#include "symcat.h"
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#include "opcodes/iq2000-desc.h"
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#include "opcodes/iq2000-opc.h"
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#include "cgen.h"
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#include "elf/common.h"
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#include "elf/iq2000.h"
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#include "libbfd.h"
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#include "hash.h"
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#include "macro.h"
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/* Structure to hold all of the different components describing
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an individual instruction. */
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typedef struct
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{
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const CGEN_INSN * insn;
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const CGEN_INSN * orig_insn;
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CGEN_FIELDS fields;
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#if CGEN_INT_INSN_P
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CGEN_INSN_INT buffer [1];
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#define INSN_VALUE(buf) (*(buf))
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#else
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unsigned char buffer [CGEN_MAX_INSN_SIZE];
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#define INSN_VALUE(buf) (buf)
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#endif
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char * addr;
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fragS * frag;
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int num_fixups;
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fixS * fixups [GAS_CGEN_MAX_FIXUPS];
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int indices [MAX_OPERAND_INSTANCES];
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}
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iq2000_insn;
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const char comment_chars[] = "#";
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const char line_comment_chars[] = "";
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const char line_separator_chars[] = ";";
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const char EXP_CHARS[] = "eE";
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const char FLT_CHARS[] = "dD";
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/* Default machine */
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#define DEFAULT_MACHINE bfd_mach_iq2000
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#define DEFAULT_FLAGS EF_IQ2000_CPU_IQ2000
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static unsigned long iq2000_mach = bfd_mach_iq2000;
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static int cpu_mach = (1 << MACH_IQ2000);
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/* Flags to set in the elf header */
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static flagword iq2000_flags = DEFAULT_FLAGS;
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typedef struct proc {
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symbolS *isym;
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unsigned long reg_mask;
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unsigned long reg_offset;
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unsigned long fpreg_mask;
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unsigned long fpreg_offset;
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unsigned long frame_offset;
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unsigned long frame_reg;
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unsigned long pc_reg;
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} procS;
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static procS cur_proc;
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static procS *cur_proc_ptr;
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static int numprocs;
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static void s_change_sec PARAMS ((int));
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static void s_iq2000_set PARAMS ((int));
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static void s_iq2000_mask PARAMS ((int));
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static void s_iq2000_frame PARAMS ((int));
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static void s_iq2000_ent PARAMS ((int));
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static void s_iq2000_end PARAMS ((int));
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static int get_number PARAMS ((void));
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static symbolS * get_symbol PARAMS ((void));
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static void iq2000_record_hi16 PARAMS((int, fixS *, segT));
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/* The target specific pseudo-ops which we support. */
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const pseudo_typeS md_pseudo_table[] =
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{
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{ "align", s_align_bytes, 0 },
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{ "word", cons, 4 },
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{ "file", dwarf2_directive_file, 0 },
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{ "loc", dwarf2_directive_loc, 0 },
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{ "rdata", s_change_sec, 'r'},
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{ "sdata", s_change_sec, 's'},
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{ "set", s_iq2000_set, 0 },
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{ "ent", s_iq2000_ent, 0 },
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{ "end", s_iq2000_end, 0 },
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{ "frame", s_iq2000_frame, 0 },
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{ "fmask", s_iq2000_mask, 'F' },
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{ "mask", s_iq2000_mask, 'R' },
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{ "dword", cons, 8 },
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{ "half", cons, 2 },
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{ NULL, NULL, 0 }
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};
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/* Relocations against symbols are done in two
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parts, with a HI relocation and a LO relocation. Each relocation
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has only 16 bits of space to store an addend. This means that in
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order for the linker to handle carries correctly, it must be able
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to locate both the HI and the LO relocation. This means that the
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relocations must appear in order in the relocation table.
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In order to implement this, we keep track of each unmatched HI
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relocation. We then sort them so that they immediately precede the
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corresponding LO relocation. */
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struct iq2000_hi_fixup
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{
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struct iq2000_hi_fixup * next; /* Next HI fixup. */
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fixS * fixp; /* This fixup. */
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segT seg; /* The section this fixup is in. */
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};
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/* The list of unmatched HI relocs. */
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static struct iq2000_hi_fixup * iq2000_hi_fixup_list;
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/* assembler options */
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#define OPTION_CPU_2000 (OPTION_MD_BASE)
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#define OPTION_CPU_10 (OPTION_MD_BASE + 1)
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struct option md_longopts[] =
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{
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{ "m2000", no_argument, NULL, OPTION_CPU_2000 },
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{ "m10", no_argument, NULL, OPTION_CPU_10 },
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{ NULL, no_argument, NULL, 0 },
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};
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size_t md_longopts_size = sizeof (md_longopts);
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const char * md_shortopts = "";
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static void iq2000_add_macro PARAMS ((const char *, const char *, const char **));
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static void iq2000_load_macros PARAMS ((void));
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static void iq10_load_macros PARAMS ((void));
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/* macro hash table, which we will add to. */
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extern struct hash_control *macro_hash;
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int
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md_parse_option (c, arg)
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int c ATTRIBUTE_UNUSED;
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char * arg ATTRIBUTE_UNUSED;
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{
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switch (c)
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{
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case OPTION_CPU_2000:
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iq2000_flags = (iq2000_flags & ~EF_IQ2000_CPU_MASK) | EF_IQ2000_CPU_IQ2000;
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iq2000_mach = bfd_mach_iq2000;
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cpu_mach = (1 << MACH_IQ2000);
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break;
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case OPTION_CPU_10:
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iq2000_flags = (iq2000_flags & ~EF_IQ2000_CPU_MASK) | EF_IQ2000_CPU_IQ10;
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iq2000_mach = bfd_mach_iq10;
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cpu_mach = (1 << MACH_IQ10);
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/* only the first 3 pseudo ops (word, file, loc) are in IQ10 */
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break;
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default:
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return 0;
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}
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return 1;
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}
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void
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md_show_usage (stream)
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FILE * stream;
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{
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fprintf (stream, _("IQ2000 specific command line options:\n"));
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fprintf (stream, _("-m2000 <default> IQ2000 processor\n"));
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fprintf (stream, _("-m10 IQ10 processor\n"));
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}
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void
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md_begin ()
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{
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/* Initialize the `cgen' interface. */
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/* Set the machine number and endian. */
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gas_cgen_cpu_desc = iq2000_cgen_cpu_open (CGEN_CPU_OPEN_MACHS, cpu_mach,
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CGEN_CPU_OPEN_ENDIAN,
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CGEN_ENDIAN_BIG,
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CGEN_CPU_OPEN_END);
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iq2000_cgen_init_asm (gas_cgen_cpu_desc);
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/* This is a callback from cgen to gas to parse operands. */
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cgen_set_parse_operand_fn (gas_cgen_cpu_desc, gas_cgen_parse_operand);
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/* Set the ELF flags if desired. */
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if (iq2000_flags)
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bfd_set_private_flags (stdoutput, iq2000_flags);
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/* Set the machine type */
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bfd_default_set_arch_mach (stdoutput, bfd_arch_iq2000, iq2000_mach);
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if (iq2000_mach == bfd_mach_iq2000)
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iq2000_load_macros ();
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else
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iq10_load_macros ();
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}
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static void
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iq2000_add_macro (name, semantics, arguments)
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const char *name;
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const char *semantics;
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const char **arguments;
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{
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macro_entry *macro;
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sb macro_name;
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const char *namestr;
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macro = (macro_entry *) xmalloc (sizeof (macro_entry));
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sb_new (¯o->sub);
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sb_new (¯o_name);
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macro->formal_count = 0;
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macro->formals = 0;
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sb_add_string (¯o->sub, semantics);
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if (arguments != NULL)
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{
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formal_entry **p = ¯o->formals;
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macro->formal_count = 0;
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macro->formal_hash = hash_new ();
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while (*arguments != NULL)
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{
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formal_entry *formal;
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formal = (formal_entry *) xmalloc (sizeof (formal_entry));
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sb_new (&formal->name);
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sb_new (&formal->def);
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sb_new (&formal->actual);
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/* chlm: Added the following to allow defaulted args. */
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if (strchr (*arguments,'='))
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{
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char * tt_args = strdup(*arguments);
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char * tt_dflt = strchr(tt_args,'=');
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*tt_dflt = 0;
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sb_add_string (&formal->name, tt_args);
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sb_add_string (&formal->def, tt_dflt + 1);
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}
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else
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sb_add_string (&formal->name, *arguments);
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/* Add to macro's hash table. */
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hash_jam (macro->formal_hash, sb_terminate (&formal->name), formal);
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formal->index = macro->formal_count;
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macro->formal_count++;
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*p = formal;
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p = &formal->next;
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*p = NULL;
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++arguments;
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}
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}
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sb_add_string (¯o_name, name);
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namestr = sb_terminate (¯o_name);
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hash_jam (macro_hash, namestr, (PTR) macro);
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macro_defined = 1;
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}
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/* Automatically enter conditional branch macros. */
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typedef struct {
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const char * mnemonic;
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const char ** expansion;
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const char ** args;
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} iq2000_macro_defs_s;
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static const char * abs_args[] = { "rd", "rs", "scratch=%1", NULL };
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static const char * abs_expn = "\n sra \\rd,\\rs,31\n xor \\scratch,\\rd,\\rs\n sub \\rd,\\scratch,\\rd\n";
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static const char * la_expn = "\n lui \\reg,%hi(\\label)\n ori \\reg,\\reg,%lo(\\label)\n";
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static const char * la_args[] = { "reg", "label", NULL };
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static const char * bxx_args[] = { "rs", "rt", "label", "scratch=%1", NULL };
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static const char * bge_expn = "\n slt \\scratch,\\rs,\\rt\n beq %0,\\scratch,\\label\n";
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static const char * bgeu_expn = "\n sltu \\scratch,\\rs,\\rt\n beq %0,\\scratch,\\label\n";
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static const char * bgt_expn = "\n slt \\scratch,\\rt,\\rs\n bne %0,\\scratch,\\label\n";
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static const char * bgtu_expn = "\n sltu \\scratch,\\rt,\\rs\n bne %0,\\scratch,\\label\n";
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static const char * ble_expn = "\n slt \\scratch,\\rt,\\rs\n beq %0,\\scratch,\\label\n";
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static const char * bleu_expn = "\n sltu \\scratch,\\rt,\\rs\n beq %0,\\scratch,\\label\n";
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static const char * blt_expn = "\n slt \\scratch,\\rs,\\rt\n bne %0,\\scratch,\\label\n";
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static const char * bltu_expn = "\n sltu \\scratch,\\rs,\\rt\n bne %0,\\scratch,\\label\n";
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static const char * sxx_args[] = { "rd", "rs", "rt", NULL };
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static const char * sge_expn = "\n slt \\rd,\\rs,\\rt\n xori \\rd,\\rd,1\n";
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static const char * sgeu_expn = "\n sltu \\rd,\\rs,\\rt\n xori \\rd,\\rd,1\n";
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static const char * sle_expn = "\n slt \\rd,\\rt,\\rs\n xori \\rd,\\rd,1\n";
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static const char * sleu_expn = "\n sltu \\rd,\\rt,\\rs\n xori \\rd,\\rd,1\n";
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static const char * sgt_expn = "\n slt \\rd,\\rt,\\rs\n";
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static const char * sgtu_expn = "\n sltu \\rd,\\rt,\\rs\n";
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static const char * sne_expn = "\n xor \\rd,\\rt,\\rs\n sltu \\rd,%0,\\rd\n";
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static const char * seq_expn = "\n xor \\rd,\\rt,\\rs\n sltu \\rd,%0,\\rd\n xori \\rd,\\rd,1\n";
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static const char * ai32_args[] = { "rt", "rs", "imm", NULL };
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static const char * andi32_expn = "\n\
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.if (\\imm & 0xffff0000 == 0xffff0000)\n\
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andoi \\rt,\\rs,%lo(\\imm)\n\
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.elseif (\\imm & 0x0000ffff == 0x0000ffff)\n\
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andoui \\rt,\\rs,%uhi(\\imm)\n\
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.elseif (\\imm & 0xffff0000 == 0x00000000)\n\
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andi \\rt,\\rs,%lo(\\imm)\n\
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.else\n\
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andoui \\rt,\\rs,%uhi(\\imm)\n\
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andoi \\rt,\\rt,%lo(\\imm)\n\
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.endif\n";
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static const char * ori32_expn = "\n\
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.if (\\imm & 0xffff == 0)\n\
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orui \\rt,\\rs,%uhi(\\imm)\n\
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.elseif (\\imm & 0xffff0000 == 0)\n\
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ori \\rt,\\rs,%lo(\\imm)\n\
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.else\n\
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orui \\rt,\\rs,%uhi(\\imm)\n\
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ori \\rt,\\rt,%lo(\\imm)\n\
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.endif\n";
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static const char * neg_args[] = { "rd", "rs", NULL };
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static const char * neg_expn = "\n sub \\rd,%0,\\rs\n";
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static const char * negu_expn = "\n subu \\rd,%0,\\rs\n";
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static const char * li_args[] = { "rt", "imm", NULL };
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static const char * li_expn = "\n\
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.if (\\imm & 0xffff0000 == 0x0)\n\
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ori \\rt,%0,\\imm\n\
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.elseif (\\imm & 0xffff0000 == 0xffff0000)\n\
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addi \\rt,%0,\\imm\n\
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.elseif (\\imm & 0x0000ffff == 0)
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lui \\rt,%uhi(\\imm)\n\
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.else\n\
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lui \\rt,%uhi(\\imm)\n\
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ori \\rt,\\rt,%lo(\\imm)\n\
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.endif\n";
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static iq2000_macro_defs_s iq2000_macro_defs[] = {
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{"abs", (const char **)&abs_expn, (const char **)&abs_args},
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{"la", (const char **)&la_expn, (const char **)&la_args},
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{"bge", (const char **)&bge_expn, (const char **)&bxx_args},
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{"bgeu", (const char **)&bgeu_expn, (const char **)&bxx_args},
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{"bgt", (const char **)&bgt_expn, (const char **)&bxx_args},
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{"bgtu", (const char **)&bgtu_expn, (const char **)&bxx_args},
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{"ble", (const char **)&ble_expn, (const char **)&bxx_args},
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{"bleu", (const char **)&bleu_expn, (const char **)&bxx_args},
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{"blt", (const char **)&blt_expn, (const char **)&bxx_args},
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{"bltu", (const char **)&bltu_expn, (const char **)&bxx_args},
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{"sge", (const char **)&sge_expn, (const char **)&sxx_args},
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{"sgeu", (const char **)&sgeu_expn, (const char **)&sxx_args},
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{"sle", (const char **)&sle_expn, (const char **)&sxx_args},
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{"sleu", (const char **)&sleu_expn, (const char **)&sxx_args},
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{"sgt", (const char **)&sgt_expn, (const char **)&sxx_args},
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{"sgtu", (const char **)&sgtu_expn, (const char **)&sxx_args},
|
||
{"seq", (const char **)&seq_expn, (const char **)&sxx_args},
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||
{"sne", (const char **)&sne_expn, (const char **)&sxx_args},
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{"neg", (const char **)&neg_expn, (const char **)&neg_args},
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{"negu", (const char **)&negu_expn, (const char **)&neg_args},
|
||
{"li", (const char **)&li_expn, (const char **)&li_args},
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||
{"ori32", (const char **)&ori32_expn, (const char **)&ai32_args},
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||
{"andi32",(const char **)&andi32_expn,(const char **)&ai32_args},
|
||
};
|
||
|
||
static void
|
||
iq2000_load_macros ()
|
||
{
|
||
int i;
|
||
int mcnt = sizeof (iq2000_macro_defs) / sizeof (iq2000_macro_defs_s);
|
||
|
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for (i = 0; i < mcnt; i++)
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iq2000_add_macro (iq2000_macro_defs[i].mnemonic,
|
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*iq2000_macro_defs[i].expansion,
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iq2000_macro_defs[i].args);
|
||
}
|
||
|
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static void
|
||
iq10_load_macros ()
|
||
{
|
||
/* Allow all iq2k macros in iq10, instead of just LA. */
|
||
iq2000_load_macros ();
|
||
#if 0
|
||
char *la_sem = "\n lui \\reg,%hi(\\label)\n ori \\reg,\\reg,%lo(\\label)\n";
|
||
|
||
char *la_arg_1 = "reg";
|
||
char *la_arg_2 = "label";
|
||
const char *la_args[3] = { la_arg_1, la_arg_2, NULL };
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||
|
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iq2000_add_macro ("la", la_sem, la_args);
|
||
#endif
|
||
}
|
||
|
||
|
||
void
|
||
md_assemble (str)
|
||
char * str;
|
||
{
|
||
static long delayed_load_register = 0;
|
||
static int last_insn_had_delay_slot = 0;
|
||
static int last_insn_has_load_delay = 0;
|
||
static int last_insn_unconditional_jump = 0;
|
||
static int last_insn_was_ldw = 0;
|
||
|
||
iq2000_insn insn;
|
||
char * errmsg;
|
||
|
||
/* Initialize GAS's cgen interface for a new instruction. */
|
||
gas_cgen_init_parse ();
|
||
|
||
insn.insn = iq2000_cgen_assemble_insn
|
||
(gas_cgen_cpu_desc, str, & insn.fields, insn.buffer, & errmsg);
|
||
|
||
if (!insn.insn)
|
||
{
|
||
as_bad ("%s", errmsg);
|
||
return;
|
||
}
|
||
|
||
/* Doesn't really matter what we pass for RELAX_P here. */
|
||
gas_cgen_finish_insn (insn.insn, insn.buffer,
|
||
CGEN_FIELDS_BITSIZE (& insn.fields), 1, NULL);
|
||
|
||
/* We need to generate an error if there's a yielding instruction in the delay
|
||
slot of a control flow modifying instruction (jump (yes), load (no)) */
|
||
if ((last_insn_had_delay_slot && !last_insn_has_load_delay) &&
|
||
CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_YIELD_INSN))
|
||
as_bad (_("the yielding instruction %s may not be in a delay slot."),
|
||
CGEN_INSN_NAME (insn.insn));
|
||
|
||
/* Warn about odd numbered base registers for paired-register
|
||
instructions like LDW. On iq2000, result is always rt. */
|
||
if (iq2000_mach == bfd_mach_iq2000
|
||
&& CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_EVEN_REG_NUM)
|
||
&& (insn.fields.f_rt % 2))
|
||
as_bad (_("Register number (R%ld) for double word access must be even."),
|
||
insn.fields.f_rt);
|
||
|
||
/* Warn about odd numbered base registers for paired-register
|
||
instructions like LDW. On iq10, result is always rd. */
|
||
if (iq2000_mach == bfd_mach_iq10
|
||
&& CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_EVEN_REG_NUM)
|
||
&& (insn.fields.f_rd % 2))
|
||
as_bad (_("Register number (R%ld) for double word access must be even."),
|
||
insn.fields.f_rd);
|
||
|
||
/* Warn about insns that reference the target of a previous load. */
|
||
/* NOTE: R0 is a special case and is not subject to load delays (except for ldw). */
|
||
if (delayed_load_register && (last_insn_has_load_delay || last_insn_was_ldw))
|
||
{
|
||
if (CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_USES_RD) &&
|
||
insn.fields.f_rd == delayed_load_register)
|
||
as_warn (_("operand references R%ld of previous load."),
|
||
insn.fields.f_rd);
|
||
|
||
if (CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_USES_RS) &&
|
||
insn.fields.f_rs == delayed_load_register)
|
||
as_warn (_("operand references R%ld of previous load."),
|
||
insn.fields.f_rs);
|
||
|
||
if (CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_USES_RT) &&
|
||
insn.fields.f_rt == delayed_load_register)
|
||
as_warn (_("operand references R%ld of previous load."),
|
||
insn.fields.f_rt);
|
||
|
||
if (CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_USES_R31) &&
|
||
delayed_load_register == 31)
|
||
as_warn (_("instruction implicitly accesses R31 of previous load."));
|
||
}
|
||
|
||
/* Warn about insns that reference the (target + 1) of a previous ldw */
|
||
if (last_insn_was_ldw)
|
||
{
|
||
if ((CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_USES_RD)
|
||
&& insn.fields.f_rd == delayed_load_register + 1)
|
||
|| (CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_USES_RS)
|
||
&& insn.fields.f_rs == delayed_load_register + 1)
|
||
|| (CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_USES_RT)
|
||
&& insn.fields.f_rt == delayed_load_register + 1))
|
||
as_warn (_("operand references R%ld of previous load."),
|
||
delayed_load_register + 1);
|
||
}
|
||
|
||
last_insn_had_delay_slot =
|
||
CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_DELAY_SLOT);
|
||
|
||
last_insn_has_load_delay =
|
||
CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_LOAD_DELAY);
|
||
|
||
if (last_insn_unconditional_jump)
|
||
last_insn_has_load_delay = last_insn_unconditional_jump = 0;
|
||
else if (! strcmp (CGEN_INSN_MNEMONIC (insn.insn), "j")
|
||
|| ! strcmp (CGEN_INSN_MNEMONIC (insn.insn), "jal"))
|
||
last_insn_unconditional_jump = 1;
|
||
|
||
/* The meaning of EVEN_REG_NUM was overloaded to also imply LDW. Since that's
|
||
not true for IQ10, let's make the above logic specific to LDW. */
|
||
last_insn_was_ldw = ! strcmp ("ldw", CGEN_INSN_NAME (insn.insn));
|
||
|
||
/* The assumption here is that the target of a load is always rt.
|
||
That is true for iq2000 & iq10. */
|
||
delayed_load_register = insn.fields.f_rt;
|
||
}
|
||
|
||
valueT
|
||
md_section_align (segment, size)
|
||
segT segment;
|
||
valueT size;
|
||
{
|
||
int align = bfd_get_section_alignment (stdoutput, segment);
|
||
return ((size + (1 << align) - 1) & (-1 << align));
|
||
}
|
||
|
||
|
||
symbolS *
|
||
md_undefined_symbol (name)
|
||
char * name ATTRIBUTE_UNUSED;
|
||
{
|
||
return 0;
|
||
}
|
||
|
||
/* Interface to relax_segment. */
|
||
|
||
/* Return an initial guess of the length by which a fragment must grow to
|
||
hold a branch to reach its destination.
|
||
Also updates fr_type/fr_subtype as necessary.
|
||
|
||
Called just before doing relaxation.
|
||
Any symbol that is now undefined will not become defined.
|
||
The guess for fr_var is ACTUALLY the growth beyond fr_fix.
|
||
Whatever we do to grow fr_fix or fr_var contributes to our returned value.
|
||
Although it may not be explicit in the frag, pretend fr_var starts with a
|
||
0 value. */
|
||
|
||
int
|
||
md_estimate_size_before_relax (fragP, segment)
|
||
fragS * fragP;
|
||
segT segment ATTRIBUTE_UNUSED;
|
||
{
|
||
int old_fr_fix = fragP->fr_fix;
|
||
|
||
/* The only thing we have to handle here are symbols outside of the
|
||
current segment. They may be undefined or in a different segment in
|
||
which case linker scripts may place them anywhere.
|
||
However, we can't finish the fragment here and emit the reloc as insn
|
||
alignment requirements may move the insn about. */
|
||
|
||
return (fragP->fr_var + fragP->fr_fix - old_fr_fix);
|
||
}
|
||
|
||
/* *fragP has been relaxed to its final size, and now needs to have
|
||
the bytes inside it modified to conform to the new size.
|
||
|
||
Called after relaxation is finished.
|
||
fragP->fr_type == rs_machine_dependent.
|
||
fragP->fr_subtype is the subtype of what the address relaxed to. */
|
||
|
||
void
|
||
md_convert_frag (abfd, sec, fragP)
|
||
bfd * abfd ATTRIBUTE_UNUSED;
|
||
segT sec ATTRIBUTE_UNUSED;
|
||
fragS * fragP ATTRIBUTE_UNUSED;
|
||
{
|
||
}
|
||
|
||
|
||
/* Functions concerning relocs. */
|
||
|
||
long
|
||
md_pcrel_from_section (fixP, sec)
|
||
fixS * fixP;
|
||
segT sec;
|
||
{
|
||
if (fixP->fx_addsy != (symbolS *) NULL
|
||
&& (! S_IS_DEFINED (fixP->fx_addsy)
|
||
|| S_GET_SEGMENT (fixP->fx_addsy) != sec))
|
||
{
|
||
/* The symbol is undefined (or is defined but not in this section).
|
||
Let the linker figure it out. */
|
||
return 0;
|
||
}
|
||
|
||
/* return the address of the delay slot */
|
||
return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
|
||
}
|
||
|
||
/* Return the bfd reloc type for OPERAND of INSN at fixup FIXP.
|
||
Returns BFD_RELOC_NONE if no reloc type can be found.
|
||
*FIXP may be modified if desired. */
|
||
|
||
bfd_reloc_code_real_type
|
||
md_cgen_lookup_reloc (insn, operand, fixP)
|
||
const CGEN_INSN * insn ATTRIBUTE_UNUSED;
|
||
const CGEN_OPERAND * operand;
|
||
fixS * fixP ATTRIBUTE_UNUSED;
|
||
{
|
||
switch (operand->type)
|
||
{
|
||
case IQ2000_OPERAND_OFFSET:
|
||
return BFD_RELOC_16_PCREL_S2;
|
||
case IQ2000_OPERAND_JMPTARG:
|
||
return BFD_RELOC_IQ2000_OFFSET_16;
|
||
case IQ2000_OPERAND_JMPTARGQ10:
|
||
if (iq2000_mach == bfd_mach_iq10)
|
||
return BFD_RELOC_IQ2000_OFFSET_21;
|
||
return BFD_RELOC_NONE;
|
||
case IQ2000_OPERAND_HI16:
|
||
return BFD_RELOC_HI16;
|
||
case IQ2000_OPERAND_LO16:
|
||
return BFD_RELOC_LO16;
|
||
default:
|
||
/* Pacify gcc -Wall. */
|
||
return BFD_RELOC_NONE;
|
||
}
|
||
|
||
return BFD_RELOC_NONE;
|
||
}
|
||
|
||
/* Record a HI16 reloc for later matching with its LO16 cousin. */
|
||
|
||
static void
|
||
iq2000_record_hi16 (reloc_type, fixP, seg)
|
||
int reloc_type;
|
||
fixS * fixP;
|
||
segT seg ATTRIBUTE_UNUSED;
|
||
{
|
||
struct iq2000_hi_fixup * hi_fixup;
|
||
|
||
assert (reloc_type == BFD_RELOC_HI16);
|
||
|
||
hi_fixup = ((struct iq2000_hi_fixup *)
|
||
xmalloc (sizeof (struct iq2000_hi_fixup)));
|
||
hi_fixup->fixp = fixP;
|
||
hi_fixup->seg = now_seg;
|
||
hi_fixup->next = iq2000_hi_fixup_list;
|
||
|
||
iq2000_hi_fixup_list = hi_fixup;
|
||
}
|
||
|
||
/* Called while parsing an instruction to create a fixup.
|
||
We need to check for HI16 relocs and queue them up for later sorting. */
|
||
|
||
fixS *
|
||
iq2000_cgen_record_fixup_exp (frag, where, insn, length, operand, opinfo, exp)
|
||
fragS * frag;
|
||
int where;
|
||
const CGEN_INSN * insn;
|
||
int length;
|
||
const CGEN_OPERAND * operand;
|
||
int opinfo;
|
||
expressionS * exp;
|
||
{
|
||
fixS * fixP = gas_cgen_record_fixup_exp (frag, where, insn, length,
|
||
operand, opinfo, exp);
|
||
|
||
switch (operand->type)
|
||
{
|
||
case IQ2000_OPERAND_HI16 :
|
||
/* If low/high was used, it is recorded in `opinfo'. */
|
||
if (fixP->fx_cgen.opinfo == BFD_RELOC_HI16
|
||
|| fixP->fx_cgen.opinfo == BFD_RELOC_LO16)
|
||
iq2000_record_hi16 (fixP->fx_cgen.opinfo, fixP, now_seg);
|
||
break;
|
||
default : /* avoid -Wall warning */
|
||
break;
|
||
}
|
||
|
||
return fixP;
|
||
}
|
||
|
||
/* Return BFD reloc type from opinfo field in a fixS.
|
||
It's tricky using fx_r_type in iq2000_frob_file because the values
|
||
are BFD_RELOC_UNUSED + operand number. */
|
||
#define FX_OPINFO_R_TYPE(f) ((f)->fx_cgen.opinfo)
|
||
|
||
/* Sort any unmatched HI16 relocs so that they immediately precede
|
||
the corresponding LO16 reloc. This is called before md_apply_fix3 and
|
||
tc_gen_reloc. */
|
||
|
||
void
|
||
iq2000_frob_file ()
|
||
{
|
||
struct iq2000_hi_fixup * l;
|
||
|
||
for (l = iq2000_hi_fixup_list; l != NULL; l = l->next)
|
||
{
|
||
segment_info_type * seginfo;
|
||
int pass;
|
||
|
||
assert (FX_OPINFO_R_TYPE (l->fixp) == BFD_RELOC_HI16
|
||
|| FX_OPINFO_R_TYPE (l->fixp) == BFD_RELOC_LO16);
|
||
|
||
/* Check quickly whether the next fixup happens to be a matching low. */
|
||
if (l->fixp->fx_next != NULL
|
||
&& FX_OPINFO_R_TYPE (l->fixp->fx_next) == BFD_RELOC_LO16
|
||
&& l->fixp->fx_addsy == l->fixp->fx_next->fx_addsy
|
||
&& l->fixp->fx_offset == l->fixp->fx_next->fx_offset)
|
||
continue;
|
||
|
||
/* Look through the fixups for this segment for a matching
|
||
`low'. When we find one, move the high just in front of it.
|
||
We do this in two passes. In the first pass, we try to find
|
||
a unique `low'. In the second pass, we permit multiple
|
||
high's relocs for a single `low'. */
|
||
seginfo = seg_info (l->seg);
|
||
for (pass = 0; pass < 2; pass++)
|
||
{
|
||
fixS * f;
|
||
fixS * prev;
|
||
|
||
prev = NULL;
|
||
for (f = seginfo->fix_root; f != NULL; f = f->fx_next)
|
||
{
|
||
/* Check whether this is a `low' fixup which matches l->fixp. */
|
||
if (FX_OPINFO_R_TYPE (f) == BFD_RELOC_LO16
|
||
&& f->fx_addsy == l->fixp->fx_addsy
|
||
&& f->fx_offset == l->fixp->fx_offset
|
||
&& (pass == 1
|
||
|| prev == NULL
|
||
|| (FX_OPINFO_R_TYPE (prev) != BFD_RELOC_HI16)
|
||
|| prev->fx_addsy != f->fx_addsy
|
||
|| prev->fx_offset != f->fx_offset))
|
||
{
|
||
fixS ** pf;
|
||
|
||
/* Move l->fixp before f. */
|
||
for (pf = &seginfo->fix_root;
|
||
* pf != l->fixp;
|
||
pf = & (* pf)->fx_next)
|
||
assert (* pf != NULL);
|
||
|
||
* pf = l->fixp->fx_next;
|
||
|
||
l->fixp->fx_next = f;
|
||
if (prev == NULL)
|
||
seginfo->fix_root = l->fixp;
|
||
else
|
||
prev->fx_next = l->fixp;
|
||
|
||
break;
|
||
}
|
||
|
||
prev = f;
|
||
}
|
||
|
||
if (f != NULL)
|
||
break;
|
||
|
||
if (pass == 1)
|
||
as_warn_where (l->fixp->fx_file, l->fixp->fx_line,
|
||
_("Unmatched high relocation"));
|
||
}
|
||
}
|
||
}
|
||
|
||
/* See whether we need to force a relocation into the output file. */
|
||
|
||
int
|
||
iq2000_force_relocation (fix)
|
||
fixS * fix;
|
||
{
|
||
if (fix->fx_r_type == BFD_RELOC_VTABLE_INHERIT
|
||
|| fix->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
|
||
return 1;
|
||
|
||
return 0;
|
||
}
|
||
|
||
/* Handle the .set pseudo-op. */
|
||
|
||
static void
|
||
s_iq2000_set (x)
|
||
int x ATTRIBUTE_UNUSED;
|
||
{
|
||
char *name = input_line_pointer, ch;
|
||
char *save_ILP = input_line_pointer;
|
||
|
||
while (!is_end_of_line[(unsigned char) *input_line_pointer])
|
||
input_line_pointer++;
|
||
ch = *input_line_pointer;
|
||
*input_line_pointer = '\0';
|
||
|
||
if (strcmp (name, "reorder") == 0)
|
||
{
|
||
}
|
||
else if (strcmp (name, "noreorder") == 0)
|
||
{
|
||
}
|
||
else if (strcmp (name, "at") == 0)
|
||
{
|
||
}
|
||
else if (strcmp (name, "noat") == 0)
|
||
{
|
||
}
|
||
else if (strcmp (name, "macro") == 0)
|
||
{
|
||
}
|
||
else if (strcmp (name, "nomacro") == 0)
|
||
{
|
||
}
|
||
else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0)
|
||
{
|
||
}
|
||
else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0)
|
||
{
|
||
}
|
||
else if (strcmp (name, "bopt") == 0)
|
||
{
|
||
}
|
||
else if (strcmp (name, "nobopt") == 0)
|
||
{
|
||
}
|
||
else
|
||
{
|
||
/* We'd like to be able to use .set symbol, expn */
|
||
input_line_pointer = save_ILP;
|
||
s_set (0);
|
||
return;
|
||
/*as_warn (_("Tried to set unrecognized symbol: %s\n"), name);*/
|
||
}
|
||
*input_line_pointer = ch;
|
||
demand_empty_rest_of_line ();
|
||
}
|
||
|
||
/* Write a value out to the object file, using the appropriate endianness. */
|
||
|
||
void
|
||
md_number_to_chars (buf, val, n)
|
||
char * buf;
|
||
valueT val;
|
||
int n;
|
||
{
|
||
number_to_chars_bigendian (buf, val, n);
|
||
}
|
||
|
||
void
|
||
md_operand (exp)
|
||
expressionS * exp;
|
||
{
|
||
/* In case of a syntax error, escape back to try next syntax combo. */
|
||
if (exp->X_op == O_absent)
|
||
gas_cgen_md_operand (exp);
|
||
}
|
||
|
||
/* Turn a string in input_line_pointer into a floating point constant
|
||
of type type, and store the appropriate bytes in *litP. The number
|
||
of LITTLENUMS emitted is stored in *sizeP . An error message is
|
||
returned, or NULL on OK. */
|
||
|
||
/* Equal to MAX_PRECISION in atof-ieee.c */
|
||
#define MAX_LITTLENUMS 6
|
||
|
||
char *
|
||
md_atof (type, litP, sizeP)
|
||
char type;
|
||
char *litP;
|
||
int *sizeP;
|
||
{
|
||
int i;
|
||
int prec;
|
||
LITTLENUM_TYPE words [MAX_LITTLENUMS];
|
||
char * t;
|
||
char * atof_ieee ();
|
||
|
||
switch (type)
|
||
{
|
||
case 'f':
|
||
case 'F':
|
||
case 's':
|
||
case 'S':
|
||
prec = 2;
|
||
break;
|
||
|
||
case 'd':
|
||
case 'D':
|
||
case 'r':
|
||
case 'R':
|
||
prec = 4;
|
||
break;
|
||
|
||
/* FIXME: Some targets allow other format chars for bigger sizes here. */
|
||
|
||
default:
|
||
* sizeP = 0;
|
||
return _("Bad call to md_atof()");
|
||
}
|
||
|
||
t = atof_ieee (input_line_pointer, type, words);
|
||
if (t)
|
||
input_line_pointer = t;
|
||
* sizeP = prec * sizeof (LITTLENUM_TYPE);
|
||
|
||
for (i = 0; i < prec; i++)
|
||
{
|
||
md_number_to_chars (litP, (valueT) words[i],
|
||
sizeof (LITTLENUM_TYPE));
|
||
litP += sizeof (LITTLENUM_TYPE);
|
||
}
|
||
|
||
return 0;
|
||
}
|
||
|
||
|
||
bfd_boolean
|
||
iq2000_fix_adjustable (fixP)
|
||
fixS * fixP;
|
||
{
|
||
bfd_reloc_code_real_type reloc_type;
|
||
|
||
if ((int) fixP->fx_r_type >= (int) BFD_RELOC_UNUSED)
|
||
{
|
||
const CGEN_INSN *insn = NULL;
|
||
int opindex = (int) fixP->fx_r_type - (int) BFD_RELOC_UNUSED;
|
||
const CGEN_OPERAND *operand = cgen_operand_lookup_by_num(gas_cgen_cpu_desc, opindex);
|
||
reloc_type = md_cgen_lookup_reloc (insn, operand, fixP);
|
||
}
|
||
else
|
||
reloc_type = fixP->fx_r_type;
|
||
|
||
if (fixP->fx_addsy == NULL)
|
||
return TRUE;
|
||
|
||
/* Prevent all adjustments to global symbols. */
|
||
if (S_IS_EXTERN (fixP->fx_addsy))
|
||
return FALSE;
|
||
|
||
if (S_IS_WEAK (fixP->fx_addsy))
|
||
return FALSE;
|
||
|
||
/* We need the symbol name for the VTABLE entries. */
|
||
if ( reloc_type == BFD_RELOC_VTABLE_INHERIT
|
||
|| reloc_type == BFD_RELOC_VTABLE_ENTRY)
|
||
return FALSE;
|
||
|
||
return TRUE;
|
||
}
|
||
|
||
static void
|
||
s_change_sec (sec)
|
||
int sec;
|
||
{
|
||
|
||
#ifdef OBJ_ELF
|
||
/* The ELF backend needs to know that we are changing sections, so
|
||
that .previous works correctly. We could do something like check
|
||
for a obj_section_change_hook macro, but that might be confusing
|
||
as it would not be appropriate to use it in the section changing
|
||
functions in read.c, since obj-elf.c intercepts those. FIXME:
|
||
This should be cleaner, somehow. */
|
||
obj_elf_section_change_hook ();
|
||
#endif
|
||
|
||
/* iq2000_emit_delays (false); */
|
||
|
||
switch (sec)
|
||
{
|
||
case 't':
|
||
s_text (0);
|
||
break;
|
||
case 'd':
|
||
case 'r':
|
||
s_data (0);
|
||
break;
|
||
}
|
||
}
|
||
|
||
/* The .end directive. */
|
||
|
||
static void
|
||
s_iq2000_end (x)
|
||
int x ATTRIBUTE_UNUSED;
|
||
{
|
||
symbolS *p;
|
||
int maybe_text;
|
||
|
||
if (!is_end_of_line[(unsigned char) *input_line_pointer])
|
||
{
|
||
p = get_symbol ();
|
||
demand_empty_rest_of_line ();
|
||
}
|
||
else
|
||
p = NULL;
|
||
|
||
if (1/*iq2000_mach == bfd_mach_iq2000*/)
|
||
{
|
||
#ifdef BFD_ASSEMBLER
|
||
if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0)
|
||
maybe_text = 1;
|
||
else
|
||
maybe_text = 0;
|
||
#else
|
||
if (now_seg != data_section && now_seg != bss_section)
|
||
maybe_text = 1;
|
||
else
|
||
maybe_text = 0;
|
||
#endif
|
||
|
||
if (!maybe_text)
|
||
as_warn (_(".end not in text section"));
|
||
|
||
if (!cur_proc_ptr)
|
||
{
|
||
as_warn (_(".end directive without a preceding .ent directive."));
|
||
demand_empty_rest_of_line ();
|
||
return;
|
||
}
|
||
|
||
if (p != NULL)
|
||
{
|
||
assert (S_GET_NAME (p));
|
||
if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->isym)))
|
||
as_warn (_(".end symbol does not match .ent symbol."));
|
||
}
|
||
else
|
||
as_warn (_(".end directive missing or unknown symbol"));
|
||
|
||
}
|
||
|
||
cur_proc_ptr = NULL;
|
||
}
|
||
|
||
/* The .aent and .ent directives. */
|
||
|
||
static void
|
||
s_iq2000_ent (aent)
|
||
int aent;
|
||
{
|
||
int number = 0;
|
||
symbolS *symbolP;
|
||
int maybe_text;
|
||
|
||
if (1/*iq2000_mach == bfd_mach_iq2000*/)
|
||
{
|
||
symbolP = get_symbol ();
|
||
if (*input_line_pointer == ',')
|
||
input_line_pointer++;
|
||
SKIP_WHITESPACE ();
|
||
if (ISDIGIT (*input_line_pointer) || *input_line_pointer == '-')
|
||
number = get_number ();
|
||
|
||
#ifdef BFD_ASSEMBLER
|
||
if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0)
|
||
maybe_text = 1;
|
||
else
|
||
maybe_text = 0;
|
||
#else
|
||
if (now_seg != data_section && now_seg != bss_section)
|
||
maybe_text = 1;
|
||
else
|
||
maybe_text = 0;
|
||
#endif
|
||
|
||
if (!maybe_text)
|
||
as_warn (_(".ent or .aent not in text section."));
|
||
|
||
if (!aent && cur_proc_ptr)
|
||
as_warn (_("missing `.end'"));
|
||
|
||
if (!aent)
|
||
{
|
||
cur_proc_ptr = &cur_proc;
|
||
memset (cur_proc_ptr, '\0', sizeof (procS));
|
||
|
||
cur_proc_ptr->isym = symbolP;
|
||
|
||
symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION;
|
||
|
||
numprocs++;
|
||
}
|
||
}
|
||
else
|
||
as_bad (_("unknown pseudo-op: `%s'"), ".ent");
|
||
|
||
demand_empty_rest_of_line ();
|
||
}
|
||
|
||
/* The .frame directive. If the mdebug section is present (IRIX 5 native)
|
||
then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
|
||
s_iq2000_frame is used so that we can set the PDR information correctly.
|
||
We can't use the ecoff routines because they make reference to the ecoff
|
||
symbol table (in the mdebug section). */
|
||
|
||
static void
|
||
s_iq2000_frame (ignore)
|
||
int ignore;
|
||
{
|
||
s_ignore (ignore);
|
||
}
|
||
|
||
/* The .fmask and .mask directives. If the mdebug section is present
|
||
(IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
|
||
embedded targets, s_iq2000_mask is used so that we can set the PDR
|
||
information correctly. We can't use the ecoff routines because they
|
||
make reference to the ecoff symbol table (in the mdebug section). */
|
||
|
||
static void
|
||
s_iq2000_mask (reg_type)
|
||
char reg_type;
|
||
{
|
||
s_ignore (reg_type);
|
||
}
|
||
|
||
static symbolS *
|
||
get_symbol ()
|
||
{
|
||
int c;
|
||
char *name;
|
||
symbolS *p;
|
||
|
||
name = input_line_pointer;
|
||
c = get_symbol_end ();
|
||
p = (symbolS *) symbol_find_or_make (name);
|
||
*input_line_pointer = c;
|
||
return p;
|
||
}
|
||
|
||
static int
|
||
get_number ()
|
||
{
|
||
int negative = 0;
|
||
long val = 0;
|
||
|
||
if (*input_line_pointer == '-')
|
||
{
|
||
++input_line_pointer;
|
||
negative = 1;
|
||
}
|
||
|
||
if (! ISDIGIT (*input_line_pointer))
|
||
as_bad (_("Expected simple number."));
|
||
|
||
if (input_line_pointer[0] == '0')
|
||
{
|
||
if (input_line_pointer[1] == 'x')
|
||
{
|
||
input_line_pointer += 2;
|
||
while (ISXDIGIT (*input_line_pointer))
|
||
{
|
||
val <<= 4;
|
||
val |= hex_value (*input_line_pointer++);
|
||
}
|
||
return negative ? -val : val;
|
||
}
|
||
else
|
||
{
|
||
++input_line_pointer;
|
||
|
||
while (ISDIGIT (*input_line_pointer))
|
||
{
|
||
val <<= 3;
|
||
val |= *input_line_pointer++ - '0';
|
||
}
|
||
return negative ? -val : val;
|
||
}
|
||
}
|
||
|
||
if (! ISDIGIT (*input_line_pointer))
|
||
{
|
||
printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
|
||
*input_line_pointer, *input_line_pointer);
|
||
as_warn (_("Invalid number"));
|
||
return -1;
|
||
}
|
||
|
||
while (ISDIGIT (*input_line_pointer))
|
||
{
|
||
val *= 10;
|
||
val += *input_line_pointer++ - '0';
|
||
}
|
||
|
||
return negative ? -val : val;
|
||
}
|
||
|