495 lines
14 KiB
C
495 lines
14 KiB
C
/* Blackfin Direct Memory Access (DMA) Controller model.
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Copyright (C) 2010-2012 Free Software Foundation, Inc.
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Contributed by Analog Devices, Inc.
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This file is part of simulators.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#include "config.h"
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#include "sim-main.h"
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#include "sim-hw.h"
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#include "devices.h"
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#include "hw-device.h"
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#include "dv-bfin_dma.h"
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#include "dv-bfin_dmac.h"
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struct bfin_dmac
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{
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/* This top portion matches common dv_bfin struct. */
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bu32 base;
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struct hw *dma_master;
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bool acked;
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const char * const *pmap;
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unsigned int pmap_count;
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};
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struct hw *
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bfin_dmac_get_peer (struct hw *dma, bu16 pmap)
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{
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struct hw *ret, *me;
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struct bfin_dmac *dmac;
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char peer[100];
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me = hw_parent (dma);
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dmac = hw_data (me);
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if (pmap & CTYPE)
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{
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/* MDMA channel. */
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unsigned int chan_num = dv_get_bus_num (dma);
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if (chan_num & 1)
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chan_num &= ~1;
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else
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chan_num |= 1;
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sprintf (peer, "%s/bfin_dma@%u", hw_path (me), chan_num);
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}
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else
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{
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unsigned int idx = pmap >> 12;
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if (idx >= dmac->pmap_count)
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hw_abort (me, "Invalid DMA peripheral_map %#x", pmap);
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else
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sprintf (peer, "/core/bfin_%s", dmac->pmap[idx]);
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}
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ret = hw_tree_find_device (me, peer);
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if (!ret)
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hw_abort (me, "Unable to locate peer for %s (pmap:%#x %s)",
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hw_name (dma), pmap, peer);
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return ret;
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}
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bu16
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bfin_dmac_default_pmap (struct hw *dma)
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{
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unsigned int chan_num = dv_get_bus_num (dma);
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if (chan_num < BFIN_DMAC_MDMA_BASE)
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return (chan_num % 12) << 12;
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else
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return CTYPE; /* MDMA */
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}
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static const char * const bfin_dmac_50x_pmap[] =
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{
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"ppi@0", "rsi", "sport@0", "sport@0", "sport@1", "sport@1",
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"spi@0", "spi@1", "uart2@0", "uart2@0", "uart2@1", "uart2@1",
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};
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/* XXX: Need to figure out how to handle portmuxed DMA channels. */
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static const struct hw_port_descriptor bfin_dmac_50x_ports[] =
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{
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{ "ppi@0", 0, 0, input_port, },
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{ "rsi", 1, 0, input_port, },
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{ "sport@0_rx", 2, 0, input_port, },
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{ "sport@0_tx", 3, 0, input_port, },
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{ "sport@1_tx", 4, 0, input_port, },
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{ "sport@1_rx", 5, 0, input_port, },
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{ "spi@0", 6, 0, input_port, },
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{ "spi@1", 7, 0, input_port, },
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{ "uart2@0_rx", 8, 0, input_port, },
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{ "uart2@0_tx", 9, 0, input_port, },
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{ "uart2@1_rx", 10, 0, input_port, },
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{ "uart2@1_tx", 11, 0, input_port, },
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{ NULL, 0, 0, 0, },
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};
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static const char * const bfin_dmac_51x_pmap[] =
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{
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"ppi@0", "emac", "emac", "sport@0", "sport@0", "sport@1",
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"sport@1", "spi@0", "uart@0", "uart@0", "uart@1", "uart@1",
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};
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/* XXX: Need to figure out how to handle portmuxed DMA channels. */
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static const struct hw_port_descriptor bfin_dmac_51x_ports[] =
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{
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{ "ppi@0", 0, 0, input_port, },
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{ "emac_rx", 1, 0, input_port, },
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{ "emac_tx", 2, 0, input_port, },
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{ "sport@0_rx", 3, 0, input_port, },
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{ "sport@0_tx", 4, 0, input_port, },
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/*{ "rsi", 4, 0, input_port, },*/
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{ "sport@1_tx", 5, 0, input_port, },
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/*{ "spi@1", 5, 0, input_port, },*/
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{ "sport@1_rx", 6, 0, input_port, },
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{ "spi@0", 7, 0, input_port, },
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{ "uart@0_rx", 8, 0, input_port, },
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{ "uart@0_tx", 9, 0, input_port, },
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{ "uart@1_rx", 10, 0, input_port, },
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{ "uart@1_tx", 11, 0, input_port, },
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{ NULL, 0, 0, 0, },
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};
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static const char * const bfin_dmac_52x_pmap[] =
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{
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"ppi@0", "emac", "emac", "sport@0", "sport@0", "sport@1",
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"sport@1", "spi", "uart@0", "uart@0", "uart@1", "uart@1",
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};
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/* XXX: Need to figure out how to handle portmuxed DMA channels
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like PPI/NFC here which share DMA0. */
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static const struct hw_port_descriptor bfin_dmac_52x_ports[] =
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{
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{ "ppi@0", 0, 0, input_port, },
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/*{ "nfc", 0, 0, input_port, },*/
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{ "emac_rx", 1, 0, input_port, },
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/*{ "hostdp", 1, 0, input_port, },*/
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{ "emac_tx", 2, 0, input_port, },
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/*{ "nfc", 2, 0, input_port, },*/
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{ "sport@0_tx", 3, 0, input_port, },
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{ "sport@0_rx", 4, 0, input_port, },
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{ "sport@1_tx", 5, 0, input_port, },
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{ "sport@1_rx", 6, 0, input_port, },
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{ "spi", 7, 0, input_port, },
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{ "uart@0_tx", 8, 0, input_port, },
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{ "uart@0_rx", 9, 0, input_port, },
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{ "uart@1_tx", 10, 0, input_port, },
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{ "uart@1_rx", 11, 0, input_port, },
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{ NULL, 0, 0, 0, },
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};
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static const char * const bfin_dmac_533_pmap[] =
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{
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"ppi@0", "sport@0", "sport@0", "sport@1", "sport@1", "spi",
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"uart@0", "uart@0",
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};
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static const struct hw_port_descriptor bfin_dmac_533_ports[] =
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{
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{ "ppi@0", 0, 0, input_port, },
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{ "sport@0_tx", 1, 0, input_port, },
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{ "sport@0_rx", 2, 0, input_port, },
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{ "sport@1_tx", 3, 0, input_port, },
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{ "sport@1_rx", 4, 0, input_port, },
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{ "spi", 5, 0, input_port, },
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{ "uart@0_tx", 6, 0, input_port, },
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{ "uart@0_rx", 7, 0, input_port, },
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{ NULL, 0, 0, 0, },
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};
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static const char * const bfin_dmac_537_pmap[] =
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{
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"ppi@0", "emac", "emac", "sport@0", "sport@0", "sport@1",
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"sport@1", "spi", "uart@0", "uart@0", "uart@1", "uart@1",
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};
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static const struct hw_port_descriptor bfin_dmac_537_ports[] =
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{
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{ "ppi@0", 0, 0, input_port, },
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{ "emac_rx", 1, 0, input_port, },
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{ "emac_tx", 2, 0, input_port, },
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{ "sport@0_tx", 3, 0, input_port, },
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{ "sport@0_rx", 4, 0, input_port, },
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{ "sport@1_tx", 5, 0, input_port, },
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{ "sport@1_rx", 6, 0, input_port, },
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{ "spi", 7, 0, input_port, },
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{ "uart@0_tx", 8, 0, input_port, },
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{ "uart@0_rx", 9, 0, input_port, },
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{ "uart@1_tx", 10, 0, input_port, },
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{ "uart@1_rx", 11, 0, input_port, },
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{ NULL, 0, 0, 0, },
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};
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static const char * const bfin_dmac0_538_pmap[] =
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{
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"ppi@0", "sport@0", "sport@0", "sport@1", "sport@1", "spi@0",
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"uart@0", "uart@0",
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};
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static const struct hw_port_descriptor bfin_dmac0_538_ports[] =
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{
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{ "ppi@0", 0, 0, input_port, },
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{ "sport@0_rx", 1, 0, input_port, },
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{ "sport@0_tx", 2, 0, input_port, },
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{ "sport@1_rx", 3, 0, input_port, },
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{ "sport@1_tx", 4, 0, input_port, },
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{ "spi@0", 5, 0, input_port, },
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{ "uart@0_rx", 6, 0, input_port, },
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{ "uart@0_tx", 7, 0, input_port, },
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{ NULL, 0, 0, 0, },
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};
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static const char * const bfin_dmac1_538_pmap[] =
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{
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"sport@2", "sport@2", "sport@3", "sport@3", NULL, NULL,
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"spi@1", "spi@2", "uart@1", "uart@1", "uart@2", "uart@2",
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};
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static const struct hw_port_descriptor bfin_dmac1_538_ports[] =
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{
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{ "sport@2_rx", 0, 0, input_port, },
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{ "sport@2_tx", 1, 0, input_port, },
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{ "sport@3_rx", 2, 0, input_port, },
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{ "sport@3_tx", 3, 0, input_port, },
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{ "spi@1", 6, 0, input_port, },
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{ "spi@2", 7, 0, input_port, },
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{ "uart@1_rx", 8, 0, input_port, },
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{ "uart@1_tx", 9, 0, input_port, },
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{ "uart@2_rx", 10, 0, input_port, },
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{ "uart@2_tx", 11, 0, input_port, },
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{ NULL, 0, 0, 0, },
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};
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static const char * const bfin_dmac0_54x_pmap[] =
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{
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"sport@0", "sport@0", "sport@1", "sport@1", "spi@0", "spi@1",
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"uart2@0", "uart2@0", "uart2@1", "uart2@1", "atapi", "atapi",
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};
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static const struct hw_port_descriptor bfin_dmac0_54x_ports[] =
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{
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{ "sport@0_rx", 0, 0, input_port, },
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{ "sport@0_tx", 1, 0, input_port, },
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{ "sport@1_rx", 2, 0, input_port, },
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{ "sport@1_tx", 3, 0, input_port, },
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{ "spi@0", 4, 0, input_port, },
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{ "spi@1", 5, 0, input_port, },
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{ "uart2@0_rx", 6, 0, input_port, },
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{ "uart2@0_tx", 7, 0, input_port, },
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{ "uart2@1_rx", 8, 0, input_port, },
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{ "uart2@1_tx", 9, 0, input_port, },
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{ "atapi", 10, 0, input_port, },
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{ "atapi", 11, 0, input_port, },
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{ NULL, 0, 0, 0, },
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};
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static const char * const bfin_dmac1_54x_pmap[] =
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{
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"eppi@0", "eppi@1", "eppi@2", "pixc", "pixc", "pixc",
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"sport@2", "sport@2", "sport@3", "sport@3", "sdh",
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"spi@2", "uart2@2", "uart2@2", "uart2@3", "uart2@3",
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};
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static const struct hw_port_descriptor bfin_dmac1_54x_ports[] =
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{
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{ "eppi@0", 0, 0, input_port, },
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{ "eppi@1", 1, 0, input_port, },
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{ "eppi@2", 2, 0, input_port, },
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{ "pixc", 3, 0, input_port, },
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{ "pixc", 4, 0, input_port, },
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{ "pixc", 5, 0, input_port, },
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{ "sport@2_rx", 6, 0, input_port, },
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{ "sport@2_tx", 7, 0, input_port, },
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{ "sport@3_rx", 8, 0, input_port, },
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{ "sport@3_tx", 9, 0, input_port, },
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{ "sdh", 10, 0, input_port, },
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/*{ "nfc", 10, 0, input_port, },*/
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{ "spi@2", 11, 0, input_port, },
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{ "uart2@2_rx", 12, 0, input_port, },
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{ "uart2@2_tx", 13, 0, input_port, },
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{ "uart2@3_rx", 14, 0, input_port, },
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{ "uart2@3_tx", 15, 0, input_port, },
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{ NULL, 0, 0, 0, },
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};
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static const char * const bfin_dmac0_561_pmap[] =
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{
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"sport@0", "sport@0", "sport@1", "sport@1", "spi", "uart@0", "uart@0",
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};
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static const struct hw_port_descriptor bfin_dmac0_561_ports[] =
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{
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{ "sport@0_rx", 0, 0, input_port, },
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{ "sport@0_tx", 1, 0, input_port, },
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{ "sport@1_rx", 2, 0, input_port, },
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{ "sport@1_tx", 3, 0, input_port, },
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{ "spi@0", 4, 0, input_port, },
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{ "uart@0_rx", 5, 0, input_port, },
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{ "uart@0_tx", 6, 0, input_port, },
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{ NULL, 0, 0, 0, },
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};
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static const char * const bfin_dmac1_561_pmap[] =
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{
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"ppi@0", "ppi@1",
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};
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static const struct hw_port_descriptor bfin_dmac1_561_ports[] =
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{
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{ "ppi@0", 0, 0, input_port, },
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{ "ppi@1", 1, 0, input_port, },
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{ NULL, 0, 0, 0, },
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};
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static const char * const bfin_dmac_59x_pmap[] =
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{
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"ppi@0", "sport@0", "sport@0", "sport@1", "sport@1", "spi@0",
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"spi@1", "uart@0", "uart@0",
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};
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static const struct hw_port_descriptor bfin_dmac_59x_ports[] =
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{
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{ "ppi@0", 0, 0, input_port, },
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{ "sport@0_tx", 1, 0, input_port, },
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{ "sport@0_rx", 2, 0, input_port, },
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{ "sport@1_tx", 3, 0, input_port, },
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{ "sport@1_rx", 4, 0, input_port, },
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{ "spi@0", 5, 0, input_port, },
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{ "spi@1", 6, 0, input_port, },
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{ "uart@0_rx", 7, 0, input_port, },
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{ "uart@0_tx", 8, 0, input_port, },
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{ NULL, 0, 0, 0, },
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};
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static void
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bfin_dmac_port_event (struct hw *me, int my_port, struct hw *source,
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int source_port, int level)
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{
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SIM_DESC sd = hw_system (me);
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struct bfin_dmac *dmac = hw_data (me);
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struct hw *dma = hw_child (me);
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while (dma)
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{
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bu16 pmap;
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sim_hw_io_read_buffer (sd, dma, &pmap, 0, 0x2c, sizeof (pmap));
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pmap >>= 12;
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if (pmap == my_port)
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break;
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dma = hw_sibling (dma);
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}
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if (!dma)
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hw_abort (me, "no valid dma mapping found for %s", dmac->pmap[my_port]);
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/* Have the DMA channel raise its interrupt to the SIC. */
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hw_port_event (dma, 0, 1);
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}
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static void
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bfin_dmac_finish (struct hw *me)
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{
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struct bfin_dmac *dmac;
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unsigned int dmac_num = dv_get_bus_num (me);
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dmac = HW_ZALLOC (me, struct bfin_dmac);
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set_hw_data (me, dmac);
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set_hw_port_event (me, bfin_dmac_port_event);
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/* Initialize the DMA Controller. */
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if (hw_find_property (me, "type") == NULL)
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hw_abort (me, "Missing \"type\" property");
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switch (hw_find_integer_property (me, "type"))
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{
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case 500 ... 509:
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if (dmac_num != 0)
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hw_abort (me, "this Blackfin only has a DMAC0");
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dmac->pmap = bfin_dmac_50x_pmap;
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dmac->pmap_count = ARRAY_SIZE (bfin_dmac_50x_pmap);
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set_hw_ports (me, bfin_dmac_50x_ports);
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break;
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case 510 ... 519:
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if (dmac_num != 0)
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hw_abort (me, "this Blackfin only has a DMAC0");
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dmac->pmap = bfin_dmac_51x_pmap;
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dmac->pmap_count = ARRAY_SIZE (bfin_dmac_51x_pmap);
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set_hw_ports (me, bfin_dmac_51x_ports);
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break;
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case 522 ... 527:
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if (dmac_num != 0)
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hw_abort (me, "this Blackfin only has a DMAC0");
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dmac->pmap = bfin_dmac_52x_pmap;
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dmac->pmap_count = ARRAY_SIZE (bfin_dmac_52x_pmap);
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set_hw_ports (me, bfin_dmac_52x_ports);
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break;
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case 531 ... 533:
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if (dmac_num != 0)
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hw_abort (me, "this Blackfin only has a DMAC0");
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dmac->pmap = bfin_dmac_533_pmap;
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dmac->pmap_count = ARRAY_SIZE (bfin_dmac_533_pmap);
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set_hw_ports (me, bfin_dmac_533_ports);
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break;
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case 534:
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case 536:
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case 537:
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if (dmac_num != 0)
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hw_abort (me, "this Blackfin only has a DMAC0");
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dmac->pmap = bfin_dmac_537_pmap;
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dmac->pmap_count = ARRAY_SIZE (bfin_dmac_537_pmap);
|
|
set_hw_ports (me, bfin_dmac_537_ports);
|
|
break;
|
|
case 538 ... 539:
|
|
switch (dmac_num)
|
|
{
|
|
case 0:
|
|
dmac->pmap = bfin_dmac0_538_pmap;
|
|
dmac->pmap_count = ARRAY_SIZE (bfin_dmac0_538_pmap);
|
|
set_hw_ports (me, bfin_dmac0_538_ports);
|
|
break;
|
|
case 1:
|
|
dmac->pmap = bfin_dmac1_538_pmap;
|
|
dmac->pmap_count = ARRAY_SIZE (bfin_dmac1_538_pmap);
|
|
set_hw_ports (me, bfin_dmac1_538_ports);
|
|
break;
|
|
default:
|
|
hw_abort (me, "this Blackfin only has a DMAC0 & DMAC1");
|
|
}
|
|
break;
|
|
case 540 ... 549:
|
|
switch (dmac_num)
|
|
{
|
|
case 0:
|
|
dmac->pmap = bfin_dmac0_54x_pmap;
|
|
dmac->pmap_count = ARRAY_SIZE (bfin_dmac0_54x_pmap);
|
|
set_hw_ports (me, bfin_dmac0_54x_ports);
|
|
break;
|
|
case 1:
|
|
dmac->pmap = bfin_dmac1_54x_pmap;
|
|
dmac->pmap_count = ARRAY_SIZE (bfin_dmac1_54x_pmap);
|
|
set_hw_ports (me, bfin_dmac1_54x_ports);
|
|
break;
|
|
default:
|
|
hw_abort (me, "this Blackfin only has a DMAC0 & DMAC1");
|
|
}
|
|
break;
|
|
case 561:
|
|
switch (dmac_num)
|
|
{
|
|
case 0:
|
|
dmac->pmap = bfin_dmac0_561_pmap;
|
|
dmac->pmap_count = ARRAY_SIZE (bfin_dmac0_561_pmap);
|
|
set_hw_ports (me, bfin_dmac0_561_ports);
|
|
break;
|
|
case 1:
|
|
dmac->pmap = bfin_dmac1_561_pmap;
|
|
dmac->pmap_count = ARRAY_SIZE (bfin_dmac1_561_pmap);
|
|
set_hw_ports (me, bfin_dmac1_561_ports);
|
|
break;
|
|
default:
|
|
hw_abort (me, "this Blackfin only has a DMAC0 & DMAC1");
|
|
}
|
|
break;
|
|
case 590 ... 599:
|
|
if (dmac_num != 0)
|
|
hw_abort (me, "this Blackfin only has a DMAC0");
|
|
dmac->pmap = bfin_dmac_59x_pmap;
|
|
dmac->pmap_count = ARRAY_SIZE (bfin_dmac_59x_pmap);
|
|
set_hw_ports (me, bfin_dmac_59x_ports);
|
|
break;
|
|
default:
|
|
hw_abort (me, "no support for DMAC on this Blackfin model yet");
|
|
}
|
|
}
|
|
|
|
const struct hw_descriptor dv_bfin_dmac_descriptor[] =
|
|
{
|
|
{"bfin_dmac", bfin_dmac_finish,},
|
|
{NULL, NULL},
|
|
};
|