607 lines
17 KiB
C
607 lines
17 KiB
C
/* Blackfin Ethernet Media Access Controller (EMAC) model.
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Copyright (C) 2010-2011 Free Software Foundation, Inc.
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Contributed by Analog Devices, Inc.
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This file is part of simulators.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#include "config.h"
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#include <errno.h>
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#include <fcntl.h>
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#include <unistd.h>
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#ifdef HAVE_SYS_IOCTL_H
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#include <sys/ioctl.h>
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#endif
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#ifdef HAVE_NET_IF_H
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#include <net/if.h>
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#endif
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#ifdef HAVE_LINUX_IF_TUN_H
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#include <linux/if_tun.h>
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#endif
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#ifdef HAVE_LINUX_IF_TUN_H
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# define WITH_TUN 1
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#else
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# define WITH_TUN 0
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#endif
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#include "sim-main.h"
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#include "sim-hw.h"
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#include "devices.h"
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#include "dv-bfin_emac.h"
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/* XXX: This doesn't support partial DMA transfers. */
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/* XXX: The TUN pieces should be pushed to the PHY so that we work with
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multiple "networks" and the PHY takes care of it. */
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struct bfin_emac
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{
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/* This top portion matches common dv_bfin struct. */
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bu32 base;
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struct hw *dma_master;
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bool acked;
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int tap;
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#if WITH_TUN
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struct ifreq ifr;
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#endif
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bu32 rx_crc;
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/* Order after here is important -- matches hardware MMR layout. */
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bu32 opmode, addrlo, addrhi, hashlo, hashhi, staadd, stadat, flc, vlan1, vlan2;
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bu32 _pad0;
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bu32 wkup_ctl, wkup_ffmsk0, wkup_ffmsk1, wkup_ffmsk2, wkup_ffmsk3;
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bu32 wkup_ffcmd, wkup_ffoff, wkup_ffcrc0, wkup_ffcrc1;
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bu32 _pad1[4];
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bu32 sysctl, systat, rx_stat, rx_stky, rx_irqe, tx_stat, tx_stky, tx_irqe;
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bu32 mmc_ctl, mmc_rirqs, mmc_rirqe, mmc_tirqs, mmc_tirqe;
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bu32 _pad2[3];
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bu16 BFIN_MMR_16(ptp_ctl);
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bu16 BFIN_MMR_16(ptp_ie);
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bu16 BFIN_MMR_16(ptp_istat);
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bu32 ptp_foff, ptp_fv1, ptp_fv2, ptp_fv3, ptp_addend, ptp_accr, ptp_offset;
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bu32 ptp_timelo, ptp_timehi, ptp_rxsnaplo, ptp_rxsnaphi, ptp_txsnaplo;
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bu32 ptp_txsnaphi, ptp_alarmlo, ptp_alarmhi, ptp_id_off, ptp_id_snap;
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bu32 ptp_pps_startlo, ptp_pps_starthi, ptp_pps_period;
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bu32 _pad3[1];
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bu32 rxc_ok, rxc_fcs, rxc_lign, rxc_octet, rxc_dmaovf, rxc_unicst, rxc_multi;
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bu32 rxc_broad, rxc_lnerri, rxc_lnerro, rxc_long, rxc_macctl, rxc_opcode;
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bu32 rxc_pause, rxc_allfrm, rxc_alloct, rxc_typed, rxc_short, rxc_eq64;
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bu32 rxc_lt128, rxc_lt256, rxc_lt512, rxc_lt1024, rxc_ge1024;
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bu32 _pad4[8];
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bu32 txc_ok, txc_1col, txc_gt1col, txc_octet, txc_defer, txc_latecl;
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bu32 txc_xs_col, txc_dmaund, txc_crserr, txc_unicst, txc_multi, txc_broad;
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bu32 txc_xs_dfr, txc_macctl, txc_allfrm, txc_alloct, txc_eq64, txc_lt128;
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bu32 txc_lt256, txc_lt512, txc_lt1024, txc_ge1024, txc_abort;
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};
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#define mmr_base() offsetof(struct bfin_emac, opmode)
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#define mmr_offset(mmr) (offsetof(struct bfin_emac, mmr) - mmr_base())
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#define mmr_idx(mmr) (mmr_offset (mmr) / 4)
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static const char * const mmr_names[BFIN_MMR_EMAC_SIZE / 4] =
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{
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"EMAC_OPMODE", "EMAC_ADDRLO", "EMAC_ADDRHI", "EMAC_HASHLO", "EMAC_HASHHI",
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"EMAC_STAADD", "EMAC_STADAT", "EMAC_FLC", "EMAC_VLAN1", "EMAC_VLAN2", NULL,
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"EMAC_WKUP_CTL", "EMAC_WKUP_FFMSK0", "EMAC_WKUP_FFMSK1", "EMAC_WKUP_FFMSK2",
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"EMAC_WKUP_FFMSK3", "EMAC_WKUP_FFCMD", "EMAC_WKUP_FFOFF", "EMAC_WKUP_FFCRC0",
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"EMAC_WKUP_FFCRC1", [mmr_idx (sysctl)] = "EMAC_SYSCTL", "EMAC_SYSTAT",
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"EMAC_RX_STAT", "EMAC_RX_STKY", "EMAC_RX_IRQE", "EMAC_TX_STAT",
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"EMAC_TX_STKY", "EMAC_TX_IRQE", "EMAC_MMC_CTL", "EMAC_MMC_RIRQS",
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"EMAC_MMC_RIRQE", "EMAC_MMC_TIRQS", "EMAC_MMC_TIRQE",
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[mmr_idx (ptp_ctl)] = "EMAC_PTP_CTL", "EMAC_PTP_IE", "EMAC_PTP_ISTAT",
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"EMAC_PTP_FOFF", "EMAC_PTP_FV1", "EMAC_PTP_FV2", "EMAC_PTP_FV3",
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"EMAC_PTP_ADDEND", "EMAC_PTP_ACCR", "EMAC_PTP_OFFSET", "EMAC_PTP_TIMELO",
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"EMAC_PTP_TIMEHI", "EMAC_PTP_RXSNAPLO", "EMAC_PTP_RXSNAPHI",
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"EMAC_PTP_TXSNAPLO", "EMAC_PTP_TXSNAPHI", "EMAC_PTP_ALARMLO",
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"EMAC_PTP_ALARMHI", "EMAC_PTP_ID_OFF", "EMAC_PTP_ID_SNAP",
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"EMAC_PTP_PPS_STARTLO", "EMAC_PTP_PPS_STARTHI", "EMAC_PTP_PPS_PERIOD",
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[mmr_idx (rxc_ok)] = "EMAC_RXC_OK", "EMAC_RXC_FCS", "EMAC_RXC_LIGN",
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"EMAC_RXC_OCTET", "EMAC_RXC_DMAOVF", "EMAC_RXC_UNICST", "EMAC_RXC_MULTI",
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"EMAC_RXC_BROAD", "EMAC_RXC_LNERRI", "EMAC_RXC_LNERRO", "EMAC_RXC_LONG",
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"EMAC_RXC_MACCTL", "EMAC_RXC_OPCODE", "EMAC_RXC_PAUSE", "EMAC_RXC_ALLFRM",
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"EMAC_RXC_ALLOCT", "EMAC_RXC_TYPED", "EMAC_RXC_SHORT", "EMAC_RXC_EQ64",
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"EMAC_RXC_LT128", "EMAC_RXC_LT256", "EMAC_RXC_LT512", "EMAC_RXC_LT1024",
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"EMAC_RXC_GE1024",
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[mmr_idx (txc_ok)] = "EMAC_TXC_OK", "EMAC_TXC_1COL", "EMAC_TXC_GT1COL",
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"EMAC_TXC_OCTET", "EMAC_TXC_DEFER", "EMAC_TXC_LATECL", "EMAC_TXC_XS_COL",
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"EMAC_TXC_DMAUND", "EMAC_TXC_CRSERR", "EMAC_TXC_UNICST", "EMAC_TXC_MULTI",
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"EMAC_TXC_BROAD", "EMAC_TXC_XS_DFR", "EMAC_TXC_MACCTL", "EMAC_TXC_ALLFRM",
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"EMAC_TXC_ALLOCT", "EMAC_TXC_EQ64", "EMAC_TXC_LT128", "EMAC_TXC_LT256",
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"EMAC_TXC_LT512", "EMAC_TXC_LT1024", "EMAC_TXC_GE1024", "EMAC_TXC_ABORT",
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};
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#define mmr_name(off) (mmr_names[(off) / 4] ? : "<INV>")
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static struct hw *
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mii_find_phy (struct hw *me, bu8 addr)
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{
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struct hw *phy = hw_child (me);
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while (phy && --addr)
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phy = hw_sibling (phy);
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return phy;
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}
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static void
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mii_write (struct hw *me)
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{
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SIM_DESC sd = hw_system (me);
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struct bfin_emac *emac = hw_data (me);
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struct hw *phy;
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bu8 addr = PHYAD (emac->staadd);
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bu8 reg = REGAD (emac->staadd);
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bu16 data = emac->stadat;
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phy = mii_find_phy (me, addr);
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if (!phy)
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return;
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sim_hw_io_write_buffer (sd, phy, &data, 1, reg, 2);
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}
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static void
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mii_read (struct hw *me)
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{
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SIM_DESC sd = hw_system (me);
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struct bfin_emac *emac = hw_data (me);
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struct hw *phy;
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bu8 addr = PHYAD (emac->staadd);
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bu8 reg = REGAD (emac->staadd);
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bu16 data;
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phy = mii_find_phy (me, addr);
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if (!phy || sim_hw_io_read_buffer (sd, phy, &data, 1, reg, 2) != 2)
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data = 0xffff;
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emac->stadat = data;
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}
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static unsigned
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bfin_emac_io_write_buffer (struct hw *me, const void *source,
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int space, address_word addr, unsigned nr_bytes)
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{
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struct bfin_emac *emac = hw_data (me);
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bu32 mmr_off;
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bu32 value;
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bu32 *valuep;
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/* XXX: 16bit accesses are allowed ... */
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dv_bfin_mmr_require_32 (me, addr, nr_bytes, true);
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value = dv_load_4 (source);
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mmr_off = addr - emac->base;
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valuep = (void *)((unsigned long)emac + mmr_base() + mmr_off);
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HW_TRACE_WRITE ();
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switch (mmr_off)
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{
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case mmr_offset(hashlo):
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case mmr_offset(hashhi):
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case mmr_offset(stadat):
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case mmr_offset(flc):
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case mmr_offset(vlan1):
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case mmr_offset(vlan2):
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case mmr_offset(wkup_ffmsk0):
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case mmr_offset(wkup_ffmsk1):
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case mmr_offset(wkup_ffmsk2):
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case mmr_offset(wkup_ffmsk3):
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case mmr_offset(wkup_ffcmd):
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case mmr_offset(wkup_ffoff):
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case mmr_offset(wkup_ffcrc0):
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case mmr_offset(wkup_ffcrc1):
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case mmr_offset(sysctl):
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case mmr_offset(rx_irqe):
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case mmr_offset(tx_irqe):
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case mmr_offset(mmc_rirqe):
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case mmr_offset(mmc_tirqe):
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*valuep = value;
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break;
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case mmr_offset(opmode):
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if (!(*valuep & RE) && (value & RE))
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emac->rx_stat &= ~RX_COMP;
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if (!(*valuep & TE) && (value & TE))
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emac->tx_stat &= ~TX_COMP;
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*valuep = value;
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break;
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case mmr_offset(addrlo):
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case mmr_offset(addrhi):
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*valuep = value;
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break;
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case mmr_offset(wkup_ctl):
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dv_w1c_4_partial (valuep, value, 0xf20);
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break;
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case mmr_offset(systat):
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dv_w1c_4 (valuep, value, 0xe1);
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break;
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case mmr_offset(staadd):
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*valuep = value | STABUSY;
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if (value & STAOP)
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mii_write (me);
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else
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mii_read (me);
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*valuep &= ~STABUSY;
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break;
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case mmr_offset(rx_stat):
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case mmr_offset(tx_stat):
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/* Discard writes to these. */
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break;
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case mmr_offset(rx_stky):
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case mmr_offset(tx_stky):
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case mmr_offset(mmc_rirqs):
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case mmr_offset(mmc_tirqs):
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dv_w1c_4 (valuep, value, -1);
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break;
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case mmr_offset(mmc_ctl):
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/* Writing to bit 0 clears all counters. */
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*valuep = value & ~1;
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if (value & 1)
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{
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memset (&emac->rxc_ok, 0, mmr_offset (rxc_ge1024) - mmr_offset (rxc_ok) + 4);
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memset (&emac->txc_ok, 0, mmr_offset (txc_abort) - mmr_offset (txc_ok) + 4);
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}
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break;
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case mmr_offset(rxc_ok) ... mmr_offset(rxc_ge1024):
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case mmr_offset(txc_ok) ... mmr_offset(txc_abort):
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/* XXX: Are these supposed to be read-only ? */
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*valuep = value;
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break;
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case mmr_offset(ptp_ctl) ... mmr_offset(ptp_pps_period):
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/* XXX: Only on some models; ignore for now. */
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break;
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default:
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dv_bfin_mmr_invalid (me, addr, nr_bytes, true);
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break;
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}
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return nr_bytes;
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}
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static unsigned
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bfin_emac_io_read_buffer (struct hw *me, void *dest,
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int space, address_word addr, unsigned nr_bytes)
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{
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struct bfin_emac *emac = hw_data (me);
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bu32 mmr_off;
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bu32 *valuep;
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/* XXX: 16bit accesses are allowed ... */
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dv_bfin_mmr_require_32 (me, addr, nr_bytes, false);
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mmr_off = addr - emac->base;
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valuep = (void *)((unsigned long)emac + mmr_base() + mmr_off);
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HW_TRACE_READ ();
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switch (mmr_off)
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{
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case mmr_offset(opmode):
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case mmr_offset(addrlo):
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case mmr_offset(addrhi):
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case mmr_offset(hashlo):
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case mmr_offset(hashhi):
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case mmr_offset(staadd):
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case mmr_offset(stadat):
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case mmr_offset(flc):
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case mmr_offset(vlan1):
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case mmr_offset(vlan2):
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case mmr_offset(wkup_ctl):
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case mmr_offset(wkup_ffmsk0):
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case mmr_offset(wkup_ffmsk1):
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case mmr_offset(wkup_ffmsk2):
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case mmr_offset(wkup_ffmsk3):
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case mmr_offset(wkup_ffcmd):
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case mmr_offset(wkup_ffoff):
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case mmr_offset(wkup_ffcrc0):
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case mmr_offset(wkup_ffcrc1):
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case mmr_offset(sysctl):
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case mmr_offset(systat):
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case mmr_offset(rx_stat):
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case mmr_offset(rx_stky):
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case mmr_offset(rx_irqe):
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case mmr_offset(tx_stat):
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case mmr_offset(tx_stky):
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case mmr_offset(tx_irqe):
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case mmr_offset(mmc_rirqs):
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case mmr_offset(mmc_rirqe):
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case mmr_offset(mmc_tirqs):
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case mmr_offset(mmc_tirqe):
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case mmr_offset(mmc_ctl):
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case mmr_offset(rxc_ok) ... mmr_offset(rxc_ge1024):
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case mmr_offset(txc_ok) ... mmr_offset(txc_abort):
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dv_store_4 (dest, *valuep);
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break;
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case mmr_offset(ptp_ctl) ... mmr_offset(ptp_pps_period):
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/* XXX: Only on some models; ignore for now. */
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break;
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default:
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dv_bfin_mmr_invalid (me, addr, nr_bytes, false);
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break;
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}
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return nr_bytes;
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}
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static void
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attach_bfin_emac_regs (struct hw *me, struct bfin_emac *emac)
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{
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address_word attach_address;
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int attach_space;
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unsigned attach_size;
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reg_property_spec reg;
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if (hw_find_property (me, "reg") == NULL)
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hw_abort (me, "Missing \"reg\" property");
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if (!hw_find_reg_array_property (me, "reg", 0, ®))
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hw_abort (me, "\"reg\" property must contain three addr/size entries");
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hw_unit_address_to_attach_address (hw_parent (me),
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®.address,
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&attach_space, &attach_address, me);
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hw_unit_size_to_attach_size (hw_parent (me), ®.size, &attach_size, me);
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if (attach_size != BFIN_MMR_EMAC_SIZE)
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hw_abort (me, "\"reg\" size must be %#x", BFIN_MMR_EMAC_SIZE);
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hw_attach_address (hw_parent (me),
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0, attach_space, attach_address, attach_size, me);
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emac->base = attach_address;
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}
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static struct dv_bfin *dma_tx;
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static unsigned
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bfin_emac_dma_read_buffer (struct hw *me, void *dest, int space,
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unsigned_word addr, unsigned nr_bytes)
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{
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struct bfin_emac *emac = hw_data (me);
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struct dv_bfin *dma = hw_data (emac->dma_master);
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unsigned char *data = dest;
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static bool flop; /* XXX: This sucks. */
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bu16 len;
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ssize_t ret;
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HW_TRACE_DMA_READ ();
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if (dma_tx == dma)
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{
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/* Handle the TX turn around and write the status. */
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emac->tx_stat |= TX_OK;
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emac->tx_stky |= TX_OK;
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memcpy (data, &emac->tx_stat, 4);
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dma->acked = true;
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return 4;
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}
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if (!(emac->opmode & RE))
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return 0;
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if (!flop)
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{
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ssize_t pad_ret;
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/* Outgoing DMA buffer has 16bit len prepended to it. */
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data += 2;
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/* This doesn't seem to work.
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if (emac->sysctl & RXDWA)
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{
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memset (data, 0, 2);
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data += 2;
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} */
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ret = read (emac->tap, data, nr_bytes);
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if (ret < 0)
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return 0;
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ret += 4; /* include crc */
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pad_ret = MAX (ret + 4, 64);
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len = pad_ret;
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memcpy (dest, &len, 2);
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pad_ret = (pad_ret + 3) & ~3;
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if (ret < pad_ret)
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memset (data + ret, 0, pad_ret - ret);
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pad_ret += 4;
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/* XXX: Need to check -- u-boot doesn't look at this. */
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|
if (emac->sysctl & RXCKS)
|
|
{
|
|
pad_ret += 4;
|
|
emac->rx_crc = 0;
|
|
}
|
|
ret = pad_ret;
|
|
|
|
/* XXX: Don't support promiscuous yet. */
|
|
emac->rx_stat |= RX_ACCEPT;
|
|
emac->rx_stat = (emac->rx_stat & ~RX_FRLEN) | len;
|
|
|
|
emac->rx_stat |= RX_COMP;
|
|
emac->rx_stky |= RX_COMP;
|
|
}
|
|
else
|
|
{
|
|
/* Write the RX status and crc info. */
|
|
emac->rx_stat |= RX_OK;
|
|
emac->rx_stky |= RX_OK;
|
|
|
|
ret = 4;
|
|
if (emac->sysctl & RXCKS)
|
|
{
|
|
memcpy (data, &emac->rx_crc, 4);
|
|
data += 4;
|
|
ret += 4;
|
|
}
|
|
memcpy (data, &emac->rx_stat, 4);
|
|
}
|
|
|
|
flop = !flop;
|
|
dma->acked = true;
|
|
return ret;
|
|
}
|
|
|
|
static unsigned
|
|
bfin_emac_dma_write_buffer (struct hw *me, const void *source,
|
|
int space, unsigned_word addr,
|
|
unsigned nr_bytes,
|
|
int violate_read_only_section)
|
|
{
|
|
struct bfin_emac *emac = hw_data (me);
|
|
struct dv_bfin *dma = hw_data (emac->dma_master);
|
|
const unsigned char *data = source;
|
|
bu16 len;
|
|
ssize_t ret;
|
|
|
|
HW_TRACE_DMA_WRITE ();
|
|
|
|
if (!(emac->opmode & TE))
|
|
return 0;
|
|
|
|
/* Incoming DMA buffer has 16bit len prepended to it. */
|
|
memcpy (&len, data, 2);
|
|
if (!len)
|
|
return 0;
|
|
|
|
ret = write (emac->tap, data + 2, len);
|
|
if (ret < 0)
|
|
return 0;
|
|
ret += 2;
|
|
|
|
emac->tx_stat |= TX_COMP;
|
|
emac->tx_stky |= TX_COMP;
|
|
|
|
dma_tx = dma;
|
|
dma->acked = true;
|
|
return ret;
|
|
}
|
|
|
|
static const struct hw_port_descriptor bfin_emac_ports[] =
|
|
{
|
|
{ "tx", DV_PORT_TX, 0, output_port, },
|
|
{ "rx", DV_PORT_RX, 0, output_port, },
|
|
{ "stat", DV_PORT_STAT, 0, output_port, },
|
|
{ NULL, 0, 0, 0, },
|
|
};
|
|
|
|
static void
|
|
bfin_emac_attach_address_callback (struct hw *me,
|
|
int level,
|
|
int space,
|
|
address_word addr,
|
|
address_word nr_bytes,
|
|
struct hw *client)
|
|
{
|
|
const hw_unit *unit = hw_unit_address (client);
|
|
HW_TRACE ((me, "attach - level=%d, space=%d, addr=0x%lx, nr_bytes=%lu, client=%s",
|
|
level, space, (unsigned long) addr, (unsigned long) nr_bytes, hw_path (client)));
|
|
/* NOTE: At preset the space is assumed to be zero. Perhaphs the
|
|
space should be mapped onto something for instance: space0 -
|
|
unified memory; space1 - IO memory; ... */
|
|
sim_core_attach (hw_system (me),
|
|
NULL, /*cpu*/
|
|
level + 10 + unit->cells[unit->nr_cells - 1],
|
|
access_read_write_exec,
|
|
space, addr,
|
|
nr_bytes,
|
|
0, /* modulo */
|
|
client,
|
|
NULL);
|
|
}
|
|
|
|
static void
|
|
bfin_emac_delete (struct hw *me)
|
|
{
|
|
struct bfin_emac *emac = hw_data (me);
|
|
close (emac->tap);
|
|
}
|
|
|
|
static void
|
|
bfin_emac_tap_init (struct hw *me)
|
|
{
|
|
#if WITH_TUN
|
|
struct bfin_emac *emac = hw_data (me);
|
|
const hw_unit *unit;
|
|
int flags;
|
|
|
|
unit = hw_unit_address (me);
|
|
|
|
emac->tap = open ("/dev/net/tun", O_RDWR);
|
|
if (emac->tap == -1)
|
|
{
|
|
HW_TRACE ((me, "unable to open /dev/net/tun: %s", strerror (errno)));
|
|
return;
|
|
}
|
|
|
|
memset (&emac->ifr, 0, sizeof (emac->ifr));
|
|
emac->ifr.ifr_flags = IFF_TAP | IFF_NO_PI;
|
|
strcpy (emac->ifr.ifr_name, "tap-gdb");
|
|
|
|
flags = 1 * 1024 * 1024;
|
|
if (ioctl (emac->tap, TUNSETIFF, &emac->ifr) < 0
|
|
#ifdef TUNSETNOCSUM
|
|
|| ioctl (emac->tap, TUNSETNOCSUM) < 0
|
|
#endif
|
|
#ifdef TUNSETSNDBUF
|
|
|| ioctl (emac->tap, TUNSETSNDBUF, &flags) < 0
|
|
#endif
|
|
)
|
|
{
|
|
HW_TRACE ((me, "tap ioctl setup failed: %s", strerror (errno)));
|
|
close (emac->tap);
|
|
return;
|
|
}
|
|
|
|
flags = fcntl (emac->tap, F_GETFL);
|
|
fcntl (emac->tap, F_SETFL, flags | O_NONBLOCK);
|
|
#endif
|
|
}
|
|
|
|
static void
|
|
bfin_emac_finish (struct hw *me)
|
|
{
|
|
struct bfin_emac *emac;
|
|
|
|
emac = HW_ZALLOC (me, struct bfin_emac);
|
|
|
|
set_hw_data (me, emac);
|
|
set_hw_io_read_buffer (me, bfin_emac_io_read_buffer);
|
|
set_hw_io_write_buffer (me, bfin_emac_io_write_buffer);
|
|
set_hw_dma_read_buffer (me, bfin_emac_dma_read_buffer);
|
|
set_hw_dma_write_buffer (me, bfin_emac_dma_write_buffer);
|
|
set_hw_ports (me, bfin_emac_ports);
|
|
set_hw_attach_address (me, bfin_emac_attach_address_callback);
|
|
set_hw_delete (me, bfin_emac_delete);
|
|
|
|
attach_bfin_emac_regs (me, emac);
|
|
|
|
/* Initialize the EMAC. */
|
|
emac->addrlo = 0xffffffff;
|
|
emac->addrhi = 0x0000ffff;
|
|
emac->vlan1 = 0x0000ffff;
|
|
emac->vlan2 = 0x0000ffff;
|
|
emac->sysctl = 0x00003f00;
|
|
emac->mmc_ctl = 0x0000000a;
|
|
|
|
bfin_emac_tap_init (me);
|
|
}
|
|
|
|
const struct hw_descriptor dv_bfin_emac_descriptor[] =
|
|
{
|
|
{"bfin_emac", bfin_emac_finish,},
|
|
{NULL, NULL},
|
|
};
|