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228 lines
6.7 KiB
C
228 lines
6.7 KiB
C
/* Target-dependent code for NetBSD/powerpc.
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Copyright (C) 2002-2017 Free Software Foundation, Inc.
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Contributed by Wasabi Systems, Inc.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#include "defs.h"
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#include "gdbtypes.h"
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#include "osabi.h"
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#include "regcache.h"
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#include "regset.h"
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#include "trad-frame.h"
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#include "tramp-frame.h"
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#include "ppc-tdep.h"
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#include "ppc-nbsd-tdep.h"
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#include "solib-svr4.h"
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/* Register offsets from <machine/reg.h>. */
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struct ppc_reg_offsets ppcnbsd_reg_offsets;
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/* Core file support. */
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/* NetBSD/powerpc register sets. */
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const struct regset ppcnbsd_gregset =
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{
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&ppcnbsd_reg_offsets,
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ppc_supply_gregset
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};
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const struct regset ppcnbsd_fpregset =
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{
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&ppcnbsd_reg_offsets,
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ppc_supply_fpregset
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};
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/* Iterate over core file register note sections. */
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static void
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ppcnbsd_iterate_over_regset_sections (struct gdbarch *gdbarch,
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iterate_over_regset_sections_cb *cb,
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void *cb_data,
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const struct regcache *regcache)
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{
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cb (".reg", 148, &ppcnbsd_gregset, NULL, cb_data);
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cb (".reg2", 264, &ppcnbsd_fpregset, NULL, cb_data);
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}
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/* NetBSD is confused. It appears that 1.5 was using the correct SVR4
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convention but, 1.6 switched to the below broken convention. For
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the moment use the broken convention. Ulgh! */
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static enum return_value_convention
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ppcnbsd_return_value (struct gdbarch *gdbarch, struct value *function,
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struct type *valtype, struct regcache *regcache,
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gdb_byte *readbuf, const gdb_byte *writebuf)
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{
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#if 0
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if ((TYPE_CODE (valtype) == TYPE_CODE_STRUCT
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|| TYPE_CODE (valtype) == TYPE_CODE_UNION)
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&& !((TYPE_LENGTH (valtype) == 16 || TYPE_LENGTH (valtype) == 8)
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&& TYPE_VECTOR (valtype))
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&& !(TYPE_LENGTH (valtype) == 1
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|| TYPE_LENGTH (valtype) == 2
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|| TYPE_LENGTH (valtype) == 4
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|| TYPE_LENGTH (valtype) == 8))
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return RETURN_VALUE_STRUCT_CONVENTION;
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else
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#endif
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return ppc_sysv_abi_broken_return_value (gdbarch, function, valtype,
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regcache, readbuf, writebuf);
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}
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/* Signal trampolines. */
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extern const struct tramp_frame ppcnbsd2_sigtramp;
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static void
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ppcnbsd_sigtramp_cache_init (const struct tramp_frame *self,
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struct frame_info *this_frame,
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struct trad_frame_cache *this_cache,
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CORE_ADDR func)
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{
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struct gdbarch *gdbarch = get_frame_arch (this_frame);
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struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
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CORE_ADDR addr, base;
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int i;
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base = get_frame_register_unsigned (this_frame,
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gdbarch_sp_regnum (gdbarch));
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if (self == &ppcnbsd2_sigtramp)
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addr = base + 0x10 + 2 * tdep->wordsize;
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else
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addr = base + 0x18 + 2 * tdep->wordsize;
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for (i = 0; i < ppc_num_gprs; i++, addr += tdep->wordsize)
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{
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int regnum = i + tdep->ppc_gp0_regnum;
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trad_frame_set_reg_addr (this_cache, regnum, addr);
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}
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trad_frame_set_reg_addr (this_cache, tdep->ppc_lr_regnum, addr);
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addr += tdep->wordsize;
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trad_frame_set_reg_addr (this_cache, tdep->ppc_cr_regnum, addr);
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addr += tdep->wordsize;
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trad_frame_set_reg_addr (this_cache, tdep->ppc_xer_regnum, addr);
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addr += tdep->wordsize;
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trad_frame_set_reg_addr (this_cache, tdep->ppc_ctr_regnum, addr);
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addr += tdep->wordsize;
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trad_frame_set_reg_addr (this_cache, gdbarch_pc_regnum (gdbarch),
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addr); /* SRR0? */
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addr += tdep->wordsize;
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/* Construct the frame ID using the function start. */
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trad_frame_set_id (this_cache, frame_id_build (base, func));
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}
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static const struct tramp_frame ppcnbsd_sigtramp =
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{
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SIGTRAMP_FRAME,
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4,
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{
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{ 0x3821fff0, -1 }, /* add r1,r1,-16 */
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{ 0x4e800021, -1 }, /* blrl */
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{ 0x38610018, -1 }, /* addi r3,r1,24 */
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{ 0x38000127, -1 }, /* li r0,295 */
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{ 0x44000002, -1 }, /* sc */
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{ 0x38000001, -1 }, /* li r0,1 */
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{ 0x44000002, -1 }, /* sc */
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{ TRAMP_SENTINEL_INSN, -1 }
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},
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ppcnbsd_sigtramp_cache_init
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};
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/* NetBSD 2.0 introduced a slightly different signal trampoline. */
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const struct tramp_frame ppcnbsd2_sigtramp =
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{
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SIGTRAMP_FRAME,
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4,
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{
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{ 0x3821fff0, -1 }, /* add r1,r1,-16 */
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{ 0x4e800021, -1 }, /* blrl */
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{ 0x38610010, -1 }, /* addi r3,r1,16 */
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{ 0x38000127, -1 }, /* li r0,295 */
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{ 0x44000002, -1 }, /* sc */
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{ 0x38000001, -1 }, /* li r0,1 */
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{ 0x44000002, -1 }, /* sc */
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{ TRAMP_SENTINEL_INSN, -1 }
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},
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ppcnbsd_sigtramp_cache_init
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};
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static void
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ppcnbsd_init_abi (struct gdbarch_info info,
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struct gdbarch *gdbarch)
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{
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/* For NetBSD, this is an on again, off again thing. Some systems
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do use the broken struct convention, and some don't. */
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set_gdbarch_return_value (gdbarch, ppcnbsd_return_value);
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/* NetBSD uses SVR4-style shared libraries. */
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set_solib_svr4_fetch_link_map_offsets
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(gdbarch, svr4_ilp32_fetch_link_map_offsets);
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set_gdbarch_iterate_over_regset_sections
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(gdbarch, ppcnbsd_iterate_over_regset_sections);
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tramp_frame_prepend_unwinder (gdbarch, &ppcnbsd_sigtramp);
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tramp_frame_prepend_unwinder (gdbarch, &ppcnbsd2_sigtramp);
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}
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/* Provide a prototype to silence -Wmissing-prototypes. */
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void _initialize_ppcnbsd_tdep (void);
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void
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_initialize_ppcnbsd_tdep (void)
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{
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gdbarch_register_osabi (bfd_arch_powerpc, 0, GDB_OSABI_NETBSD,
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ppcnbsd_init_abi);
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/* Avoid initializing the register offsets again if they were
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already initialized by ppcnbsd-nat.c. */
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if (ppcnbsd_reg_offsets.pc_offset == 0)
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{
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/* General-purpose registers. */
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ppcnbsd_reg_offsets.r0_offset = 0;
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ppcnbsd_reg_offsets.gpr_size = 4;
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ppcnbsd_reg_offsets.xr_size = 4;
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ppcnbsd_reg_offsets.lr_offset = 128;
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ppcnbsd_reg_offsets.cr_offset = 132;
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ppcnbsd_reg_offsets.xer_offset = 136;
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ppcnbsd_reg_offsets.ctr_offset = 140;
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ppcnbsd_reg_offsets.pc_offset = 144;
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ppcnbsd_reg_offsets.ps_offset = -1;
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ppcnbsd_reg_offsets.mq_offset = -1;
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/* Floating-point registers. */
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ppcnbsd_reg_offsets.f0_offset = 0;
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ppcnbsd_reg_offsets.fpscr_offset = 256;
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ppcnbsd_reg_offsets.fpscr_size = 4;
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/* AltiVec registers. */
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ppcnbsd_reg_offsets.vr0_offset = 0;
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ppcnbsd_reg_offsets.vrsave_offset = 512;
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ppcnbsd_reg_offsets.vscr_offset = 524;
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}
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}
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