binutils-gdb/opcodes/cgen-opc.in
Doug Evans 86dc452e25 * cgen-dis.c (hash_insn_array): CGEN_INSN_VALUE ->
CGEN_INSN_BASE_VALUE.
	* cgen-asm.in (insert_normal): Change start,length to unsigned int.
	New args word_offset, word_length.  Rewrite.
	(FLD): Define.
	(insert_1): Fix lsb0 case.
	* cgen-dis.in (extract_normal): Change start,length to unsigned int.
	New args word_offset, word_length.  Rewrite.
	(FLD): Define.
	(extract_1): Fix lsb0 case.
	* cgen-opc.in (FLD): Define.
	* m32r-opc.c,m32r-opc.h,m32r-asm.c,m32r-dis.c: Regenerate.
	* fr30-opc.c,fr30-opc.h,fr30-asm.c,fr30-dis.c: Regenerate.
1998-11-30 23:41:55 +00:00

203 lines
5.8 KiB
C

/* Generic opcode table support for targets using CGEN. -*- C -*-
CGEN: Cpu tools GENerator
THIS FILE IS USED TO GENERATE @prefix@-opc.c.
Copyright (C) 1998 Free Software Foundation, Inc.
This file is part of the GNU Binutils and GDB, the GNU debugger.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
#include "sysdep.h"
#include <stdio.h>
#include "ansidecl.h"
#include "libiberty.h"
#include "bfd.h"
#include "symcat.h"
#include "@prefix@-opc.h"
#include "opintl.h"
/* Used by the ifield rtx function. */
#define FLD(f) (fields->f)
/* The hash functions are recorded here to help keep assembler code out of
the disassembler and vice versa. */
static int asm_hash_insn_p PARAMS ((const CGEN_INSN *));
static unsigned int asm_hash_insn PARAMS ((const char *));
static int dis_hash_insn_p PARAMS ((const CGEN_INSN *));
static unsigned int dis_hash_insn PARAMS ((const char *, CGEN_INSN_INT));
/* Look up instruction INSN_VALUE and extract its fields.
INSN, if non-null, is the insn table entry.
Otherwise INSN_VALUE is examined to compute it.
LENGTH is the bit length of INSN_VALUE if known, otherwise 0.
0 is only valid if `insn == NULL && ! CGEN_INT_INSN_P'.
If INSN != NULL, LENGTH must be valid.
ALIAS_P is non-zero if alias insns are to be included in the search.
The result is a pointer to the insn table entry, or NULL if the instruction
wasn't recognized. */
const CGEN_INSN *
@arch@_cgen_lookup_insn (od, insn, insn_value, length, fields, alias_p)
CGEN_OPCODE_DESC od;
const CGEN_INSN *insn;
CGEN_INSN_BYTES insn_value;
int length;
CGEN_FIELDS *fields;
int alias_p;
{
unsigned char buf[CGEN_MAX_INSN_SIZE];
unsigned char *bufp;
CGEN_INSN_INT base_insn;
#if CGEN_INT_INSN_P
CGEN_EXTRACT_INFO *info = NULL;
#else
CGEN_EXTRACT_INFO ex_info;
CGEN_EXTRACT_INFO *info = &ex_info;
#endif
#if CGEN_INT_INSN_P
cgen_put_insn_value (od, buf, length, insn_value);
bufp = buf;
base_insn = insn_value; /*???*/
#else
ex_info.dis_info = NULL;
ex_info.insn_bytes = insn_value;
ex_info.valid = -1;
base_insn = cgen_get_insn_value (od, buf, length);
bufp = insn_value;
#endif
if (!insn)
{
const CGEN_INSN_LIST *insn_list;
/* The instructions are stored in hash lists.
Pick the first one and keep trying until we find the right one. */
insn_list = CGEN_DIS_LOOKUP_INSN (od, bufp, base_insn);
while (insn_list != NULL)
{
insn = insn_list->insn;
if (alias_p
|| ! CGEN_INSN_ATTR (insn, CGEN_INSN_ALIAS))
{
/* Basic bit mask must be correct. */
/* ??? May wish to allow target to defer this check until the
extract handler. */
if ((base_insn & CGEN_INSN_BASE_MASK (insn))
== CGEN_INSN_BASE_VALUE (insn))
{
/* ??? 0 is passed for `pc' */
int elength = (*CGEN_EXTRACT_FN (insn)) (od, insn, info,
base_insn, fields,
(bfd_vma) 0);
if (elength > 0)
{
/* sanity check */
if (length != 0 && length != elength)
abort ();
return insn;
}
}
}
insn_list = CGEN_DIS_NEXT_INSN (insn_list);
}
}
else
{
/* Sanity check: can't pass an alias insn if ! alias_p. */
if (! alias_p
&& CGEN_INSN_ATTR (insn, CGEN_INSN_ALIAS))
abort ();
/* Sanity check: length must be correct. */
if (length != CGEN_INSN_BITSIZE (insn))
abort ();
/* ??? 0 is passed for `pc' */
length = (*CGEN_EXTRACT_FN (insn)) (od, insn, info, base_insn, fields,
(bfd_vma) 0);
/* Sanity check: must succeed.
Could relax this later if it ever proves useful. */
if (length == 0)
abort ();
return insn;
}
return NULL;
}
/* Fill in the operand instances used by INSN whose operands are FIELDS.
INDICES is a pointer to a buffer of MAX_OPERAND_INSTANCES ints to be filled
in. */
void
@arch@_cgen_get_insn_operands (od, insn, fields, indices)
CGEN_OPCODE_DESC od;
const CGEN_INSN * insn;
const CGEN_FIELDS * fields;
int *indices;
{
const CGEN_OPERAND_INSTANCE *opinst;
int i;
for (i = 0, opinst = CGEN_INSN_OPERANDS (insn);
opinst != NULL
&& CGEN_OPERAND_INSTANCE_TYPE (opinst) != CGEN_OPERAND_INSTANCE_END;
++i, ++opinst)
{
const CGEN_OPERAND *op = CGEN_OPERAND_INSTANCE_OPERAND (opinst);
if (op == NULL)
indices[i] = CGEN_OPERAND_INSTANCE_INDEX (opinst);
else
indices[i] = @arch@_cgen_get_int_operand (CGEN_OPERAND_INDEX (op),
fields);
}
}
/* Cover function to @arch@_cgen_get_insn_operands when either INSN or FIELDS
isn't known.
The INSN, INSN_VALUE, and LENGTH arguments are passed to
@arch@_cgen_lookup_insn unchanged.
The result is the insn table entry or NULL if the instruction wasn't
recognized. */
const CGEN_INSN *
@arch@_cgen_lookup_get_insn_operands (od, insn, insn_value, length, indices)
CGEN_OPCODE_DESC od;
const CGEN_INSN *insn;
CGEN_INSN_BYTES insn_value;
int length;
int *indices;
{
CGEN_FIELDS fields;
/* Pass non-zero for ALIAS_P only if INSN != NULL.
If INSN == NULL, we want a real insn. */
insn = @arch@_cgen_lookup_insn (od, insn, insn_value, length, &fields,
insn != NULL);
if (! insn)
return NULL;
@arch@_cgen_get_insn_operands (od, insn, &fields, indices);
return insn;
}