861 lines
27 KiB
C
861 lines
27 KiB
C
/* Copyright (C) 2009-2019 Free Software Foundation, Inc.
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Contributed by ARM Ltd.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#include "common/common-defs.h"
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#include "common/break-common.h"
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#include "common/common-regcache.h"
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#include "nat/linux-nat.h"
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#include "aarch64-linux-hw-point.h"
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#include <sys/uio.h>
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#include <asm/ptrace.h>
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#include <sys/ptrace.h>
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#include <elf.h>
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/* Number of hardware breakpoints/watchpoints the target supports.
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They are initialized with values obtained via the ptrace calls
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with NT_ARM_HW_BREAK and NT_ARM_HW_WATCH respectively. */
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int aarch64_num_bp_regs;
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int aarch64_num_wp_regs;
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/* True if this kernel does not have the bug described by PR
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external/20207 (Linux >= 4.10). A fixed kernel supports any
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contiguous range of bits in 8-bit byte DR_CONTROL_MASK. A buggy
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kernel supports only 0x01, 0x03, 0x0f and 0xff. We start by
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assuming the bug is fixed, and then detect the bug at
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PTRACE_SETREGSET time. */
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static bool kernel_supports_any_contiguous_range = true;
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/* Return starting byte 0..7 incl. of a watchpoint encoded by CTRL. */
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unsigned int
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aarch64_watchpoint_offset (unsigned int ctrl)
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{
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uint8_t mask = DR_CONTROL_MASK (ctrl);
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unsigned retval;
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/* Shift out bottom zeros. */
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for (retval = 0; mask && (mask & 1) == 0; ++retval)
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mask >>= 1;
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return retval;
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}
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/* Utility function that returns the length in bytes of a watchpoint
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according to the content of a hardware debug control register CTRL.
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Any contiguous range of bytes in CTRL is supported. The returned
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value can be between 0..8 (inclusive). */
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unsigned int
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aarch64_watchpoint_length (unsigned int ctrl)
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{
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uint8_t mask = DR_CONTROL_MASK (ctrl);
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unsigned retval;
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/* Shift out bottom zeros. */
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mask >>= aarch64_watchpoint_offset (ctrl);
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/* Count bottom ones. */
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for (retval = 0; (mask & 1) != 0; ++retval)
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mask >>= 1;
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if (mask != 0)
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error (_("Unexpected hardware watchpoint length register value 0x%x"),
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DR_CONTROL_MASK (ctrl));
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return retval;
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}
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/* Given the hardware breakpoint or watchpoint type TYPE and its
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length LEN, return the expected encoding for a hardware
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breakpoint/watchpoint control register. */
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static unsigned int
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aarch64_point_encode_ctrl_reg (enum target_hw_bp_type type, int offset, int len)
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{
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unsigned int ctrl, ttype;
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gdb_assert (offset == 0 || kernel_supports_any_contiguous_range);
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gdb_assert (offset + len <= AARCH64_HWP_MAX_LEN_PER_REG);
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/* type */
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switch (type)
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{
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case hw_write:
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ttype = 2;
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break;
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case hw_read:
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ttype = 1;
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break;
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case hw_access:
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ttype = 3;
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break;
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case hw_execute:
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ttype = 0;
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break;
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default:
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perror_with_name (_("Unrecognized breakpoint/watchpoint type"));
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}
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ctrl = ttype << 3;
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/* offset and length bitmask */
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ctrl |= ((1 << len) - 1) << (5 + offset);
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/* enabled at el0 */
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ctrl |= (2 << 1) | 1;
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return ctrl;
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}
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/* Addresses to be written to the hardware breakpoint and watchpoint
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value registers need to be aligned; the alignment is 4-byte and
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8-type respectively. Linux kernel rejects any non-aligned address
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it receives from the related ptrace call. Furthermore, the kernel
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currently only supports the following Byte Address Select (BAS)
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values: 0x1, 0x3, 0xf and 0xff, which means that for a hardware
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watchpoint to be accepted by the kernel (via ptrace call), its
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valid length can only be 1 byte, 2 bytes, 4 bytes or 8 bytes.
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Despite these limitations, the unaligned watchpoint is supported in
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this port.
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Return 0 for any non-compliant ADDR and/or LEN; return 1 otherwise. */
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static int
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aarch64_point_is_aligned (int is_watchpoint, CORE_ADDR addr, int len)
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{
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unsigned int alignment = 0;
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if (is_watchpoint)
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alignment = AARCH64_HWP_ALIGNMENT;
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else
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{
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struct regcache *regcache
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= get_thread_regcache_for_ptid (current_lwp_ptid ());
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/* Set alignment to 2 only if the current process is 32-bit,
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since thumb instruction can be 2-byte aligned. Otherwise, set
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alignment to AARCH64_HBP_ALIGNMENT. */
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if (regcache_register_size (regcache, 0) == 8)
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alignment = AARCH64_HBP_ALIGNMENT;
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else
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alignment = 2;
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}
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if (addr & (alignment - 1))
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return 0;
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if ((!kernel_supports_any_contiguous_range
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&& len != 8 && len != 4 && len != 2 && len != 1)
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|| (kernel_supports_any_contiguous_range
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&& (len < 1 || len > 8)))
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return 0;
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return 1;
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}
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/* Given the (potentially unaligned) watchpoint address in ADDR and
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length in LEN, return the aligned address, offset from that base
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address, and aligned length in *ALIGNED_ADDR_P, *ALIGNED_OFFSET_P
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and *ALIGNED_LEN_P, respectively. The returned values will be
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valid values to write to the hardware watchpoint value and control
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registers.
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The given watchpoint may get truncated if more than one hardware
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register is needed to cover the watched region. *NEXT_ADDR_P
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and *NEXT_LEN_P, if non-NULL, will return the address and length
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of the remaining part of the watchpoint (which can be processed
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by calling this routine again to generate another aligned address,
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offset and length tuple.
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Essentially, unaligned watchpoint is achieved by minimally
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enlarging the watched area to meet the alignment requirement, and
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if necessary, splitting the watchpoint over several hardware
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watchpoint registers.
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On kernels that predate the support for Byte Address Select (BAS)
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in the hardware watchpoint control register, the offset from the
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base address is always zero, and so in that case the trade-off is
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that there will be false-positive hits for the read-type or the
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access-type hardware watchpoints; for the write type, which is more
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commonly used, there will be no such issues, as the higher-level
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breakpoint management in gdb always examines the exact watched
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region for any content change, and transparently resumes a thread
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from a watchpoint trap if there is no change to the watched region.
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Another limitation is that because the watched region is enlarged,
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the watchpoint fault address discovered by
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aarch64_stopped_data_address may be outside of the original watched
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region, especially when the triggering instruction is accessing a
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larger region. When the fault address is not within any known
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range, watchpoints_triggered in gdb will get confused, as the
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higher-level watchpoint management is only aware of original
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watched regions, and will think that some unknown watchpoint has
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been triggered. To prevent such a case,
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aarch64_stopped_data_address implementations in gdb and gdbserver
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try to match the trapped address with a watched region, and return
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an address within the latter. */
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static void
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aarch64_align_watchpoint (CORE_ADDR addr, int len, CORE_ADDR *aligned_addr_p,
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int *aligned_offset_p, int *aligned_len_p,
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CORE_ADDR *next_addr_p, int *next_len_p,
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CORE_ADDR *next_addr_orig_p)
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{
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int aligned_len;
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unsigned int offset, aligned_offset;
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CORE_ADDR aligned_addr;
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const unsigned int alignment = AARCH64_HWP_ALIGNMENT;
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const unsigned int max_wp_len = AARCH64_HWP_MAX_LEN_PER_REG;
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/* As assumed by the algorithm. */
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gdb_assert (alignment == max_wp_len);
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if (len <= 0)
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return;
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/* The address put into the hardware watchpoint value register must
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be aligned. */
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offset = addr & (alignment - 1);
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aligned_addr = addr - offset;
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aligned_offset
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= kernel_supports_any_contiguous_range ? addr & (alignment - 1) : 0;
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gdb_assert (offset >= 0 && offset < alignment);
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gdb_assert (aligned_addr >= 0 && aligned_addr <= addr);
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gdb_assert (offset + len > 0);
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if (offset + len >= max_wp_len)
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{
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/* Need more than one watchpoint register; truncate at the
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alignment boundary. */
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aligned_len
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= max_wp_len - (kernel_supports_any_contiguous_range ? offset : 0);
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len -= (max_wp_len - offset);
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addr += (max_wp_len - offset);
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gdb_assert ((addr & (alignment - 1)) == 0);
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}
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else
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{
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/* Find the smallest valid length that is large enough to
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accommodate this watchpoint. */
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static const unsigned char
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aligned_len_array[AARCH64_HWP_MAX_LEN_PER_REG] =
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{ 1, 2, 4, 4, 8, 8, 8, 8 };
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aligned_len = (kernel_supports_any_contiguous_range
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? len : aligned_len_array[offset + len - 1]);
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addr += len;
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len = 0;
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}
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if (aligned_addr_p)
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*aligned_addr_p = aligned_addr;
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if (aligned_offset_p)
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*aligned_offset_p = aligned_offset;
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if (aligned_len_p)
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*aligned_len_p = aligned_len;
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if (next_addr_p)
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*next_addr_p = addr;
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if (next_len_p)
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*next_len_p = len;
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if (next_addr_orig_p)
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*next_addr_orig_p = align_down (*next_addr_orig_p + alignment, alignment);
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}
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/* Helper for aarch64_notify_debug_reg_change. Records the
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information about the change of one hardware breakpoint/watchpoint
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setting for the thread LWP.
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N.B. The actual updating of hardware debug registers is not
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carried out until the moment the thread is resumed. */
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static int
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debug_reg_change_callback (struct lwp_info *lwp, int is_watchpoint,
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unsigned int idx)
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{
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int tid = ptid_of_lwp (lwp).lwp ();
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struct arch_lwp_info *info = lwp_arch_private_info (lwp);
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dr_changed_t *dr_changed_ptr;
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dr_changed_t dr_changed;
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if (info == NULL)
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{
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info = XCNEW (struct arch_lwp_info);
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lwp_set_arch_private_info (lwp, info);
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}
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if (show_debug_regs)
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{
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debug_printf ("debug_reg_change_callback: \n\tOn entry:\n");
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debug_printf ("\ttid%d, dr_changed_bp=0x%s, "
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"dr_changed_wp=0x%s\n", tid,
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phex (info->dr_changed_bp, 8),
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phex (info->dr_changed_wp, 8));
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}
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dr_changed_ptr = is_watchpoint ? &info->dr_changed_wp
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: &info->dr_changed_bp;
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dr_changed = *dr_changed_ptr;
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gdb_assert (idx >= 0
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&& (idx <= (is_watchpoint ? aarch64_num_wp_regs
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: aarch64_num_bp_regs)));
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/* The actual update is done later just before resuming the lwp,
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we just mark that one register pair needs updating. */
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DR_MARK_N_CHANGED (dr_changed, idx);
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*dr_changed_ptr = dr_changed;
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/* If the lwp isn't stopped, force it to momentarily pause, so
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we can update its debug registers. */
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if (!lwp_is_stopped (lwp))
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linux_stop_lwp (lwp);
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if (show_debug_regs)
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{
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debug_printf ("\tOn exit:\n\ttid%d, dr_changed_bp=0x%s, "
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"dr_changed_wp=0x%s\n", tid,
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phex (info->dr_changed_bp, 8),
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phex (info->dr_changed_wp, 8));
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}
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return 0;
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}
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/* Notify each thread that their IDXth breakpoint/watchpoint register
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pair needs to be updated. The message will be recorded in each
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thread's arch-specific data area, the actual updating will be done
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when the thread is resumed. */
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static void
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aarch64_notify_debug_reg_change (const struct aarch64_debug_reg_state *state,
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int is_watchpoint, unsigned int idx)
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{
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ptid_t pid_ptid = ptid_t (current_lwp_ptid ().pid ());
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iterate_over_lwps (pid_ptid, [=] (struct lwp_info *info)
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{
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return debug_reg_change_callback (info,
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is_watchpoint,
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idx);
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});
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}
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/* Reconfigure STATE to be compatible with Linux kernels with the PR
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external/20207 bug. This is called when
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KERNEL_SUPPORTS_ANY_CONTIGUOUS_RANGE transitions to false. Note we
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don't try to support combining watchpoints with matching (and thus
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shared) masks, as it's too late when we get here. On buggy
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kernels, GDB will try to first setup the perfect matching ranges,
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which will run out of registers before this function can merge
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them. It doesn't look like worth the effort to improve that, given
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eventually buggy kernels will be phased out. */
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static void
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aarch64_downgrade_regs (struct aarch64_debug_reg_state *state)
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{
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for (int i = 0; i < aarch64_num_wp_regs; ++i)
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if ((state->dr_ctrl_wp[i] & 1) != 0)
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{
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gdb_assert (state->dr_ref_count_wp[i] != 0);
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uint8_t mask_orig = (state->dr_ctrl_wp[i] >> 5) & 0xff;
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gdb_assert (mask_orig != 0);
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static const uint8_t old_valid[] = { 0x01, 0x03, 0x0f, 0xff };
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uint8_t mask = 0;
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for (const uint8_t old_mask : old_valid)
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if (mask_orig <= old_mask)
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{
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mask = old_mask;
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break;
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}
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gdb_assert (mask != 0);
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/* No update needed for this watchpoint? */
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if (mask == mask_orig)
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continue;
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state->dr_ctrl_wp[i] |= mask << 5;
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state->dr_addr_wp[i]
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= align_down (state->dr_addr_wp[i], AARCH64_HWP_ALIGNMENT);
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/* Try to match duplicate entries. */
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for (int j = 0; j < i; ++j)
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if ((state->dr_ctrl_wp[j] & 1) != 0
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&& state->dr_addr_wp[j] == state->dr_addr_wp[i]
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&& state->dr_addr_orig_wp[j] == state->dr_addr_orig_wp[i]
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&& state->dr_ctrl_wp[j] == state->dr_ctrl_wp[i])
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{
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state->dr_ref_count_wp[j] += state->dr_ref_count_wp[i];
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state->dr_ref_count_wp[i] = 0;
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state->dr_addr_wp[i] = 0;
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state->dr_addr_orig_wp[i] = 0;
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state->dr_ctrl_wp[i] &= ~1;
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break;
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}
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aarch64_notify_debug_reg_change (state, 1 /* is_watchpoint */, i);
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}
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}
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/* Record the insertion of one breakpoint/watchpoint, as represented
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by ADDR and CTRL, in the process' arch-specific data area *STATE. */
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static int
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aarch64_dr_state_insert_one_point (struct aarch64_debug_reg_state *state,
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enum target_hw_bp_type type,
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CORE_ADDR addr, int offset, int len,
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CORE_ADDR addr_orig)
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{
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int i, idx, num_regs, is_watchpoint;
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unsigned int ctrl, *dr_ctrl_p, *dr_ref_count;
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CORE_ADDR *dr_addr_p, *dr_addr_orig_p;
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/* Set up state pointers. */
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is_watchpoint = (type != hw_execute);
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gdb_assert (aarch64_point_is_aligned (is_watchpoint, addr, len));
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if (is_watchpoint)
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{
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num_regs = aarch64_num_wp_regs;
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dr_addr_p = state->dr_addr_wp;
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dr_addr_orig_p = state->dr_addr_orig_wp;
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dr_ctrl_p = state->dr_ctrl_wp;
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dr_ref_count = state->dr_ref_count_wp;
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}
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else
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{
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num_regs = aarch64_num_bp_regs;
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dr_addr_p = state->dr_addr_bp;
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dr_addr_orig_p = nullptr;
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dr_ctrl_p = state->dr_ctrl_bp;
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dr_ref_count = state->dr_ref_count_bp;
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}
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ctrl = aarch64_point_encode_ctrl_reg (type, offset, len);
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/* Find an existing or free register in our cache. */
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idx = -1;
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for (i = 0; i < num_regs; ++i)
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{
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if ((dr_ctrl_p[i] & 1) == 0)
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{
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gdb_assert (dr_ref_count[i] == 0);
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idx = i;
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/* no break; continue hunting for an exising one. */
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}
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else if (dr_addr_p[i] == addr
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&& (dr_addr_orig_p == nullptr || dr_addr_orig_p[i] == addr_orig)
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&& dr_ctrl_p[i] == ctrl)
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{
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gdb_assert (dr_ref_count[i] != 0);
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idx = i;
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break;
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}
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}
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/* No space. */
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if (idx == -1)
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return -1;
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/* Update our cache. */
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if ((dr_ctrl_p[idx] & 1) == 0)
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{
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/* new entry */
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dr_addr_p[idx] = addr;
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if (dr_addr_orig_p != nullptr)
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dr_addr_orig_p[idx] = addr_orig;
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dr_ctrl_p[idx] = ctrl;
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dr_ref_count[idx] = 1;
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/* Notify the change. */
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aarch64_notify_debug_reg_change (state, is_watchpoint, idx);
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}
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else
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{
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/* existing entry */
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dr_ref_count[idx]++;
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}
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return 0;
|
|
}
|
|
|
|
/* Record the removal of one breakpoint/watchpoint, as represented by
|
|
ADDR and CTRL, in the process' arch-specific data area *STATE. */
|
|
|
|
static int
|
|
aarch64_dr_state_remove_one_point (struct aarch64_debug_reg_state *state,
|
|
enum target_hw_bp_type type,
|
|
CORE_ADDR addr, int offset, int len,
|
|
CORE_ADDR addr_orig)
|
|
{
|
|
int i, num_regs, is_watchpoint;
|
|
unsigned int ctrl, *dr_ctrl_p, *dr_ref_count;
|
|
CORE_ADDR *dr_addr_p, *dr_addr_orig_p;
|
|
|
|
/* Set up state pointers. */
|
|
is_watchpoint = (type != hw_execute);
|
|
if (is_watchpoint)
|
|
{
|
|
num_regs = aarch64_num_wp_regs;
|
|
dr_addr_p = state->dr_addr_wp;
|
|
dr_addr_orig_p = state->dr_addr_orig_wp;
|
|
dr_ctrl_p = state->dr_ctrl_wp;
|
|
dr_ref_count = state->dr_ref_count_wp;
|
|
}
|
|
else
|
|
{
|
|
num_regs = aarch64_num_bp_regs;
|
|
dr_addr_p = state->dr_addr_bp;
|
|
dr_addr_orig_p = nullptr;
|
|
dr_ctrl_p = state->dr_ctrl_bp;
|
|
dr_ref_count = state->dr_ref_count_bp;
|
|
}
|
|
|
|
ctrl = aarch64_point_encode_ctrl_reg (type, offset, len);
|
|
|
|
/* Find the entry that matches the ADDR and CTRL. */
|
|
for (i = 0; i < num_regs; ++i)
|
|
if (dr_addr_p[i] == addr
|
|
&& (dr_addr_orig_p == nullptr || dr_addr_orig_p[i] == addr_orig)
|
|
&& dr_ctrl_p[i] == ctrl)
|
|
{
|
|
gdb_assert (dr_ref_count[i] != 0);
|
|
break;
|
|
}
|
|
|
|
/* Not found. */
|
|
if (i == num_regs)
|
|
return -1;
|
|
|
|
/* Clear our cache. */
|
|
if (--dr_ref_count[i] == 0)
|
|
{
|
|
/* Clear the enable bit. */
|
|
ctrl &= ~1;
|
|
dr_addr_p[i] = 0;
|
|
if (dr_addr_orig_p != nullptr)
|
|
dr_addr_orig_p[i] = 0;
|
|
dr_ctrl_p[i] = ctrl;
|
|
/* Notify the change. */
|
|
aarch64_notify_debug_reg_change (state, is_watchpoint, i);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
int
|
|
aarch64_handle_breakpoint (enum target_hw_bp_type type, CORE_ADDR addr,
|
|
int len, int is_insert,
|
|
struct aarch64_debug_reg_state *state)
|
|
{
|
|
if (is_insert)
|
|
{
|
|
/* The hardware breakpoint on AArch64 should always be 4-byte
|
|
aligned, but on AArch32, it can be 2-byte aligned. Note that
|
|
we only check the alignment on inserting breakpoint because
|
|
aarch64_point_is_aligned needs the inferior_ptid inferior's
|
|
regcache to decide whether the inferior is 32-bit or 64-bit.
|
|
However when GDB follows the parent process and detach breakpoints
|
|
from child process, inferior_ptid is the child ptid, but the
|
|
child inferior doesn't exist in GDB's view yet. */
|
|
if (!aarch64_point_is_aligned (0 /* is_watchpoint */ , addr, len))
|
|
return -1;
|
|
|
|
return aarch64_dr_state_insert_one_point (state, type, addr, 0, len, -1);
|
|
}
|
|
else
|
|
return aarch64_dr_state_remove_one_point (state, type, addr, 0, len, -1);
|
|
}
|
|
|
|
/* This is essentially the same as aarch64_handle_breakpoint, apart
|
|
from that it is an aligned watchpoint to be handled. */
|
|
|
|
static int
|
|
aarch64_handle_aligned_watchpoint (enum target_hw_bp_type type,
|
|
CORE_ADDR addr, int len, int is_insert,
|
|
struct aarch64_debug_reg_state *state)
|
|
{
|
|
if (is_insert)
|
|
return aarch64_dr_state_insert_one_point (state, type, addr, 0, len, addr);
|
|
else
|
|
return aarch64_dr_state_remove_one_point (state, type, addr, 0, len, addr);
|
|
}
|
|
|
|
/* Insert/remove unaligned watchpoint by calling
|
|
aarch64_align_watchpoint repeatedly until the whole watched region,
|
|
as represented by ADDR and LEN, has been properly aligned and ready
|
|
to be written to one or more hardware watchpoint registers.
|
|
IS_INSERT indicates whether this is an insertion or a deletion.
|
|
Return 0 if succeed. */
|
|
|
|
static int
|
|
aarch64_handle_unaligned_watchpoint (enum target_hw_bp_type type,
|
|
CORE_ADDR addr, int len, int is_insert,
|
|
struct aarch64_debug_reg_state *state)
|
|
{
|
|
CORE_ADDR addr_orig = addr;
|
|
|
|
while (len > 0)
|
|
{
|
|
CORE_ADDR aligned_addr;
|
|
int aligned_offset, aligned_len, ret;
|
|
CORE_ADDR addr_orig_next = addr_orig;
|
|
|
|
aarch64_align_watchpoint (addr, len, &aligned_addr, &aligned_offset,
|
|
&aligned_len, &addr, &len, &addr_orig_next);
|
|
|
|
if (is_insert)
|
|
ret = aarch64_dr_state_insert_one_point (state, type, aligned_addr,
|
|
aligned_offset,
|
|
aligned_len, addr_orig);
|
|
else
|
|
ret = aarch64_dr_state_remove_one_point (state, type, aligned_addr,
|
|
aligned_offset,
|
|
aligned_len, addr_orig);
|
|
|
|
if (show_debug_regs)
|
|
debug_printf ("handle_unaligned_watchpoint: is_insert: %d\n"
|
|
" "
|
|
"aligned_addr: %s, aligned_len: %d\n"
|
|
" "
|
|
"addr_orig: %s\n"
|
|
" "
|
|
"next_addr: %s, next_len: %d\n"
|
|
" "
|
|
"addr_orig_next: %s\n",
|
|
is_insert, core_addr_to_string_nz (aligned_addr),
|
|
aligned_len, core_addr_to_string_nz (addr_orig),
|
|
core_addr_to_string_nz (addr), len,
|
|
core_addr_to_string_nz (addr_orig_next));
|
|
|
|
addr_orig = addr_orig_next;
|
|
|
|
if (ret != 0)
|
|
return ret;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
int
|
|
aarch64_handle_watchpoint (enum target_hw_bp_type type, CORE_ADDR addr,
|
|
int len, int is_insert,
|
|
struct aarch64_debug_reg_state *state)
|
|
{
|
|
if (aarch64_point_is_aligned (1 /* is_watchpoint */ , addr, len))
|
|
return aarch64_handle_aligned_watchpoint (type, addr, len, is_insert,
|
|
state);
|
|
else
|
|
return aarch64_handle_unaligned_watchpoint (type, addr, len, is_insert,
|
|
state);
|
|
}
|
|
|
|
/* Call ptrace to set the thread TID's hardware breakpoint/watchpoint
|
|
registers with data from *STATE. */
|
|
|
|
void
|
|
aarch64_linux_set_debug_regs (struct aarch64_debug_reg_state *state,
|
|
int tid, int watchpoint)
|
|
{
|
|
int i, count;
|
|
struct iovec iov;
|
|
struct user_hwdebug_state regs;
|
|
const CORE_ADDR *addr;
|
|
const unsigned int *ctrl;
|
|
|
|
memset (®s, 0, sizeof (regs));
|
|
iov.iov_base = ®s;
|
|
count = watchpoint ? aarch64_num_wp_regs : aarch64_num_bp_regs;
|
|
addr = watchpoint ? state->dr_addr_wp : state->dr_addr_bp;
|
|
ctrl = watchpoint ? state->dr_ctrl_wp : state->dr_ctrl_bp;
|
|
if (count == 0)
|
|
return;
|
|
iov.iov_len = (offsetof (struct user_hwdebug_state, dbg_regs)
|
|
+ count * sizeof (regs.dbg_regs[0]));
|
|
|
|
for (i = 0; i < count; i++)
|
|
{
|
|
regs.dbg_regs[i].addr = addr[i];
|
|
regs.dbg_regs[i].ctrl = ctrl[i];
|
|
}
|
|
|
|
if (ptrace (PTRACE_SETREGSET, tid,
|
|
watchpoint ? NT_ARM_HW_WATCH : NT_ARM_HW_BREAK,
|
|
(void *) &iov))
|
|
{
|
|
/* Handle Linux kernels with the PR external/20207 bug. */
|
|
if (watchpoint && errno == EINVAL
|
|
&& kernel_supports_any_contiguous_range)
|
|
{
|
|
kernel_supports_any_contiguous_range = false;
|
|
aarch64_downgrade_regs (state);
|
|
aarch64_linux_set_debug_regs (state, tid, watchpoint);
|
|
return;
|
|
}
|
|
error (_("Unexpected error setting hardware debug registers"));
|
|
}
|
|
}
|
|
|
|
/* See nat/aarch64-linux-hw-point.h. */
|
|
|
|
bool
|
|
aarch64_linux_any_set_debug_regs_state (aarch64_debug_reg_state *state,
|
|
bool watchpoint)
|
|
{
|
|
int count = watchpoint ? aarch64_num_wp_regs : aarch64_num_bp_regs;
|
|
if (count == 0)
|
|
return false;
|
|
|
|
const CORE_ADDR *addr = watchpoint ? state->dr_addr_wp : state->dr_addr_bp;
|
|
const unsigned int *ctrl = watchpoint ? state->dr_ctrl_wp : state->dr_ctrl_bp;
|
|
|
|
for (int i = 0; i < count; i++)
|
|
if (addr[i] != 0 || ctrl[i] != 0)
|
|
return true;
|
|
|
|
return false;
|
|
}
|
|
|
|
/* Print the values of the cached breakpoint/watchpoint registers. */
|
|
|
|
void
|
|
aarch64_show_debug_reg_state (struct aarch64_debug_reg_state *state,
|
|
const char *func, CORE_ADDR addr,
|
|
int len, enum target_hw_bp_type type)
|
|
{
|
|
int i;
|
|
|
|
debug_printf ("%s", func);
|
|
if (addr || len)
|
|
debug_printf (" (addr=0x%08lx, len=%d, type=%s)",
|
|
(unsigned long) addr, len,
|
|
type == hw_write ? "hw-write-watchpoint"
|
|
: (type == hw_read ? "hw-read-watchpoint"
|
|
: (type == hw_access ? "hw-access-watchpoint"
|
|
: (type == hw_execute ? "hw-breakpoint"
|
|
: "??unknown??"))));
|
|
debug_printf (":\n");
|
|
|
|
debug_printf ("\tBREAKPOINTs:\n");
|
|
for (i = 0; i < aarch64_num_bp_regs; i++)
|
|
debug_printf ("\tBP%d: addr=%s, ctrl=0x%08x, ref.count=%d\n",
|
|
i, core_addr_to_string_nz (state->dr_addr_bp[i]),
|
|
state->dr_ctrl_bp[i], state->dr_ref_count_bp[i]);
|
|
|
|
debug_printf ("\tWATCHPOINTs:\n");
|
|
for (i = 0; i < aarch64_num_wp_regs; i++)
|
|
debug_printf ("\tWP%d: addr=%s (orig=%s), ctrl=0x%08x, ref.count=%d\n",
|
|
i, core_addr_to_string_nz (state->dr_addr_wp[i]),
|
|
core_addr_to_string_nz (state->dr_addr_orig_wp[i]),
|
|
state->dr_ctrl_wp[i], state->dr_ref_count_wp[i]);
|
|
}
|
|
|
|
/* Get the hardware debug register capacity information from the
|
|
process represented by TID. */
|
|
|
|
void
|
|
aarch64_linux_get_debug_reg_capacity (int tid)
|
|
{
|
|
struct iovec iov;
|
|
struct user_hwdebug_state dreg_state;
|
|
|
|
iov.iov_base = &dreg_state;
|
|
iov.iov_len = sizeof (dreg_state);
|
|
|
|
/* Get hardware watchpoint register info. */
|
|
if (ptrace (PTRACE_GETREGSET, tid, NT_ARM_HW_WATCH, &iov) == 0
|
|
&& (AARCH64_DEBUG_ARCH (dreg_state.dbg_info) == AARCH64_DEBUG_ARCH_V8
|
|
|| AARCH64_DEBUG_ARCH (dreg_state.dbg_info) == AARCH64_DEBUG_ARCH_V8_1
|
|
|| AARCH64_DEBUG_ARCH (dreg_state.dbg_info) == AARCH64_DEBUG_ARCH_V8_2))
|
|
{
|
|
aarch64_num_wp_regs = AARCH64_DEBUG_NUM_SLOTS (dreg_state.dbg_info);
|
|
if (aarch64_num_wp_regs > AARCH64_HWP_MAX_NUM)
|
|
{
|
|
warning (_("Unexpected number of hardware watchpoint registers"
|
|
" reported by ptrace, got %d, expected %d."),
|
|
aarch64_num_wp_regs, AARCH64_HWP_MAX_NUM);
|
|
aarch64_num_wp_regs = AARCH64_HWP_MAX_NUM;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
warning (_("Unable to determine the number of hardware watchpoints"
|
|
" available."));
|
|
aarch64_num_wp_regs = 0;
|
|
}
|
|
|
|
/* Get hardware breakpoint register info. */
|
|
if (ptrace (PTRACE_GETREGSET, tid, NT_ARM_HW_BREAK, &iov) == 0
|
|
&& (AARCH64_DEBUG_ARCH (dreg_state.dbg_info) == AARCH64_DEBUG_ARCH_V8
|
|
|| AARCH64_DEBUG_ARCH (dreg_state.dbg_info) == AARCH64_DEBUG_ARCH_V8_1
|
|
|| AARCH64_DEBUG_ARCH (dreg_state.dbg_info) == AARCH64_DEBUG_ARCH_V8_2))
|
|
{
|
|
aarch64_num_bp_regs = AARCH64_DEBUG_NUM_SLOTS (dreg_state.dbg_info);
|
|
if (aarch64_num_bp_regs > AARCH64_HBP_MAX_NUM)
|
|
{
|
|
warning (_("Unexpected number of hardware breakpoint registers"
|
|
" reported by ptrace, got %d, expected %d."),
|
|
aarch64_num_bp_regs, AARCH64_HBP_MAX_NUM);
|
|
aarch64_num_bp_regs = AARCH64_HBP_MAX_NUM;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
warning (_("Unable to determine the number of hardware breakpoints"
|
|
" available."));
|
|
aarch64_num_bp_regs = 0;
|
|
}
|
|
}
|
|
|
|
/* Return true if we can watch a memory region that starts address
|
|
ADDR and whose length is LEN in bytes. */
|
|
|
|
int
|
|
aarch64_linux_region_ok_for_watchpoint (CORE_ADDR addr, int len)
|
|
{
|
|
CORE_ADDR aligned_addr;
|
|
|
|
/* Can not set watchpoints for zero or negative lengths. */
|
|
if (len <= 0)
|
|
return 0;
|
|
|
|
/* Must have hardware watchpoint debug register(s). */
|
|
if (aarch64_num_wp_regs == 0)
|
|
return 0;
|
|
|
|
/* We support unaligned watchpoint address and arbitrary length,
|
|
as long as the size of the whole watched area after alignment
|
|
doesn't exceed size of the total area that all watchpoint debug
|
|
registers can watch cooperatively.
|
|
|
|
This is a very relaxed rule, but unfortunately there are
|
|
limitations, e.g. false-positive hits, due to limited support of
|
|
hardware debug registers in the kernel. See comment above
|
|
aarch64_align_watchpoint for more information. */
|
|
|
|
aligned_addr = addr & ~(AARCH64_HWP_MAX_LEN_PER_REG - 1);
|
|
if (aligned_addr + aarch64_num_wp_regs * AARCH64_HWP_MAX_LEN_PER_REG
|
|
< addr + len)
|
|
return 0;
|
|
|
|
/* All tests passed so we are likely to be able to set the watchpoint.
|
|
The reason that it is 'likely' rather than 'must' is because
|
|
we don't check the current usage of the watchpoint registers, and
|
|
there may not be enough registers available for this watchpoint.
|
|
Ideally we should check the cached debug register state, however
|
|
the checking is costly. */
|
|
return 1;
|
|
}
|