317 lines
8.0 KiB
C
317 lines
8.0 KiB
C
/* Blackfin One-Time Programmable Memory (OTP) model
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Copyright (C) 2010-2013 Free Software Foundation, Inc.
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Contributed by Analog Devices, Inc.
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This file is part of simulators.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#include "config.h"
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#include "sim-main.h"
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#include "devices.h"
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#include "dv-bfin_otp.h"
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/* XXX: No public documentation on this interface. This seems to work
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with the on-chip ROM functions though and was figured out by
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disassembling & walking that code. */
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/* XXX: About only thing that should be done here are CRC fields. And
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supposedly there is an interrupt that could be generated. */
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struct bfin_otp
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{
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bu32 base;
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/* The actual OTP storage -- 0x200 pages, each page is 128bits.
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While certain pages have predefined and/or secure access, we don't
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bother trying to implement that coverage. All pages are open for
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reading & writing. */
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bu32 mem[0x200 * 4];
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/* Order after here is important -- matches hardware MMR layout. */
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bu16 BFIN_MMR_16(control);
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bu16 BFIN_MMR_16(ben);
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bu16 BFIN_MMR_16(status);
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bu32 timing;
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bu32 _pad0[28];
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bu32 data0, data1, data2, data3;
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};
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#define mmr_base() offsetof(struct bfin_otp, control)
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#define mmr_offset(mmr) (offsetof(struct bfin_otp, mmr) - mmr_base())
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#define mmr_idx(mmr) (mmr_offset (mmr) / 4)
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static const char * const mmr_names[] =
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{
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"OTP_CONTROL", "OTP_BEN", "OTP_STATUS", "OTP_TIMING",
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[mmr_idx (data0)] = "OTP_DATA0", "OTP_DATA1", "OTP_DATA2", "OTP_DATA3",
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};
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#define mmr_name(off) (mmr_names[(off) / 4] ? : "<INV>")
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/* XXX: This probably misbehaves with big endian hosts. */
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static void
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bfin_otp_transfer (struct bfin_otp *otp, void *vdst, void *vsrc)
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{
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bu8 *dst = vdst, *src = vsrc;
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int bidx;
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for (bidx = 0; bidx < 16; ++bidx)
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if (otp->ben & (1 << bidx))
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dst[bidx] = src[bidx];
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}
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static void
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bfin_otp_read_page (struct bfin_otp *otp, bu16 page)
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{
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bfin_otp_transfer (otp, &otp->data0, &otp->mem[page * 4]);
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}
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static void
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bfin_otp_write_page_val (struct bfin_otp *otp, bu16 page, bu64 val[2])
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{
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bfin_otp_transfer (otp, &otp->mem[page * 4], val);
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}
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static void
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bfin_otp_write_page_val2 (struct bfin_otp *otp, bu16 page, bu64 lo, bu64 hi)
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{
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bu64 val[2] = { lo, hi };
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bfin_otp_write_page_val (otp, page, val);
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}
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static void
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bfin_otp_write_page (struct bfin_otp *otp, bu16 page)
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{
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bfin_otp_write_page_val (otp, page, (void *)&otp->data0);
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}
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static unsigned
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bfin_otp_io_write_buffer (struct hw *me, const void *source, int space,
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address_word addr, unsigned nr_bytes)
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{
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struct bfin_otp *otp = hw_data (me);
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bu32 mmr_off;
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bu32 value;
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bu16 *value16p;
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bu32 *value32p;
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void *valuep;
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if (nr_bytes == 4)
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value = dv_load_4 (source);
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else
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value = dv_load_2 (source);
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mmr_off = addr - otp->base;
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valuep = (void *)((unsigned long)otp + mmr_base() + mmr_off);
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value16p = valuep;
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value32p = valuep;
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HW_TRACE_WRITE ();
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switch (mmr_off)
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{
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case mmr_offset(control):
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{
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int page;
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dv_bfin_mmr_require_16 (me, addr, nr_bytes, true);
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/* XXX: Seems like these bits aren't writable. */
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*value16p = value & 0x39FF;
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/* Low bits seem to be the page address. */
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page = value & PAGE_ADDR;
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/* Write operation. */
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if (value & DO_WRITE)
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bfin_otp_write_page (otp, page);
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/* Read operation. */
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if (value & DO_READ)
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bfin_otp_read_page (otp, page);
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otp->status |= STATUS_DONE;
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break;
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}
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case mmr_offset(ben):
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dv_bfin_mmr_require_16 (me, addr, nr_bytes, true);
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/* XXX: All bits seem to be writable. */
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*value16p = value;
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break;
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case mmr_offset(status):
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dv_bfin_mmr_require_16 (me, addr, nr_bytes, true);
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/* XXX: All bits seem to be W1C. */
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dv_w1c_2 (value16p, value, -1);
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break;
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case mmr_offset(timing):
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case mmr_offset(data0):
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case mmr_offset(data1):
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case mmr_offset(data2):
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case mmr_offset(data3):
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dv_bfin_mmr_require_32 (me, addr, nr_bytes, true);
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*value32p = value;
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break;
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default:
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dv_bfin_mmr_invalid (me, addr, nr_bytes, true);
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break;
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}
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return nr_bytes;
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}
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static unsigned
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bfin_otp_io_read_buffer (struct hw *me, void *dest, int space,
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address_word addr, unsigned nr_bytes)
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{
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struct bfin_otp *otp = hw_data (me);
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bu32 mmr_off;
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bu16 *value16p;
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bu32 *value32p;
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void *valuep;
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mmr_off = addr - otp->base;
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valuep = (void *)((unsigned long)otp + mmr_base() + mmr_off);
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value16p = valuep;
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value32p = valuep;
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HW_TRACE_READ ();
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switch (mmr_off)
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{
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case mmr_offset(control):
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case mmr_offset(ben):
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case mmr_offset(status):
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dv_bfin_mmr_require_16 (me, addr, nr_bytes, false);
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dv_store_2 (dest, *value16p);
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break;
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case mmr_offset(timing):
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case mmr_offset(data0):
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case mmr_offset(data1):
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case mmr_offset(data2):
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case mmr_offset(data3):
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dv_bfin_mmr_require_32 (me, addr, nr_bytes, false);
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dv_store_4 (dest, *value32p);
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break;
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default:
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dv_bfin_mmr_invalid (me, addr, nr_bytes, false);
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break;
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}
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return nr_bytes;
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}
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static void
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attach_bfin_otp_regs (struct hw *me, struct bfin_otp *otp)
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{
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address_word attach_address;
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int attach_space;
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unsigned attach_size;
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reg_property_spec reg;
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if (hw_find_property (me, "reg") == NULL)
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hw_abort (me, "Missing \"reg\" property");
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if (!hw_find_reg_array_property (me, "reg", 0, ®))
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hw_abort (me, "\"reg\" property must contain three addr/size entries");
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hw_unit_address_to_attach_address (hw_parent (me),
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®.address,
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&attach_space, &attach_address, me);
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hw_unit_size_to_attach_size (hw_parent (me), ®.size, &attach_size, me);
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if (attach_size != BFIN_MMR_OTP_SIZE)
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hw_abort (me, "\"reg\" size must be %#x", BFIN_MMR_OTP_SIZE);
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hw_attach_address (hw_parent (me),
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0, attach_space, attach_address, attach_size, me);
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otp->base = attach_address;
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}
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static const struct hw_port_descriptor bfin_otp_ports[] =
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{
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{ "stat", 0, 0, output_port, },
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{ NULL, 0, 0, 0, },
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};
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static void
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bfin_otp_finish (struct hw *me)
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{
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char part_str[16];
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struct bfin_otp *otp;
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unsigned int fps03;
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int type = hw_find_integer_property (me, "type");
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otp = HW_ZALLOC (me, struct bfin_otp);
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set_hw_data (me, otp);
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set_hw_io_read_buffer (me, bfin_otp_io_read_buffer);
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set_hw_io_write_buffer (me, bfin_otp_io_write_buffer);
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set_hw_ports (me, bfin_otp_ports);
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attach_bfin_otp_regs (me, otp);
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/* Initialize the OTP. */
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otp->ben = 0xFFFF;
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otp->timing = 0x00001485;
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/* Semi-random value for unique chip id. */
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bfin_otp_write_page_val2 (otp, FPS00, (unsigned long)otp, ~(unsigned long)otp);
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memset (part_str, 0, sizeof (part_str));
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sprintf (part_str, "ADSP-BF%iX", type);
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switch (type)
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{
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case 512:
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fps03 = FPS03_BF512;
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break;
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case 514:
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fps03 = FPS03_BF514;
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break;
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case 516:
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fps03 = FPS03_BF516;
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break;
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case 518:
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fps03 = FPS03_BF518;
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break;
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case 522:
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fps03 = FPS03_BF522;
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break;
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case 523:
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fps03 = FPS03_BF523;
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break;
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case 524:
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fps03 = FPS03_BF524;
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break;
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case 525:
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fps03 = FPS03_BF525;
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break;
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case 526:
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fps03 = FPS03_BF526;
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break;
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case 527:
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fps03 = FPS03_BF527;
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break;
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default:
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fps03 = 0;
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break;
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}
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part_str[14] = (fps03 >> 0);
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part_str[15] = (fps03 >> 8);
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bfin_otp_write_page_val (otp, FPS03, (void *)part_str);
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}
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const struct hw_descriptor dv_bfin_otp_descriptor[] =
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{
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{"bfin_otp", bfin_otp_finish,},
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{NULL, NULL},
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};
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