Nick Clifton faf766e317 Add note about 2.30 branch creation to changelogs

2018-01-13 13:26:38 +00:00

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ChangeLog

Add note about 2.30 branch creation to changelogs

2018-01-13 13:26:38 +00:00

cris.cpu

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epiphany.cpu

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epiphany.opc

epiphany/disassembler: Improve alignment of output.

2016-02-02 11:09:17 +00:00

fr30.cpu

Correct fr30 comment

2016-03-03 12:55:30 +10:30

fr30.opc

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frv.cpu

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frv.opc

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ip2k.cpu

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ip2k.opc

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iq10.cpu

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iq2000.cpu

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iq2000.opc

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iq2000m.cpu

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lm32.cpu

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lm32.opc

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m32c.cpu

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m32c.opc

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m32r.cpu

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m32r.opc

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mep-avc2.cpu

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mep-avc.cpu

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mep-c5.cpu

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mep-core.cpu

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mep-default.cpu

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mep-ext-cop.cpu

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mep-fmax.cpu

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mep-h1.cpu

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mep-ivc2.cpu

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mep-rhcop.cpu

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mep-sample-ucidsp.cpu

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mep.cpu

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mep.opc

Add fall through comment to source in cpu/

2016-10-06 22:48:37 +10:30

mt.cpu

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mt.opc

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or1k.cpu

Remove support for the (deprecated) openrisc and or32 configurations and replace

2014-04-22 15:57:47 +01:00

or1k.opc

Whitespace fixes for cpu/or1k.opc

2014-06-12 12:30:57 +09:30

or1kcommon.cpu

Update the openrisc previous program counter (ppc) when running code in the cgen based simulator.

2017-03-20 15:33:51 +00:00

or1korbis.cpu

or1k: add missing l.msync, l.psync and l.psync instructions.

2014-07-20 20:26:09 +03:00

or1korfpx.cpu

Remove support for the (deprecated) openrisc and or32 configurations and replace

2014-04-22 15:57:47 +01:00

sh64-compact.cpu

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sh64-media.cpu

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sh.cpu

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sh.opc

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simplify.inc

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xc16x.cpu

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xc16x.opc

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xstormy16.cpu

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xstormy16.opc

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