250 lines
7.5 KiB
C
250 lines
7.5 KiB
C
/* Mitsubishi Electric Corp. D30V Simulator.
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Copyright (C) 1997, Free Software Foundation, Inc.
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Contributed by Cygnus Support.
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This file is part of GDB, the GNU debugger.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2, or (at your option)
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any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License along
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with this program; if not, write to the Free Software Foundation, Inc.,
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59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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#ifndef _CPU_H_
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#define _CPU_H_
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enum {
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NR_GENERAL_PURPOSE_REGISTERS = 64,
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NR_CONTROL_REGISTERS = 64,
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NR_ACCUMULATORS = 2,
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STACK_POINTER_GPR = 63,
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NR_STACK_POINTERS = 2,
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};
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enum {
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processor_status_word_cr = 0,
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backup_processor_status_word_cr = 1,
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program_counter_cr = 2,
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backup_program_counter_cr = 3,
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debug_backup_processor_status_word_cr = 4,
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debug_backup_program_counter_cr = 5,
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reserved_6_cr = 6,
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repeat_count_cr = 7,
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repeat_start_address_cr = 8,
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repeat_end_address_cr = 9,
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modulo_start_address_cr = 10,
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modulo_end_address_cr = 11,
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instruction_break_address_cr = 14,
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eit_vector_base_cr = 15,
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};
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enum {
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PSW_SM = 0,
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PSW_EA = 2,
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PSW_DB = 3,
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PSW_DS = 4,
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PSW_IE = 5,
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PSW_RP = 6,
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PSW_MD = 7,
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PSW_F0 = 17,
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PSW_F1 = 19,
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PSW_F2 = 21,
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PSW_F3 = 23,
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PSW_S = 25,
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PSW_V = 27,
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PSW_VA = 29,
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PSW_C = 31,
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};
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/* aliases for PSW flag numbers (F0..F7) */
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enum
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{
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PSW_S_FLAG = 4,
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};
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typedef struct _registers {
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unsigned32 general_purpose[NR_GENERAL_PURPOSE_REGISTERS];
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/* keep track of the stack pointer */
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unsigned32 sp[NR_STACK_POINTERS]; /* swap with SP */
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unsigned32 current_sp;
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unsigned32 control[NR_CONTROL_REGISTERS];
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unsigned64 accumulator[NR_ACCUMULATORS];
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} registers;
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typedef enum _cpu_units {
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memory_unit,
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integer_unit,
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any_unit,
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} cpu_units;
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/* In order to support parallel instructions, which one instruction can be
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writing to a register that is used as input to another, queue up the
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writes to the end of the instruction boundaries. */
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#define MAX_WRITE32 16
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#define MAX_WRITE64 2
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struct _write32 {
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int num; /* # of 32-bit writes queued up */
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unsigned32 value[MAX_WRITE32]; /* value to write */
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unsigned32 mask[MAX_WRITE32]; /* mask to use */
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unsigned32 *ptr[MAX_WRITE32]; /* address to write to */
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};
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struct _write64 {
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int num; /* # of 64-bit writes queued up */
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unsigned64 value[MAX_WRITE64]; /* value to write */
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unsigned64 *ptr[MAX_WRITE64]; /* address to write to */
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};
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struct _sim_cpu {
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cpu_units unit;
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registers regs;
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sim_cpu_base base;
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int trace_call_p; /* Whether to do call tracing. */
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int trace_trap_p; /* If unknown traps dump out the regs */
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int trace_action; /* trace bits at end of instructions */
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int left_kills_right_p; /* left insn kills insn in right slot of -> */
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int mvtsys_left_p; /* left insn was mvtsys */
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int did_trap; /* we did a trap & need to finish it */
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struct _write32 write32; /* queued up 32-bit writes */
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struct _write64 write64; /* queued up 64-bit writes */
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};
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#define PC (STATE_CPU (sd, 0)->regs.control[program_counter_cr])
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#define PSW (STATE_CPU (sd, 0)->regs.control[processor_status_word_cr])
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#define PSWL (*AL2_4(&PSW))
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#define PSWH (*AH2_4(&PSW))
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#define DPSW (STATE_CPU (sd, 0)->regs.control[debug_backup_processor_status_word_cr])
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#define DPC (STATE_CPU (sd, 0)->regs.control[debug_backup_program_counter_cr])
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#define bPC (STATE_CPU (sd, 0)->regs.control[backup_program_counter_cr])
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#define bPSW (STATE_CPU (sd, 0)->regs.control[backup_processor_status_word_cr])
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#define RPT_C (STATE_CPU (sd, 0)->regs.control[repeat_count_cr])
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#define RPT_S (STATE_CPU (sd, 0)->regs.control[repeat_start_address_cr])
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#define RPT_E (STATE_CPU (sd, 0)->regs.control[repeat_end_address_cr])
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#define MOD_S (STATE_CPU (sd, 0)->regs.control[modulo_start_address_cr])
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#define MOD_E (STATE_CPU (sd, 0)->regs.control[modulo_end_address_cr])
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#define IBA (STATE_CPU (sd, 0)->regs.control[instruction_break_address_cr])
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#define EIT_VB (STATE_CPU (sd, 0)->regs.control[eit_vector_base_cr])
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#define GPR (STATE_CPU (sd, 0)->regs.general_purpose)
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#define GPR_SET(N,VAL) (GPR[(N)] = (VAL))
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#define ACC (STATE_CPU (sd, 0)->regs.accumulator)
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#define CREG (STATE_CPU (sd, 0)->regs.control)
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#define SP (GPR[STACK_POINTER_GPR])
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#define TRACE_CALL_P (STATE_CPU (sd, 0)->trace_call_p)
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#define TRACE_TRAP_P (STATE_CPU (sd, 0)->trace_trap_p)
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#define TRACE_ACTION (STATE_CPU (sd, 0)->trace_action)
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#define TRACE_ACTION_CALL 0x00000001 /* call occurred */
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#define TRACE_ACTION_RETURN 0x00000002 /* return occurred */
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#define WRITE32 (STATE_CPU (sd, 0)->write32)
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#define WRITE32_NUM (WRITE32.num)
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#define WRITE32_PTR(N) (WRITE32.ptr[N])
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#define WRITE32_MASK(N) (WRITE32.mask[N])
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#define WRITE32_VALUE(N) (WRITE32.value[N])
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#define WRITE32_QUEUE(PTR, VALUE) WRITE32_QUEUE_MASK (PTR, VALUE, 0xffffffff)
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#define WRITE32_QUEUE_MASK(PTR, VALUE, MASK) \
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do { \
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int _num = WRITE32_NUM; \
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if (_num >= MAX_WRITE32) \
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sim_engine_abort (sd, STATE_CPU (sd, 0), cia, \
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"Too many queued 32-bit writes"); \
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WRITE32_PTR(_num) = PTR; \
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WRITE32_VALUE(_num) = VALUE; \
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WRITE32_MASK(_num) = MASK; \
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WRITE32_NUM = _num+1; \
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} while (0)
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#define DID_TRAP (STATE_CPU (sd, 0)->did_trap)
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#define WRITE64 (STATE_CPU (sd, 0)->write64)
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#define WRITE64_NUM (WRITE64.num)
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#define WRITE64_PTR(N) (WRITE64.ptr[N])
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#define WRITE64_VALUE(N) (WRITE64.value[N])
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#define WRITE64_QUEUE(PTR, VALUE) \
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do { \
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int _num = WRITE64_NUM; \
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if (_num >= MAX_WRITE64) \
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sim_engine_abort (sd, STATE_CPU (sd, 0), cia, \
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"Too many queued 64-bit writes"); \
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WRITE64_PTR(_num) = PTR; \
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WRITE64_VALUE(_num) = VALUE; \
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WRITE64_NUM = _num+1; \
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} while (0)
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#define DPSW_VALID 0xbf005555
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#define PSW_VALID 0xb7005555
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#define EIT_VALID 0xfffff000 /* From page 7-4 of D30V/MPEG arch. manual */
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#define EIT_VB_DEFAULT 0xfffff000 /* Value of the EIT_VB register after reset */
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/* Verify that the instruction is in the correct slot */
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#define IS_WRONG_SLOT is_wrong_slot(sd, cia, MY_INDEX)
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extern int is_wrong_slot
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(SIM_DESC sd,
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address_word cia,
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itable_index index);
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#define IS_CONDITION_OK is_condition_ok(sd, cia, CCC)
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extern int is_condition_ok
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(SIM_DESC sd,
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address_word cia,
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int cond);
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#define SIM_HAVE_BREAKPOINTS /* Turn on internal breakpoint module */
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/* Internal breakpoint instruction is syscall 5 */
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#define SIM_BREAKPOINT {0x0e, 0x00, 0x00, 0x05}
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#define SIM_BREAKPOINT_SIZE (4)
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/* Call occurred */
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extern void call_occurred
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(SIM_DESC sd,
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sim_cpu *cpu,
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address_word cia,
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address_word nia);
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/* Return occurred */
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extern void return_occurred
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(SIM_DESC sd,
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sim_cpu *cpu,
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address_word cia,
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address_word nia);
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/* Whether to do call tracing. */
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extern int d30v_call_trace_p;
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/* Read/write functions for system call interface. */
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extern int d30v_read_mem
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(host_callback *cb,
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struct cb_syscall *sc,
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unsigned long taddr,
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char *buf,
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int bytes);
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extern int d30v_write_mem
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(host_callback *cb,
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struct cb_syscall *sc,
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unsigned long taddr,
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const char *buf,
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int bytes);
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/* Process all of the queued up writes in order now */
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void unqueue_writes
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(SIM_DESC sd,
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sim_cpu *cpu,
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address_word cia);
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#endif /* _CPU_H_ */
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