631 lines
17 KiB
C
631 lines
17 KiB
C
/* Disassembler for the PA-RISC. Somewhat derived from sparc-pinsn.c.
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Copyright 1989, 1990, 1992, 1993 Free Software Foundation, Inc.
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Contributed by the Center for Software Science at the
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University of Utah (pa-gdb-bugs@cs.utah.edu).
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
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#include <ansidecl.h>
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#include "sysdep.h"
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#include "dis-asm.h"
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#include "opcode/hppa.h"
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/* Initializer for an array of names of registers.
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There should be NUM_REGS strings in this initializer. */
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#define REGISTER_NAMES \
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{"flags", "r1", "rp", "r3", "r4", "r5", "r6", "r7", "r8", "r9", \
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"r10", "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", \
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"r20", "r21", "r22", "arg3", "arg2", "arg1", "arg0", "dp", "ret0", "ret1", \
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"sp", "r31", "sar", "pcoqh", "pcsqh", "pcoqt", "pcsqt", \
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"eiem", "iir", "isr", "ior", "ipsw", "goto", "sr4", "sr0", "sr1", "sr2", \
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"sr3", "sr5", "sr6", "sr7", "cr0", "cr8", "cr9", "ccr", "cr12", "cr13", \
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"cr24", "cr25", "cr26", "mpsfu_high", "mpsfu_low", "mpsfu_ovflo", "pad", \
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"fpsr", "fpe1", "fpe2", "fpe3", "fpe4", "fpe5", "fpe6", "fpe7", \
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"fp4", "fp5", "fp6", "fp7", "fp8", \
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"fp9", "fp10", "fp11", "fp12", "fp13", "fp14", "fp15", \
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"fp16", "fp17", "fp18", "fp19", "fp20", "fp21", "fp22", "fp23", \
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"fp24", "fp25", "fp26", "fp27", "fp28", "fp29", "fp30", "fp31"}
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static const char *const reg_names[] = REGISTER_NAMES;
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typedef unsigned int CORE_ADDR;
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/* Get at various relevent fields of an instruction word. */
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#define MASK_5 0x1f
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#define MASK_11 0x7ff
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#define MASK_14 0x3fff
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#define MASK_21 0x1fffff
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/* This macro gets bit fields using HP's numbering (MSB = 0) */
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#define GET_FIELD(X, FROM, TO) \
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((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1))
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/* Some of these have been converted to 2-d arrays because they
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consume less storage this way. If the maintenance becomes a
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problem, convert them back to const 1-d pointer arrays. */
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static const char control_reg[][6] = {
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"rctr", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7",
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"pidr1", "pidr2", "ccr", "sar", "pidr3", "pidr4",
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"iva", "eiem", "itmr", "pcsq", "pcoq", "iir", "isr",
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"ior", "ipsw", "eirr", "tr0", "tr1", "tr2", "tr3",
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"tr4", "tr5", "tr6", "tr7"
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};
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static const char compare_cond_names[][5] = {
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"", ",=", ",<", ",<=", ",<<", ",<<=", ",sv",
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",od", ",tr", ",<>", ",>=", ",>", ",>>=",
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",>>", ",nsv", ",ev"
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};
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static const char add_cond_names[][5] = {
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"", ",=", ",<", ",<=", ",nuv", ",znv", ",sv",
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",od", ",tr", ",<>", ",>=", ",>", ",uv",
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",vnz", ",nsv", ",ev"
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};
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static const char *const logical_cond_names[] = {
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"", ",=", ",<", ",<=", 0, 0, 0, ",od",
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",tr", ",<>", ",>=", ",>", 0, 0, 0, ",ev"};
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static const char *const unit_cond_names[] = {
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"", 0, ",sbz", ",shz", ",sdc", 0, ",sbc", ",shc",
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",tr", 0, ",nbz", ",nhz", ",ndc", 0, ",nbc", ",nhc"
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};
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static const char shift_cond_names[][4] = {
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"", ",=", ",<", ",od", ",tr", ",<>", ",>=", ",ev"
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};
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static const char index_compl_names[][4] = {"", ",m", ",s", ",sm"};
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static const char short_ldst_compl_names[][4] = {"", ",ma", "", ",mb"};
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static const char *const short_bytes_compl_names[] = {
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"", ",b,m", ",e", ",e,m"
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};
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static const char *const float_format_names[] = {",sgl", ",dbl", "", ",quad"};
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static const char float_comp_names[][8] =
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{
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",false?", ",false", ",?", ",!<=>", ",=", ",=t", ",?=", ",!<>",
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",!?>=", ",<", ",?<", ",!>=", ",!?>", ",<=", ",?<=", ",!>",
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",!?<=", ",>", ",?>", ",!<=", ",!?<", ",>=", ",?>=", ",!<",
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",!?=", ",<>", ",!=", ",!=t", ",!?", ",<=>", ",true?", ",true"
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};
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/* For a bunch of different instructions form an index into a
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completer name table. */
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#define GET_COMPL(insn) (GET_FIELD (insn, 26, 26) | \
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GET_FIELD (insn, 18, 18) << 1)
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#define GET_COND(insn) (GET_FIELD ((insn), 16, 18) + \
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(GET_FIELD ((insn), 19, 19) ? 8 : 0))
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/* Utility function to print registers. Put these first, so gcc's function
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inlining can do its stuff. */
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#define fputs_filtered(STR,F) (*info->fprintf_func) (info->stream, "%s", STR)
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static void
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fput_reg (reg, info)
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unsigned reg;
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disassemble_info *info;
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{
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(*info->fprintf_func) (info->stream, reg ? reg_names[reg] : "r0");
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}
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static void
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fput_reg_r (reg, info)
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unsigned reg;
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disassemble_info *info;
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{
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(*info->fprintf_func) (info->stream, "%sR", reg ? reg_names[reg] : "r0");
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}
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static void
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fput_creg (reg, info)
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unsigned reg;
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disassemble_info *info;
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{
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(*info->fprintf_func) (info->stream, control_reg[reg]);
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}
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/* print constants with sign */
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static void
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fput_const (num, info)
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unsigned num;
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disassemble_info *info;
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{
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if ((int)num < 0)
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(*info->fprintf_func) (info->stream, "-%x", -(int)num);
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else
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(*info->fprintf_func) (info->stream, "%x", num);
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}
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/* Routines to extract various sized constants out of hppa
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instructions. */
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/* This assumes that no garbage lies outside of the lower bits of
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value. */
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static int
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sign_extend (val, bits)
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unsigned val, bits;
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{
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return (int)(val >> (bits - 1) ? (-1 << bits) | val : val);
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}
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/* For many immediate values the sign bit is the low bit! */
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static int
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low_sign_extend (val, bits)
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unsigned val, bits;
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{
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return (int)((val & 0x1 ? (-1 << (bits - 1)) : 0) | val >> 1);
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}
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/* extract the immediate field from a ld{bhw}s instruction */
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#if 0 /* not used */
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static unsigned
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get_field (val, from, to)
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unsigned val, from, to;
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{
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val = val >> (31 - to);
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return val & ((1 << (32 - from)) - 1);
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}
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static unsigned
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set_field (val, from, to, new_val)
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unsigned *val, from, to, new_val;
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{
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unsigned mask = ~((1 << (to - from + 1)) << (31 - from));
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return *val = (*val & mask) | (new_val << (31 - from));
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}
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#endif
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/* extract a 3-bit space register number from a be, ble, mtsp or mfsp */
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static int
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extract_3 (word)
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unsigned word;
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{
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return GET_FIELD (word, 18, 18) << 2 | GET_FIELD (word, 16, 17);
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}
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static int
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extract_5_load (word)
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unsigned word;
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{
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return low_sign_extend (word >> 16 & MASK_5, 5);
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}
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/* extract the immediate field from a st{bhw}s instruction */
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static int
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extract_5_store (word)
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unsigned word;
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{
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return low_sign_extend (word & MASK_5, 5);
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}
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/* extract the immediate field from a break instruction */
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static unsigned
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extract_5r_store (word)
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unsigned word;
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{
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return (word & MASK_5);
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}
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/* extract the immediate field from a {sr}sm instruction */
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static unsigned
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extract_5R_store (word)
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unsigned word;
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{
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return (word >> 16 & MASK_5);
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}
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/* extract the immediate field from a bb instruction */
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static unsigned
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extract_5Q_store (word)
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unsigned word;
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{
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return (word >> 21 & MASK_5);
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}
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/* extract an 11 bit immediate field */
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static int
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extract_11 (word)
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unsigned word;
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{
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return low_sign_extend (word & MASK_11, 11);
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}
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/* extract a 14 bit immediate field */
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static int
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extract_14 (word)
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unsigned word;
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{
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return low_sign_extend (word & MASK_14, 14);
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}
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#if 0
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/* deposit a 14 bit constant in a word */
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static unsigned
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deposit_14 (opnd, word)
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int opnd;
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unsigned word;
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{
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unsigned sign = (opnd < 0 ? 1 : 0);
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return word | ((unsigned)opnd << 1 & MASK_14) | sign;
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}
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#endif
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/* extract a 21 bit constant */
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static int
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extract_21 (word)
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unsigned word;
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{
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int val;
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word &= MASK_21;
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word <<= 11;
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val = GET_FIELD (word, 20, 20);
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val <<= 11;
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val |= GET_FIELD (word, 9, 19);
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val <<= 2;
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val |= GET_FIELD (word, 5, 6);
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val <<= 5;
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val |= GET_FIELD (word, 0, 4);
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val <<= 2;
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val |= GET_FIELD (word, 7, 8);
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return sign_extend (val, 21) << 11;
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}
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#if 0
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/* deposit a 21 bit constant in a word. Although 21 bit constants are
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usually the top 21 bits of a 32 bit constant, we assume that only
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the low 21 bits of opnd are relevant */
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static unsigned
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deposit_21 (opnd, word)
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unsigned opnd, word;
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{
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unsigned val = 0;
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val |= GET_FIELD (opnd, 11 + 14, 11 + 18);
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val <<= 2;
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val |= GET_FIELD (opnd, 11 + 12, 11 + 13);
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val <<= 2;
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val |= GET_FIELD (opnd, 11 + 19, 11 + 20);
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val <<= 11;
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val |= GET_FIELD (opnd, 11 + 1, 11 + 11);
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val <<= 1;
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val |= GET_FIELD (opnd, 11 + 0, 11 + 0);
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return word | val;
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}
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#endif
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/* extract a 12 bit constant from branch instructions */
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static int
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extract_12 (word)
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unsigned word;
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{
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return sign_extend (GET_FIELD (word, 19, 28) |
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GET_FIELD (word, 29, 29) << 10 |
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(word & 0x1) << 11, 12) << 2;
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}
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/* extract a 17 bit constant from branch instructions, returning the
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19 bit signed value. */
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static int
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extract_17 (word)
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unsigned word;
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{
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return sign_extend (GET_FIELD (word, 19, 28) |
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GET_FIELD (word, 29, 29) << 10 |
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GET_FIELD (word, 11, 15) << 11 |
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(word & 0x1) << 16, 17) << 2;
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}
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/* Print one instruction. */
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int
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print_insn_hppa (memaddr, info)
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bfd_vma memaddr;
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disassemble_info *info;
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{
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unsigned int insn, i, op;
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FILE *stream = info->stream;
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{
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int status =
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(*info->read_memory_func) (memaddr, (bfd_byte*) &insn, sizeof (insn),
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info);
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if (status != 0)
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{
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(*info->memory_error_func) (status, memaddr, info);
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return -1;
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}
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}
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for (i = 0; i < NUMOPCODES; ++i)
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{
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const struct pa_opcode *opcode = &pa_opcodes[i];
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if ((insn & opcode->mask) == opcode->match)
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{
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register const char *s;
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(*info->fprintf_func) (info->stream, "%s", opcode->name);
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if (!strchr ("cCY<?!@-+&U>~nZFIMad", opcode->args[0]))
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(*info->fprintf_func) (info->stream, " ");
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for (s = opcode->args; *s != '\0'; ++s)
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{
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switch (*s)
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{
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case 'x':
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fput_reg (GET_FIELD (insn, 11, 15), info);
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break;
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case 'X':
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if (GET_FIELD (insn, 25, 25))
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fput_reg_r (GET_FIELD (insn, 11, 15), info);
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else
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fput_reg (GET_FIELD (insn, 11, 15), info);
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break;
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case 'b':
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fput_reg (GET_FIELD (insn, 6, 10), info);
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break;
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case '^':
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fput_creg (GET_FIELD (insn, 6, 10), info);
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break;
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case 'E':
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if (GET_FIELD (insn, 25, 25))
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fput_reg_r (GET_FIELD (insn, 6, 10), info);
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else
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fput_reg (GET_FIELD (insn, 6, 10), info);
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break;
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case 't':
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fput_reg (GET_FIELD (insn, 27, 31), info);
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break;
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case 'v':
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if (GET_FIELD (insn, 25, 25))
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fput_reg_r (GET_FIELD (insn, 27, 31), info);
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else
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fput_reg (GET_FIELD (insn, 27, 31), info);
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break;
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case '4':
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fput_creg (GET_FIELD (insn, 6, 10), info);
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break;
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case '6':
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fput_reg (GET_FIELD (insn, 11, 15), info);
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break;
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case '7':
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fput_reg (GET_FIELD (insn, 27, 31), info);
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break;
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case '8':
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fput_reg (GET_FIELD (insn, 16, 20), info);
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break;
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case '9':
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fput_reg (GET_FIELD (insn, 21, 25), info);
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break;
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case '5':
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fput_const (extract_5_load (insn), info);
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break;
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case 's':
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fprintf_filtered (stream, "sr%d", GET_FIELD (insn, 16, 17));
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break;
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case 'S':
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(*info->fprintf_func) (info->stream, "sr%d", extract_3 (insn));
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break;
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case 'c':
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(*info->fprintf_func) (info->stream, "%s ",
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index_compl_names[GET_COMPL (insn)]);
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break;
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case 'C':
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(*info->fprintf_func) (info->stream, "%s ",
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short_ldst_compl_names[GET_COMPL (insn)]);
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break;
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case 'Y':
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(*info->fprintf_func) (info->stream, "%s ",
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short_bytes_compl_names[GET_COMPL (insn)]);
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break;
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/* these four conditions are for the set of instructions
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which distinguish true/false conditions by opcode rather
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than by the 'f' bit (sigh): comb, comib, addb, addib */
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case '<':
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fputs_filtered (compare_cond_names[GET_FIELD (insn, 16, 18)],
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info);
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break;
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case '?':
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fputs_filtered (compare_cond_names[GET_FIELD (insn, 16, 18) + 8],
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info);
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break;
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case '@':
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fputs_filtered (add_cond_names[GET_FIELD (insn, 16, 18) + 8],
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info);
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break;
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case 'a':
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(*info->fprintf_func) (info->stream, "%s",
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compare_cond_names[GET_COND (insn)]);
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break;
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case 'd':
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case '!':
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(*info->fprintf_func) (info->stream, "%s",
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add_cond_names[GET_FIELD (insn, 16, 18)]);
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break;
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case '&':
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(*info->fprintf_func) (info->stream, "%s ",
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logical_cond_names[GET_COND (insn)]);
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break;
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case 'U':
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(*info->fprintf_func) (info->stream, "%s ",
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unit_cond_names[GET_COND (insn)]);
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break;
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case '>':
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case '~':
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(*info->fprintf_func)
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(info->stream, "%s",
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shift_cond_names[GET_FIELD (insn, 16, 18)]);
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|
|
/* If the next character in args is 'n', it will handle
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putting out the space. */
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if (s[1] != 'n')
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(*info->fprintf_func) (info->stream, " ");
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break;
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case 'V':
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fput_const (extract_5_store (insn), info);
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break;
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case 'R':
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fput_const (extract_5R_store (insn), info);
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break;
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case 'Q':
|
|
fput_const (extract_5Q_store (insn), info);
|
|
break;
|
|
case 'i':
|
|
fput_const (extract_11 (insn), info);
|
|
break;
|
|
case 'j':
|
|
fput_const (extract_14 (insn), info);
|
|
break;
|
|
case 'k':
|
|
fput_const (extract_21 (insn), info);
|
|
break;
|
|
case 'n':
|
|
if (insn & 0x2)
|
|
(*info->fprintf_func) (info->stream, ",n ");
|
|
else
|
|
(*info->fprintf_func) (info->stream, " ");
|
|
break;
|
|
case 'w':
|
|
(*info->print_address_func) (memaddr + 8 + extract_12 (insn),
|
|
info);
|
|
break;
|
|
case 'W':
|
|
/* don't interpret an address if it's an external branch
|
|
instruction. */
|
|
op = GET_FIELD (insn, 0, 5);
|
|
if (op != 0x38 /* be */ && op != 0x39 /* ble */)
|
|
(*info->print_address_func) ((memaddr + 8
|
|
+ extract_17 (insn)),
|
|
info);
|
|
else
|
|
fput_const (extract_17 (insn), info);
|
|
break;
|
|
case 'p':
|
|
(*info->fprintf_func) (info->stream, "%d",
|
|
31 - GET_FIELD (insn, 22, 26));
|
|
break;
|
|
case 'P':
|
|
(*info->fprintf_func) (info->stream, "%d",
|
|
GET_FIELD (insn, 22, 26));
|
|
break;
|
|
case 'T':
|
|
(*info->fprintf_func) (info->stream, "%d",
|
|
32 - GET_FIELD (insn, 27, 31));
|
|
break;
|
|
case 'A':
|
|
fput_const (GET_FIELD (insn, 6, 18), info);
|
|
break;
|
|
case 'Z':
|
|
if (GET_FIELD (insn, 26, 26))
|
|
(*info->fprintf_func) (info->stream, ",m ");
|
|
else
|
|
(*info->fprintf_func) (info->stream, " ");
|
|
break;
|
|
case 'D':
|
|
fput_const (GET_FIELD (insn, 6, 31), info);
|
|
break;
|
|
case 'f':
|
|
(*info->fprintf_func) (info->stream, ",%d", GET_FIELD (insn, 23, 25));
|
|
break;
|
|
case 'O':
|
|
fput_const ((GET_FIELD (insn, 6,20) << 5 |
|
|
GET_FIELD (insn, 27, 31)), info);
|
|
break;
|
|
case 'o':
|
|
fput_const (GET_FIELD (insn, 6, 20), info);
|
|
break;
|
|
case '2':
|
|
fput_const ((GET_FIELD (insn, 6, 22) << 5 |
|
|
GET_FIELD (insn, 27, 31)), info);
|
|
break;
|
|
case '1':
|
|
fput_const ((GET_FIELD (insn, 11, 20) << 5 |
|
|
GET_FIELD (insn, 27, 31)), info);
|
|
break;
|
|
case '0':
|
|
fput_const ((GET_FIELD (insn, 16, 20) << 5 |
|
|
GET_FIELD (insn, 27, 31)), info);
|
|
break;
|
|
case 'u':
|
|
(*info->fprintf_func) (info->stream, "%d", GET_FIELD (insn, 23, 25));
|
|
break;
|
|
case 'F':
|
|
/* if no destination completer, need a space here */
|
|
if (GET_FIELD (insn, 21, 22) == 1)
|
|
fputs_filtered (float_format_names[GET_FIELD (insn, 19, 20)],
|
|
info);
|
|
else
|
|
(*info->fprintf_func) (info->stream, "%s ",
|
|
float_format_names[GET_FIELD
|
|
(insn, 19, 20)]);
|
|
break;
|
|
case 'G':
|
|
(*info->fprintf_func) (info->stream, "%s ",
|
|
float_format_names[GET_FIELD (insn,
|
|
17, 18)]);
|
|
break;
|
|
case 'H':
|
|
fputs_filtered (float_format_names[GET_FIELD
|
|
(insn, 26, 26)], info);
|
|
break;
|
|
case 'I':
|
|
/* if no destination completer, need a space here */
|
|
if (GET_FIELD (insn, 21, 22) == 1)
|
|
fputs_filtered (float_format_names[GET_FIELD (insn, 20, 20)],
|
|
info);
|
|
else
|
|
fprintf_filtered (stream, "%s ",
|
|
float_format_names[GET_FIELD
|
|
(insn, 20, 20)]);
|
|
break;
|
|
case 'J':
|
|
if (GET_FIELD (insn, 24, 24))
|
|
fput_reg_r (GET_FIELD (insn, 6, 10), info);
|
|
else
|
|
fput_reg (GET_FIELD (insn, 6, 10), info);
|
|
|
|
break;
|
|
case 'K':
|
|
if (GET_FIELD (insn, 19, 19))
|
|
fput_reg_r (GET_FIELD (insn, 11, 15), info);
|
|
else
|
|
fput_reg (GET_FIELD (insn, 11, 15), info);
|
|
break;
|
|
case 'M':
|
|
fputs_filtered (float_comp_names[GET_FIELD (insn, 27, 31)],
|
|
info);
|
|
break;
|
|
default:
|
|
(*info->fprintf_func) (info->stream, "%c", *s);
|
|
break;
|
|
}
|
|
}
|
|
return sizeof(insn);
|
|
}
|
|
}
|
|
(*info->fprintf_func) (info->stream, "#%8x", insn);
|
|
return sizeof(insn);
|
|
}
|