265b467340
INT_VECTOR_BASE auxiliary register is available across all ARC architectures. xxxx-xx-xx Claudiu Zissulescu <claziss@gmail.com> * arc-regs.h (int_vector_base): Make it available for all ARC CPUs. Signed-off-by: Claudiu Zissulescu <claziss@gmail.com>
535 lines
16 KiB
Plaintext
535 lines
16 KiB
Plaintext
2020-02-25 Claudiu Zissulescu <claziss@gmail.com>
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* arc-regs.h (int_vector_base): Make it available for all ARC
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CPUs.
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2020-02-20 Nelson Chu <nelson.chu@sifive.com>
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* riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
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changed.
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2020-02-19 Nelson Chu <nelson.chu@sifive.com>
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* riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
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c.mv/c.li if rs1 is zero.
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2020-02-17 H.J. Lu <hongjiu.lu@intel.com>
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* i386-gen.c (cpu_flag_init): Replace CpuABM with
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CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add
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CPU_POPCNT_FLAGS.
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(cpu_flags): Remove CpuABM. Add CpuPOPCNT.
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* i386-opc.h (CpuABM): Removed.
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(CpuPOPCNT): New.
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(i386_cpu_flags): Remove cpuabm. Add cpupopcnt.
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* i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
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popcnt. Remove CpuABM from lzcnt.
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* i386-init.h: Regenerated.
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* i386-tbl.h: Likewise.
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2020-02-17 Jan Beulich <jbeulich@suse.com>
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* i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
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Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
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VexW1 instead of open-coding them.
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* i386-tbl.h: Re-generate.
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2020-02-17 Jan Beulich <jbeulich@suse.com>
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* i386-opc.tbl (AddrPrefixOpReg): Define.
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(monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
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umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
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templates. Drop NoRex64.
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* i386-tbl.h: Re-generate.
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2020-02-17 Jan Beulich <jbeulich@suse.com>
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PR gas/6518
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* i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
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vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
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into Intel syntax instance (with Unpsecified) and AT&T one
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(without).
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(vcvtneps2bf16): Likewise, along with folding the two so far
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separate ones.
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* i386-tbl.h: Re-generate.
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2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
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* i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
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CPU_ANY_SSE4A_FLAGS.
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2020-02-17 Alan Modra <amodra@gmail.com>
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* i386-gen.c (cpu_flag_init): Correct last change.
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2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
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* i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove
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CPU_ANY_SSE4_FLAGS.
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2020-02-14 H.J. Lu <hongjiu.lu@intel.com>
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* i386-opc.tbl (movsx): Remove Intel syntax comments.
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(movzx): Likewise.
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2020-02-14 Jan Beulich <jbeulich@suse.com>
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PR gas/25438
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* i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
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destination for Cpu64-only variant.
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(movzx): Fold patterns.
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* i386-tbl.h: Re-generate.
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2020-02-13 Jan Beulich <jbeulich@suse.com>
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* i386-gen.c (cpu_flag_init): Move CpuSSE4a from
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CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
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CPU_ANY_SSE4_FLAGS entry.
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* i386-init.h: Re-generate.
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2020-02-12 Jan Beulich <jbeulich@suse.com>
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* i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
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with Unspecified, making the present one AT&T syntax only.
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* i386-tbl.h: Re-generate.
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2020-02-12 Jan Beulich <jbeulich@suse.com>
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* i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
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* i386-tbl.h: Re-generate.
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2020-02-12 Jan Beulich <jbeulich@suse.com>
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PR gas/24546
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* i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
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* i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
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Amd64 and Intel64 templates.
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(call, jmp): Likewise for far indirect variants. Dro
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Unspecified.
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* i386-tbl.h: Re-generate.
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2020-02-11 Jan Beulich <jbeulich@suse.com>
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* i386-gen.c (opcode_modifiers): Remove ShortForm entry.
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* i386-opc.h (ShortForm): Delete.
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(struct i386_opcode_modifier): Remove shortform field.
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* i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
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fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
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fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
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ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
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Drop ShortForm.
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* i386-tbl.h: Re-generate.
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2020-02-11 Jan Beulich <jbeulich@suse.com>
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* i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
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fucompi): Drop ShortForm from operand-less templates.
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* i386-tbl.h: Re-generate.
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2020-02-11 Alan Modra <amodra@gmail.com>
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* cgen-ibld.in (extract_normal): Set *valuep on all return paths.
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* bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
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* ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
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* m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
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* xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
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2020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
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* arm-dis.c (print_insn_cde): Define 'V' parse character.
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(cde_opcodes): Add VCX* instructions.
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2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
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Matthew Malcomson <matthew.malcomson@arm.com>
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* arm-dis.c (struct cdeopcode32): New.
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(CDE_OPCODE): New macro.
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(cde_opcodes): New disassembly table.
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(regnames): New option to table.
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(cde_coprocs): New global variable.
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(print_insn_cde): New
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(print_insn_thumb32): Use print_insn_cde.
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(parse_arm_disassembler_options): Parse coprocN args.
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2020-02-10 H.J. Lu <hongjiu.lu@intel.com>
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PR gas/25516
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* i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
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with ISA64.
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* i386-opc.h (AMD64): Removed.
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(Intel64): Likewose.
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(AMD64): New.
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(INTEL64): Likewise.
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(INTEL64ONLY): Likewise.
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(i386_opcode_modifier): Replace amd64 and intel64 with isa64.
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* i386-opc.tbl (Amd64): New.
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(Intel64): Likewise.
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(Intel64Only): Likewise.
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Replace AMD64 with Amd64. Update sysenter/sysenter with
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Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
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* i386-tbl.h: Regenerated.
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2020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
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PR 25469
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* z80-dis.c: Add support for GBZ80 opcodes.
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2020-02-04 Alan Modra <amodra@gmail.com>
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* d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
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2020-02-03 Alan Modra <amodra@gmail.com>
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* m32c-ibld.c: Regenerate.
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2020-02-01 Alan Modra <amodra@gmail.com>
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* frv-ibld.c: Regenerate.
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2020-01-31 Jan Beulich <jbeulich@suse.com>
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* i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
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(intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
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(OP_E_memory): Replace xmm_mdq_mode case label by
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vex_scalar_w_dq_mode one.
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* i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
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2020-01-31 Jan Beulich <jbeulich@suse.com>
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* i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
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(vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
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vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
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(intel_operand_size): Drop vex_w_dq_mode case label.
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2020-01-31 Richard Sandiford <richard.sandiford@arm.com>
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* aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
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Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
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2020-01-30 Alan Modra <amodra@gmail.com>
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* m32c-ibld.c: Regenerate.
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2020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
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* bpf-opc.c: Regenerate.
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2020-01-30 Jan Beulich <jbeulich@suse.com>
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* i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
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(dis386): Use them to replace C2/C3 table entries.
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(x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
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* i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
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ones. Use Size64 instead of DefaultSize on Intel64 ones.
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* i386-tbl.h: Re-generate.
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2020-01-30 Jan Beulich <jbeulich@suse.com>
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* i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
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forms.
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(fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
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DefaultSize.
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* i386-tbl.h: Re-generate.
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2020-01-30 Alan Modra <amodra@gmail.com>
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* tic4x-dis.c (tic4x_dp): Make unsigned.
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2020-01-27 H.J. Lu <hongjiu.lu@intel.com>
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Jan Beulich <jbeulich@suse.com>
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PR binutils/25445
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* i386-dis.c (MOVSXD_Fixup): New function.
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(movsxd_mode): New enum.
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(x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
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(intel_operand_size): Handle movsxd_mode.
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(OP_E_register): Likewise.
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(OP_G): Likewise.
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* i386-opc.tbl: Remove Rex64 and allow 32-bit destination
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register on movsxd. Add movsxd with 16-bit destination register
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for AMD64 and Intel64 ISAs.
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* i386-tbl.h: Regenerated.
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2020-01-27 Tamar Christina <tamar.christina@arm.com>
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PR 25403
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* aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
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* aarch64-asm-2.c: Regenerate
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* aarch64-dis-2.c: Likewise.
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* aarch64-opc-2.c: Likewise.
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2020-01-21 Jan Beulich <jbeulich@suse.com>
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* i386-opc.tbl (sysret): Drop DefaultSize.
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* i386-tbl.h: Re-generate.
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2020-01-21 Jan Beulich <jbeulich@suse.com>
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* i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
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Dword.
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(vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
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* i386-tbl.h: Re-generate.
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2020-01-20 Nick Clifton <nickc@redhat.com>
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* po/de.po: Updated German translation.
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* po/pt_BR.po: Updated Brazilian Portuguese translation.
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* po/uk.po: Updated Ukranian translation.
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2020-01-20 Alan Modra <amodra@gmail.com>
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* hppa-dis.c (fput_const): Remove useless cast.
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2020-01-20 Alan Modra <amodra@gmail.com>
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* arm-dis.c (print_insn_arm): Wrap 'T' value.
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2020-01-18 Nick Clifton <nickc@redhat.com>
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* configure: Regenerate.
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* po/opcodes.pot: Regenerate.
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2020-01-18 Nick Clifton <nickc@redhat.com>
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Binutils 2.34 branch created.
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2020-01-17 Christian Biesinger <cbiesinger@google.com>
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* opintl.h: Fix spelling error (seperate).
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2020-01-17 H.J. Lu <hongjiu.lu@intel.com>
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* i386-opc.tbl: Add {vex} pseudo prefix.
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* i386-tbl.h: Regenerated.
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2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
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PR 25376
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* opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
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(neon_opcodes): Likewise.
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(select_arm_features): Make sure we enable MVE bits when selecting
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armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
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any architecture.
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2020-01-16 Jan Beulich <jbeulich@suse.com>
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* i386-opc.tbl: Drop stale comment from XOP section.
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2020-01-16 Jan Beulich <jbeulich@suse.com>
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* i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
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(extractps): Add VexWIG to SSE2AVX forms.
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* i386-tbl.h: Re-generate.
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2020-01-16 Jan Beulich <jbeulich@suse.com>
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* i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
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Size64 from and use VexW1 on SSE2AVX forms.
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(vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
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VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
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* i386-tbl.h: Re-generate.
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2020-01-15 Alan Modra <amodra@gmail.com>
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* tic4x-dis.c (tic4x_version): Make unsigned long.
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(optab, optab_special, registernames): New file scope vars.
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(tic4x_print_register): Set up registernames rather than
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malloc'd registertable.
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(tic4x_disassemble): Delete optable and optable_special. Use
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optab and optab_special instead. Throw away old optab,
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optab_special and registernames when info->mach changes.
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2020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
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PR 25377
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* z80-dis.c (suffix): Use .db instruction to generate double
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prefix.
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2020-01-14 Alan Modra <amodra@gmail.com>
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* z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
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values to unsigned before shifting.
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2020-01-13 Thomas Troeger <tstroege@gmx.de>
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* arm-dis.c (print_insn_arm): Fill in insn info fields for control
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flow instructions.
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(print_insn_thumb16, print_insn_thumb32): Likewise.
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(print_insn): Initialize the insn info.
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* i386-dis.c (print_insn): Initialize the insn info fields, and
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detect jumps.
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2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
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* arc-opc.c (C_NE): Make it required.
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2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
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* opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
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reserved register name.
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2020-01-13 Alan Modra <amodra@gmail.com>
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* ns32k-dis.c (Is_gen): Use strchr, add 'f'.
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(print_insn_ns32k): Adjust ioffset for 'f' index_offset.
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2020-01-13 Alan Modra <amodra@gmail.com>
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* wasm32-dis.c (print_insn_wasm32): Localise variables. Store
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result of wasm_read_leb128 in a uint64_t and check that bits
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are not lost when copying to other locals. Use uint32_t for
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most locals. Use PRId64 when printing int64_t.
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2020-01-13 Alan Modra <amodra@gmail.com>
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* score-dis.c: Formatting.
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* score7-dis.c: Formatting.
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||
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2020-01-13 Alan Modra <amodra@gmail.com>
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* score-dis.c (print_insn_score48): Use unsigned variables for
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unsigned values. Don't left shift negative values.
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(print_insn_score32): Likewise.
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* score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
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2020-01-13 Alan Modra <amodra@gmail.com>
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* tic4x-dis.c (tic4x_print_register): Remove dead code.
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2020-01-13 Alan Modra <amodra@gmail.com>
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* fr30-ibld.c: Regenerate.
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2020-01-13 Alan Modra <amodra@gmail.com>
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* xgate-dis.c (print_insn): Don't left shift signed value.
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(ripBits): Formatting, use 1u.
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2020-01-10 Alan Modra <amodra@gmail.com>
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* tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
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* tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
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2020-01-10 Alan Modra <amodra@gmail.com>
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* m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
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and XRREG value earlier to avoid a shift with negative exponent.
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* m10200-dis.c (disassemble): Similarly.
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2020-01-09 Nick Clifton <nickc@redhat.com>
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PR 25224
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* z80-dis.c (ld_ii_ii): Use correct cast.
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|
||
2020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
|
||
|
||
PR 25224
|
||
* z80-dis.c (ld_ii_ii): Use character constant when checking
|
||
opcode byte value.
|
||
|
||
2020-01-09 Jan Beulich <jbeulich@suse.com>
|
||
|
||
* i386-dis.c (SEP_Fixup): New.
|
||
(SEP): Define.
|
||
(dis386_twobyte): Use it for sysenter/sysexit.
|
||
(enum x86_64_isa): Change amd64 enumerator to value 1.
|
||
(OP_J): Compare isa64 against intel64 instead of amd64.
|
||
* i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
|
||
forms.
|
||
* i386-tbl.h: Re-generate.
|
||
|
||
2020-01-08 Alan Modra <amodra@gmail.com>
|
||
|
||
* z8k-dis.c: Include libiberty.h
|
||
(instr_data_s): Make max_fetched unsigned.
|
||
(z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
|
||
Don't exceed byte_info bounds.
|
||
(output_instr): Make num_bytes unsigned.
|
||
(unpack_instr): Likewise for nibl_count and loop.
|
||
* z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
|
||
idx unsigned.
|
||
* z8k-opc.h: Regenerate.
|
||
|
||
2020-01-07 Shahab Vahedi <shahab@synopsys.com>
|
||
|
||
* arc-tbl.h (llock): Use 'LLOCK' as class.
|
||
(llockd): Likewise.
|
||
(scond): Use 'SCOND' as class.
|
||
(scondd): Likewise.
|
||
(llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
|
||
(scondd): Likewise.
|
||
|
||
2020-01-06 Alan Modra <amodra@gmail.com>
|
||
|
||
* m32c-ibld.c: Regenerate.
|
||
|
||
2020-01-06 Alan Modra <amodra@gmail.com>
|
||
|
||
PR 25344
|
||
* z80-dis.c (suffix): Don't use a local struct buffer copy.
|
||
Peek at next byte to prevent recursion on repeated prefix bytes.
|
||
Ensure uninitialised "mybuf" is not accessed.
|
||
(print_insn_z80): Don't zero n_fetch and n_used here,..
|
||
(print_insn_z80_buf): ..do it here instead.
|
||
|
||
2020-01-04 Alan Modra <amodra@gmail.com>
|
||
|
||
* m32r-ibld.c: Regenerate.
|
||
|
||
2020-01-04 Alan Modra <amodra@gmail.com>
|
||
|
||
* cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
|
||
|
||
2020-01-04 Alan Modra <amodra@gmail.com>
|
||
|
||
* crx-dis.c (match_opcode): Avoid shift left of signed value.
|
||
|
||
2020-01-04 Alan Modra <amodra@gmail.com>
|
||
|
||
* d30v-dis.c (print_insn): Avoid signed overflow in left shift.
|
||
|
||
2020-01-03 Jan Beulich <jbeulich@suse.com>
|
||
|
||
* aarch64-tbl.h (aarch64_opcode_table): Use
|
||
SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
|
||
|
||
2020-01-03 Jan Beulich <jbeulich@suse.com>
|
||
|
||
* aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
|
||
forms of SUDOT and USDOT.
|
||
|
||
2020-01-03 Jan Beulich <jbeulich@suse.com>
|
||
|
||
* aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
|
||
uzip{1,2}.
|
||
* opcodes/aarch64-dis-2.c: Re-generate.
|
||
|
||
2020-01-03 Jan Beulich <jbeulich@suse.com>
|
||
|
||
* aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
|
||
FMMLA encoding.
|
||
* opcodes/aarch64-dis-2.c: Re-generate.
|
||
|
||
2020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
|
||
|
||
* z80-dis.c: Add support for eZ80 and Z80 instructions.
|
||
|
||
2020-01-01 Alan Modra <amodra@gmail.com>
|
||
|
||
Update year range in copyright notice of all files.
|
||
|
||
For older changes see ChangeLog-2019
|
||
|
||
Copyright (C) 2020 Free Software Foundation, Inc.
|
||
|
||
Copying and distribution of this file, with or without modification,
|
||
are permitted in any medium without royalty provided the copyright
|
||
notice and this notice are preserved.
|
||
|
||
Local Variables:
|
||
mode: change-log
|
||
left-margin: 8
|
||
fill-column: 74
|
||
version-control: never
|
||
End:
|