8e394ffc7a
2015-09-25 Andrew Bennett <andrew.bennett@imgtec.com>
Ali Lown <ali.lown@imgtec.com>
sim/common/
* sim-bits.h (EXTEND6): New macro.
(EXTEND12): New macro.
(EXTEND25): New macro.
sim/mips/
* Makefile.in (tmp-micromips): New rule.
(tmp-mach-multi): Add support for micromips.
* configure.ac (mips*-sde-elf* | mips*-mti-elf*): Made a multi sim
that works for both mips64 and micromips64.
(mipsisa32r2*-*-*): Made a multi sim that works for mips32 and
micromips32.
Add build support for micromips.
* dsp.igen (do_ph_s_absq, do_w_s_absq, do_qb_s_absq, do_addsc,
do_addwc, do_bitrev, do_extpv, do_extrv, do_extrv_s_h, do_insv,
do_lxx do_modsub, do_mthlip, do_mulsaq_s_w_ph, do_ph_packrl, do_qb_pick
do_ph_pick, do_qb_ph_precequ, do_qb_ph_preceu, do_w_preceq
do_w_ph_precrq, do_ph_qb_precrq, do_w_ph_rs_precrq do_qb_w_raddu,
do_rddsp, do_repl, do_shilov, do_ph_shl, do_qb_shl do_w_s_shllv,
do_ph_shrlv, do_w_r_shrav, do_wrdsp, do_qb_shrav, do_append,
do_balign, do_ph_w_mulsa, do_ph_qb_precr, do_prepend): New functions.
Refactored instruction code to use these functions.
* dsp2.igen: Refactored instruction code to use the new functions.
* interp.c (decode_coproc): Refactored to work with any instruction
encoding.
(isa_mode): New variable
(RSVD_INSTRUCTION): Changed to 0x00000039.
* m16.igen (BREAK16): Refactored instruction to use do_break16.
(JALX32): Add mips32, mips64, mips32r2 and mips64r2 models.
* micromips.dc: New file.
* micromips.igen: New file.
* micromips16.dc: New file.
* micromipsdsp.igen: New file.
* micromipsrun.c: New file.
* mips.igen (do_swc1): Changed to work with any instruction encoding.
(do_add do_addi do_andi do_dadd do_daddi do_dsll32 do_dsra32
do_dsrl32, do_dsub, do_break, do_break16, do_clo, do_clz, do_dclo
do_dclz, do_lb, do_lh, do_lwr, do_lwl, do_lwc, do_lw, do_lwu, do_lhu
do_ldc, do_lbu, do_ll, do_lld, do_lui, do_madd, do_dsp_madd, do_maddu
do_dsp_maddu, do_dsp_mfhi, do_dsp_mflo, do_movn, do_movz, do_msub
do_dsp_msub, do_msubu, do_dsp_msubu, do_mthi, do_dsp_mthi, do_mtlo
do_dsp_mtlo, do_mul, do_dsp_mult, do_dsp_multu, do_pref, do_sc, do_scd
do_sub, do_sw, do_teq, do_teqi, do_tge, do_tgei, do_tgeiu, do_tgeu, do_tlt
do_tlti, do_tltiu, do_tltu, do_tne, do_tnei, do_abs_fmt, do_add_fmt
do_alnv_ps, do_c_cond_fmt, do_ceil_fmt, do_cfc1, do_ctc1, do_cvt_d_fmt
do_cvt_l_fmt, do_cvt_ps_s, do_cvt_s_fmt, do_cvt_s_pl, do_cvt_s_pu
do_cvt_w_fmt, do_div_fmt, do_dmfc1b, do_dmtc1b, do_floor_fmt, do_luxc1_32
do_luxc1_64, do_lwc1, do_lwxc1, do_madd_fmt, do_mfc1b, do_mov_fmt, do_movtf
do_movtf_fmt, do_movn_fmt, do_movz_fmt, do_msub_fmt, do_mtc1b, do_mul_fmt
do_neg_fmt, do_nmadd_fmt, do_nmsub_fmt, do_pll_ps, do_plu_ps, do_pul_ps
do_puu_ps, do_recip_fmt, do_round_fmt, do_rsqrt_fmt, do_prefx, do_sdc1
do_suxc1_32, do_suxc1_64, do_sqrt_fmt, do_sub_fmt, do_swc1, do_swxc1
do_trunc_fmt): New functions, refactored from existing instructions.
Refactored instruction code to use these functions.
(RSVD): Changed to use new reserved instruction.
(loadstore_ea, not_word_value, unpredictable, check_mt_hilo, check_mf_hilo,
check_mult_hilo, check_div_hilo, check_u64, do_luxc1_32, do_sdc1, do_suxc1_32,
check_fmt_p, check_fpu, do_load_double, do_store_double): Added micromips32
and micromips64 models.
Added include for micromips.igen and micromipsdsp.igen
Add micromips32 and micromips64 models.
(DecodeCoproc): Updated to use new macro definition.
* mips3264r2.igen (do_dsbh, do_dshd, do_dext, do_dextm, do_dextu, do_di,
do_dins, do_dinsm, do_ei, do_ext, do_mfhc1, do_mthc1, do_ins, do_dinsu,
do_seb, do_seh do_rdhwr, do_wsbh): New functions.
Refactored instruction code to use these functions.
* sim-main.h (CP0_operation): New enum.
(DecodeCoproc): Updated macro.
(IMEM32_MICROMIPS, IMEM16_MICROMIPS, MICROMIPS_MINOR_OPCODE,
MICROMIPS_DELAYSLOT_SIZE_ANY, MICROMIPS_DELAYSLOT_SIZE_16, MICROMIPS_DELAYSLOT_SIZE_32,
ISA_MODE_MIPS32 and ISA_MODE_MICROMIPS): New defines.
(sim_state): Add isa_mode field.
sim/testsuite/sim/mips/
* basic.exp (run_micromips_test, run_sim_tests): New functions
Add support for micromips tests.
* hilo-hazard-4.s: New file.
* testutils.inc (_dowrite): Changed reserved instruction encoding.
(writemsg): Moved the la and li instructions before the data they are
assigned to, which prevents a bug where MIPS32 relocations are used instead
of micromips relocations when building for micromips.
673 lines
15 KiB
C
673 lines
15 KiB
C
// -*- C -*-
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// Simulator definition for the MIPS DSP REV 2 ASE.
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// Copyright (C) 2007-2015 Free Software Foundation, Inc.
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// Contributed by MIPS Technologies, Inc.
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// Written by Chao-ying Fu (fu@mips.com).
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//
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// This file is part of the MIPS sim
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//
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// This program is free software; you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation; either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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// op: 0 = ADD, 1 = SUB
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// sat: 0 = no saturation, 1 = saturation
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:function:::void:do_u_ph_op:int rd, int rs, int rt, int op, int sat
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{
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int i;
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unsigned32 h0;
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unsigned16 h1, h2;
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unsigned32 v1 = GPR[rs];
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unsigned32 v2 = GPR[rt];
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unsigned32 result = 0;
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for (i = 0; i < 32; i += 16, v1 >>= 16, v2 >>= 16)
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{
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h1 = (unsigned16)(v1 & 0xffff);
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h2 = (unsigned16)(v2 & 0xffff);
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if (op == 0) // ADD
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h0 = (unsigned32)h1 + (unsigned32)h2;
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else // SUB
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h0 = (unsigned32)h1 - (unsigned32)h2;
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if (op == 0 && (h0 > (unsigned32)0x0000ffff)) // ADD SAT
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{
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DSPCR |= DSPCR_OUFLAG4;
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if (sat == 1)
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h0 = 0xffff;
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}
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else if (op == 1 && h1 < h2) // SUB SAT
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{
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DSPCR |= DSPCR_OUFLAG4;
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if (sat == 1)
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h0 = 0x0;
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}
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result |= ((unsigned32)((unsigned16)h0) << i);
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}
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GPR[rd] = EXTEND32 (result);
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}
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// op: 0 = ADD, 1 = SUB
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// round: 0 = no rounding, 1 = rounding
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:function:::void:do_uh_qb_op:int rd, int rs, int rt, int op, int round
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{
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int i;
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unsigned32 h0;
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unsigned8 h1, h2;
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unsigned32 v1 = GPR[rs];
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unsigned32 v2 = GPR[rt];
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unsigned32 result = 0;
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for (i = 0; i < 32; i += 8, v1 >>= 8, v2 >>= 8)
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{
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h1 = (unsigned8)(v1 & 0xff);
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h2 = (unsigned8)(v2 & 0xff);
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if (op == 0) // ADD
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h0 = (unsigned32)h1 + (unsigned32)h2;
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else // SUB
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h0 = (unsigned32)h1 - (unsigned32)h2;
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if (round == 1)
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h0 = (h0 + 1) >> 1;
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else
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h0 = h0 >> 1;
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result |= ((unsigned32)((unsigned8)h0) << i);
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}
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GPR[rd] = EXTEND32 (result);
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}
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// op: 0 = EQ, 1 = LT, 2 = LE
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:function:::void:do_qb_cmpgdu:int rd, int rs, int rt, int op
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{
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int i, j;
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unsigned32 v1 = GPR[rs];
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unsigned32 v2 = GPR[rt];
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unsigned8 h1, h2;
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unsigned32 result = 0;
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unsigned32 mask;
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for (i = 0, j = 0; i < 32; i += 8, j++, v1 >>= 8, v2 >>= 8)
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{
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h1 = (unsigned8)(v1 & 0xff);
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h2 = (unsigned8)(v2 & 0xff);
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mask = ~(1 << (DSPCR_CCOND_SHIFT + j));
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DSPCR &= mask;
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if (op == 0) // EQ
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{
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result |= ((h1 == h2) << j);
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DSPCR |= ((h1 == h2) << (DSPCR_CCOND_SHIFT + j));
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}
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else if (op == 1) // LT
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{
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result |= ((h1 < h2) << j);
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DSPCR |= ((h1 < h2) << (DSPCR_CCOND_SHIFT + j));
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}
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else // LE
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{
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result |= ((h1 <= h2) << j);
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DSPCR |= ((h1 <= h2) << (DSPCR_CCOND_SHIFT + j));
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}
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}
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GPR[rd] = EXTEND32 (result);
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}
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// op: 0 = DPA 1 = DPS
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:function:::void:do_w_ph_dot_product:int ac, int rs, int rt, int op
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{
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int i;
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unsigned32 v1 = GPR[rs];
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unsigned32 v2 = GPR[rt];
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signed16 h1, h2;
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signed32 result;
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unsigned32 lo = DSPLO(ac);
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unsigned32 hi = DSPHI(ac);
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signed64 prod = (signed64)((((unsigned64)hi) << 32) + (unsigned64)lo);
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for (i = 0; i < 32; i += 16, v1 >>= 16, v2 >>= 16)
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{
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h1 = (signed16)(v1 & 0xffff);
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h2 = (signed16)(v2 & 0xffff);
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result = (signed32)h1 * (signed32)h2;
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if (op == 0) // DPA
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prod += (signed64)result;
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else // DPS
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prod -= (signed64)result;
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}
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DSPLO(ac) = EXTEND32 (prod);
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DSPHI(ac) = EXTEND32 (prod >> 32);
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}
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// round: 0 = no rounding, 1 = rounding
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:function:::void:do_w_mulq:int rd, int rs, int rt, int round
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{
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unsigned32 v1 = GPR[rs];
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unsigned32 v2 = GPR[rt];
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signed32 w1, w2;
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signed64 prod;
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unsigned32 result;
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w1 = (signed32) v1;
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w2 = (signed32 )v2;
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if (w1 == (signed32) 0x80000000 && w2 == (signed32) 0x80000000)
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{
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DSPCR |= DSPCR_OUFLAG5;
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prod = 0x7fffffff;
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}
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else
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{
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prod = ((signed64) w1 * (signed64) w2) << 1;
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if (round == 1)
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prod += 0x0000000080000000LL;
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prod = prod >> 32;
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}
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result = (unsigned32) prod;
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GPR[rd] = EXTEND32 (result);
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}
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// round: 0 = no rounding, 1 = rounding
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:function:::void:do_precr_sra:int rt, int rs, int sa, int round
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{
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unsigned32 v1 = GPR[rt];
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unsigned32 v2 = GPR[rs];
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signed32 w1 = (signed32) v1;
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signed32 w2 = (signed32) v2;
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signed32 result;
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if (sa != 0)
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{
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if (round == 1 && (w1 & (1 << (sa - 1))))
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w1 = (w1 >> sa) + 1;
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else
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w1 = w1 >> sa;
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if (round == 1 && (w2 & (1 << (sa - 1))))
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w2 = (w2 >> sa) + 1;
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else
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w2 = w2 >> sa;
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}
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result = (w1 << 16) | (w2 & 0xffff);
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GPR[rt] = EXTEND32 (result);
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}
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// round: 0 = no rounding, 1 = rounding
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:function:::void:do_qb_shra:int rd, int rt, int shift, int round
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{
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int i, j;
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signed8 q0;
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unsigned32 v1 = GPR[rt];
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unsigned32 result = 0;
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for (i = 0; i < 32; i += 8, v1 >>= 8)
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{
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q0 = (signed8)(v1 & 0xff);
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if (shift != 0)
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{
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if (round == 1 && (q0 & (1 << (shift - 1))))
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q0 = (q0 >> shift) + 1;
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else
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q0 = q0 >> shift;
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}
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result |= ((unsigned32)((unsigned8)q0) << i);
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}
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GPR[rd] = EXTEND32 (result);
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}
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:function:::void:do_ph_shrl:int rd, int rt, int shift
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{
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int i, j;
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unsigned16 h0;
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unsigned32 v1 = GPR[rt];
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unsigned32 result = 0;
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for (i = 0; i < 32; i += 16, v1 >>= 16)
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{
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h0 = (unsigned16)(v1 & 0xffff);
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h0 = h0 >> shift;
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result |= ((unsigned32)h0 << i);
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}
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GPR[rd] = EXTEND32 (result);
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}
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// op: 0 = ADD, 1 = SUB
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// round: 0 = no rounding, 1 = rounding
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:function:::void:do_qh_ph_op:int rd, int rs, int rt, int op, int round
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{
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int i;
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signed32 h0;
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signed16 h1, h2;
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unsigned32 v1 = GPR[rs];
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unsigned32 v2 = GPR[rt];
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unsigned32 result = 0;
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for (i = 0; i < 32; i += 16, v1 >>= 16, v2 >>= 16)
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{
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h1 = (signed16)(v1 & 0xffff);
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h2 = (signed16)(v2 & 0xffff);
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if (op == 0) // ADD
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h0 = (signed32)h1 + (signed32)h2;
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else // SUB
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h0 = (signed32)h1 - (signed32)h2;
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if (round == 1)
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h0 = (h0 + 1) >> 1;
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else
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h0 = h0 >> 1;
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result |= ((unsigned32)((unsigned16)h0) << i);
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}
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GPR[rd] = EXTEND32 (result);
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}
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// op: 0 = ADD, 1 = SUB
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// round: 0 = no rounding, 1 = rounding
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:function:::void:do_qh_w_op:int rd, int rs, int rt, int op, int round
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{
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int i;
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signed64 v0;
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signed32 v1 = (signed32)GPR[rs];
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signed32 v2 = (signed32)GPR[rt];
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if (op == 0) // ADD
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v0 = (signed64)v1 + (signed64)v2;
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else // SUB
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v0 = (signed64)v1 - (signed64)v2;
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if (round == 1)
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v0 = (v0 + 1) >> 1;
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else
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v0 = v0 >> 1;
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GPR[rd] = EXTEND32 (v0);
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}
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// op: 0 = DPAX, 1 = DPSX
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:function:::void:do_x_w_ph_dot_product:int ac, int rs, int rt, int op
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{
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int i;
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unsigned32 v1 = GPR[rs];
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unsigned32 v2 = GPR[rt];
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signed16 h1, h2;
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signed32 result;
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unsigned32 lo = DSPLO(ac);
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unsigned32 hi = DSPHI(ac);
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signed64 prod = (signed64)((((unsigned64)hi) << 32) + (unsigned64)lo);
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for (i = 0; i < 32; i += 16, v1 >>= 16, v2 <<= 16)
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{
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h1 = (signed16)(v1 & 0xffff);
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h2 = (signed16)((v2 & 0xffff0000) >> 16);
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result = (signed32)h1 * (signed32)h2;
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if (op == 0) // DPAX
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prod += (signed64)result;
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else // DPSX
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prod -= (signed64)result;
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}
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DSPLO(ac) = EXTEND32 (prod);
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DSPHI(ac) = EXTEND32 (prod >> 32);
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}
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// op: 0 = DPAQX, 1 = DPSQX
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// sat: 0 = no saturation, 1 = saturation of the accumulator
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:function:::void:do_qx_w_ph_dot_product:int ac, int rs, int rt, int op, int sat
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{
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int i;
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unsigned32 v1 = GPR[rs];
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unsigned32 v2 = GPR[rt];
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signed16 h1, h2;
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signed32 result;
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unsigned32 lo = DSPLO(ac);
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unsigned32 hi = DSPHI(ac);
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signed64 prod = (signed64)((((unsigned64)hi) << 32) + (unsigned64)lo);
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signed64 max, min;
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for (i = 0; i < 32; i += 16, v1 >>= 16, v2 <<= 16)
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{
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h1 = (signed16)(v1 & 0xffff);
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h2 = (signed16)((v2 & 0xffff0000) >> 16);
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if (h1 == (signed16)0x8000 && h2 == (signed16)0x8000)
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{
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DSPCR |= (1 << (DSPCR_OUFLAG_SHIFT + ac));
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result = 0x7fffffff;
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}
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else
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result = ((signed32)h1 * (signed32)h2) << 1;
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if (op == 0) // DPAQX
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prod += (signed64)result;
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else // DPSQX
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prod -= (signed64)result;
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}
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// Saturation on the accumulator.
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if (sat == 1)
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{
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max = (signed64) 0x7fffffffLL;
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min = (signed64) 0xffffffff80000000LL;
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if (prod > max)
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{
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DSPCR |= (1 << (DSPCR_OUFLAG_SHIFT + ac));
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prod = max;
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}
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else if (prod < min)
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{
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DSPCR |= (1 << (DSPCR_OUFLAG_SHIFT + ac));
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prod = min;
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}
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}
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DSPLO(ac) = EXTEND32 (prod);
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DSPHI(ac) = EXTEND32 (prod >> 32);
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}
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011111,00000,5.RT,5.RD,00001,010010:SPECIAL3:32::ABSQ_S.QB
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"absq_s.qb r<RD>, r<RT>"
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*dsp2:
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{
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do_qb_s_absq (SD_, RD, RT);
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}
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011111,5.RS,5.RT,5.RD,01000,010000:SPECIAL3:32::ADDU.PH
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"addu.ph r<RD>, r<RS>, r<RT>"
|
|
*dsp2:
|
|
{
|
|
do_u_ph_op (SD_, RD, RS, RT, 0, 0);
|
|
}
|
|
|
|
011111,5.RS,5.RT,5.RD,01100,010000:SPECIAL3:32::ADDU_S.PH
|
|
"addu_s.ph r<RD>, r<RS>, r<RT>"
|
|
*dsp2:
|
|
{
|
|
do_u_ph_op (SD_, RD, RS, RT, 0, 1);
|
|
}
|
|
|
|
011111,5.RS,5.RT,5.RD,00000,011000:SPECIAL3:32::ADDUH.QB
|
|
"adduh.qb r<RD>, r<RS>, r<RT>"
|
|
*dsp2:
|
|
{
|
|
do_uh_qb_op (SD_, RD, RS, RT, 0, 0);
|
|
}
|
|
|
|
011111,5.RS,5.RT,5.RD,00010,011000:SPECIAL3:32::ADDUH_R.QB
|
|
"adduh_r.qb r<RD>, r<RS>, r<RT>"
|
|
*dsp2:
|
|
{
|
|
do_uh_qb_op (SD_, RD, RS, RT, 0, 1);
|
|
}
|
|
|
|
011111,5.RS,5.RT,5.SA,00000,110001:SPECIAL3:32::APPEND
|
|
"append r<RT>, r<RS>, <SA>"
|
|
*dsp2:
|
|
{
|
|
do_append (SD_, RT, RS, SA);
|
|
}
|
|
|
|
011111,5.RS,5.RT,000,2.BP,10000,110001:SPECIAL3:32::BALIGN
|
|
"balign r<RT>, r<RS>, <BP>"
|
|
*dsp2:
|
|
{
|
|
do_balign (SD_, RT, RS, BP);
|
|
}
|
|
|
|
011111,5.RS,5.RT,5.RD,11000,010001:SPECIAL3:32::CMPGDU.EQ.QB
|
|
"cmpgdu.eq.qb r<RD>, r<RS>, r<RT>"
|
|
*dsp2:
|
|
{
|
|
do_qb_cmpgdu (SD_, RD, RS, RT, 0);
|
|
}
|
|
|
|
011111,5.RS,5.RT,5.RD,11001,010001:SPECIAL3:32::CMPGDU.LT.QB
|
|
"cmpgdu.lt.qb r<RD>, r<RS>, r<RT>"
|
|
*dsp2:
|
|
{
|
|
do_qb_cmpgdu (SD_, RD, RS, RT, 1);
|
|
}
|
|
|
|
011111,5.RS,5.RT,5.RD,11010,010001:SPECIAL3:32::CMPGDU.LE.QB
|
|
"cmpgdu.le.qb r<RD>, r<RS>, r<RT>"
|
|
*dsp2:
|
|
{
|
|
do_qb_cmpgdu (SD_, RD, RS, RT, 2);
|
|
}
|
|
|
|
011111,5.RS,5.RT,000,2.AC,00000,110000:SPECIAL3:32::DPA.W.PH
|
|
"dpa.w.ph ac<AC>, r<RS>, r<RT>"
|
|
*dsp2:
|
|
{
|
|
do_w_ph_dot_product (SD_, AC, RS, RT, 0);
|
|
}
|
|
|
|
011111,5.RS,5.RT,000,2.AC,00001,110000:SPECIAL3:32::DPS.W.PH
|
|
"dps.w.ph ac<AC>, r<RS>, r<RT>"
|
|
*dsp2:
|
|
{
|
|
do_w_ph_dot_product (SD_, AC, RS, RT, 1);
|
|
}
|
|
|
|
011111,5.RS,5.RT,5.RD,01100,011000:SPECIAL3:32::MUL.PH
|
|
"mul.ph r<RD>, r<RS>, r<RT>"
|
|
*dsp2:
|
|
{
|
|
do_ph_op (SD_, RD, RS, RT, 2, 0);
|
|
}
|
|
|
|
011111,5.RS,5.RT,5.RD,01110,011000:SPECIAL3:32::MUL_S.PH
|
|
"mul_s.ph r<RD>, r<RS>, r<RT>"
|
|
*dsp2:
|
|
{
|
|
do_ph_op (SD_, RD, RS, RT, 2, 1);
|
|
}
|
|
|
|
011111,5.RS,5.RT,5.RD,10111,011000:SPECIAL3:32::MULQ_RS.W
|
|
"mulq_rs.w r<RD>, r<RS>, r<RT>"
|
|
*dsp2:
|
|
{
|
|
do_w_mulq (SD_, RD, RS, RT, 1);
|
|
}
|
|
|
|
011111,5.RS,5.RT,5.RD,11110,010000:SPECIAL3:32::MULQ_S.PH
|
|
"mulq_s.ph r<RD>, r<RS>, r<RT>"
|
|
*dsp2:
|
|
{
|
|
do_ph_mulq (SD_, RD, RS, RT, 0);
|
|
}
|
|
|
|
011111,5.RS,5.RT,5.RD,10110,011000:SPECIAL3:32::MULQ_S.W
|
|
"mulq_s.w r<RD>, r<RS>, r<RT>"
|
|
*dsp2:
|
|
{
|
|
do_w_mulq (SD_, RD, RS, RT, 0);
|
|
}
|
|
|
|
011111,5.RS,5.RT,000,2.AC,00010,110000:SPECIAL3:32::MULSA.W.PH
|
|
"mulsa.w.ph ac<AC>, r<RS>, r<RT>"
|
|
*dsp2:
|
|
{
|
|
do_ph_w_mulsa (SD_, AC, RS, RT);
|
|
}
|
|
|
|
011111,5.RS,5.RT,5.RD,01101,010001:SPECIAL3:32::PRECR.QB.PH
|
|
"precr.qb.ph r<RD>, r<RS>, r<RT>"
|
|
*dsp2:
|
|
{
|
|
do_ph_qb_precr (SD_, RD, RS, RT);
|
|
}
|
|
|
|
011111,5.RS,5.RT,5.SA,11110,010001:SPECIAL3:32::PRECR_SRA.PH.W
|
|
"precr_sra.ph.w r<RT>, r<RS>, <SA>"
|
|
*dsp2:
|
|
{
|
|
do_precr_sra (SD_, RT, RS, SA, 0);
|
|
}
|
|
|
|
011111,5.RS,5.RT,5.SA,11111,010001:SPECIAL3:32::PRECR_SRA_R.PH.W
|
|
"precr_sra_r.ph.w r<RT>, r<RS>, <SA>"
|
|
*dsp2:
|
|
{
|
|
do_precr_sra (SD_, RT, RS, SA, 1);
|
|
}
|
|
|
|
011111,5.RS,5.RT,5.SA,00001,110001:SPECIAL3:32::PREPEND
|
|
"prepend r<RT>, r<RS>, <SA>"
|
|
*dsp2:
|
|
{
|
|
do_prepend (SD_, RT, RS, SA);
|
|
}
|
|
|
|
011111,00,3.SHIFT3,5.RT,5.RD,00100,010011:SPECIAL3:32::SHRA.QB
|
|
"shra.qb r<RD>, r<RT>, <SHIFT3>"
|
|
*dsp2:
|
|
{
|
|
do_qb_shra (SD_, RD, RT, SHIFT3, 0);
|
|
}
|
|
|
|
011111,00,3.SHIFT3,5.RT,5.RD,00101,010011:SPECIAL3:32::SHRA_R.QB
|
|
"shra_r.qb r<RD>, r<RT>, <SHIFT3>"
|
|
*dsp2:
|
|
{
|
|
do_qb_shra (SD_, RD, RT, SHIFT3, 1);
|
|
}
|
|
|
|
011111,5.RS,5.RT,5.RD,00110,010011:SPECIAL3:32::SHRAV.QB
|
|
"shrav.qb r<RD>, r<RT>, r<RS>"
|
|
*dsp2:
|
|
{
|
|
do_qb_shrav (SD_, RD, RT, RS, 0);
|
|
}
|
|
|
|
011111,5.RS,5.RT,5.RD,00111,010011:SPECIAL3:32::SHRAV_R.QB
|
|
"shrav_r.qb r<RD>, r<RT>, r<RS>"
|
|
*dsp2:
|
|
{
|
|
do_qb_shrav (SD_, RD, RT, RS, 1);
|
|
}
|
|
|
|
011111,0,4.SHIFT4,5.RT,5.RD,11001,010011:SPECIAL3:32::SHRL.PH
|
|
"shrl.ph r<RD>, r<RT>, <SHIFT4>"
|
|
*dsp2:
|
|
{
|
|
do_ph_shrl (SD_, RD, RT, SHIFT4);
|
|
}
|
|
|
|
011111,5.RS,5.RT,5.RD,11011,010011:SPECIAL3:32::SHRLV.PH
|
|
"shrlv.ph r<RD>, r<RT>, r<RS>"
|
|
*dsp2:
|
|
{
|
|
do_ph_shrlv (SD_, RD, RT, RS);
|
|
}
|
|
|
|
011111,5.RS,5.RT,5.RD,01001,010000:SPECIAL3:32::SUBU.PH
|
|
"subu.ph r<RD>, r<RS>, r<RT>"
|
|
*dsp2:
|
|
{
|
|
do_u_ph_op (SD_, RD, RS, RT, 1, 0);
|
|
}
|
|
|
|
011111,5.RS,5.RT,5.RD,01101,010000:SPECIAL3:32::SUBU_S.PH
|
|
"subu_s.ph r<RD>, r<RS>, r<RT>"
|
|
*dsp2:
|
|
{
|
|
do_u_ph_op (SD_, RD, RS, RT, 1, 1);
|
|
}
|
|
|
|
011111,5.RS,5.RT,5.RD,00001,011000:SPECIAL3:32::SUBUH.QB
|
|
"subuh.qb r<RD>, r<RS>, r<RT>"
|
|
*dsp2:
|
|
{
|
|
do_uh_qb_op (SD_, RD, RS, RT, 1, 0);
|
|
}
|
|
|
|
011111,5.RS,5.RT,5.RD,00011,011000:SPECIAL3:32::SUBUH_R.QB
|
|
"subuh_r.qb r<RD>, r<RS>, r<RT>"
|
|
*dsp2:
|
|
{
|
|
do_uh_qb_op (SD_, RD, RS, RT, 1, 1);
|
|
}
|
|
|
|
011111,5.RS,5.RT,5.RD,01000,011000:SPECIAL3:32::ADDQH.PH
|
|
"addqh.ph r<RD>, r<RS>, r<RT>"
|
|
*dsp2:
|
|
{
|
|
do_qh_ph_op (SD_, RD, RS, RT, 0, 0);
|
|
}
|
|
|
|
011111,5.RS,5.RT,5.RD,01010,011000:SPECIAL3:32::ADDQH_R.PH
|
|
"addqh_r.ph r<RD>, r<RS>, r<RT>"
|
|
*dsp2:
|
|
{
|
|
do_qh_ph_op (SD_, RD, RS, RT, 0, 1);
|
|
}
|
|
|
|
011111,5.RS,5.RT,5.RD,10000,011000:SPECIAL3:32::ADDQH.W
|
|
"addqh.w r<RD>, r<RS>, r<RT>"
|
|
*dsp2:
|
|
{
|
|
do_qh_w_op (SD_, RD, RS, RT, 0, 0);
|
|
}
|
|
|
|
011111,5.RS,5.RT,5.RD,10010,011000:SPECIAL3:32::ADDQH_R.W
|
|
"addqh_r.w r<RD>, r<RS>, r<RT>"
|
|
*dsp2:
|
|
{
|
|
do_qh_w_op (SD_, RD, RS, RT, 0, 1);
|
|
}
|
|
|
|
011111,5.RS,5.RT,5.RD,01001,011000:SPECIAL3:32::SUBQH.PH
|
|
"subqh.ph r<RD>, r<RS>, r<RT>"
|
|
*dsp2:
|
|
{
|
|
do_qh_ph_op (SD_, RD, RS, RT, 1, 0);
|
|
}
|
|
|
|
011111,5.RS,5.RT,5.RD,01011,011000:SPECIAL3:32::SUBQH_R.PH
|
|
"subqh_r.ph r<RD>, r<RS>, r<RT>"
|
|
*dsp2:
|
|
{
|
|
do_qh_ph_op (SD_, RD, RS, RT, 1, 1);
|
|
}
|
|
|
|
011111,5.RS,5.RT,5.RD,10001,011000:SPECIAL3:32::SUBQH.W
|
|
"subqh.w r<RD>, r<RS>, r<RT>"
|
|
*dsp2:
|
|
{
|
|
do_qh_w_op (SD_, RD, RS, RT, 1, 0);
|
|
}
|
|
|
|
011111,5.RS,5.RT,5.RD,10011,011000:SPECIAL3:32::SUBQH_R.W
|
|
"subqh_r.w r<RD>, r<RS>, r<RT>"
|
|
*dsp2:
|
|
{
|
|
do_qh_w_op (SD_, RD, RS, RT, 1, 1);
|
|
}
|
|
|
|
011111,5.RS,5.RT,000,2.AC,01000,110000:SPECIAL3:32::DPAX.W.PH
|
|
"dpax.w.ph ac<AC>, r<RS>, r<RT>"
|
|
*dsp2:
|
|
{
|
|
do_x_w_ph_dot_product (SD_, AC, RS, RT, 0);
|
|
}
|
|
|
|
011111,5.RS,5.RT,000,2.AC,01001,110000:SPECIAL3:32::DPSX.W.PH
|
|
"dpsx.w.ph ac<AC>, r<RS>, r<RT>"
|
|
*dsp2:
|
|
{
|
|
do_x_w_ph_dot_product (SD_, AC, RS, RT, 1);
|
|
}
|
|
|
|
011111,5.RS,5.RT,000,2.AC,11000,110000:SPECIAL3:32::DPAQX_S.W.PH
|
|
"dpaqx_s.w.ph ac<AC>, r<RS>, r<RT>"
|
|
*dsp2:
|
|
{
|
|
do_qx_w_ph_dot_product (SD_, AC, RS, RT, 0, 0);
|
|
}
|
|
|
|
011111,5.RS,5.RT,000,2.AC,11010,110000:SPECIAL3:32::DPAQX_SA.W.PH
|
|
"dpaqx_sa.w.ph ac<AC>, r<RS>, r<RT>"
|
|
*dsp2:
|
|
{
|
|
do_qx_w_ph_dot_product (SD_, AC, RS, RT, 0, 1);
|
|
}
|
|
|
|
011111,5.RS,5.RT,000,2.AC,11001,110000:SPECIAL3:32::DPSQX_S.W.PH
|
|
"dpsqx_s.w.ph ac<AC>, r<RS>, r<RT>"
|
|
*dsp2:
|
|
{
|
|
do_qx_w_ph_dot_product (SD_, AC, RS, RT, 1, 0);
|
|
}
|
|
|
|
011111,5.RS,5.RT,000,2.AC,11011,110000:SPECIAL3:32::DPSQX_SA.W.PH
|
|
"dpsqx_sa.w.ph ac<AC>, r<RS>, r<RT>"
|
|
*dsp2:
|
|
{
|
|
do_qx_w_ph_dot_product (SD_, AC, RS, RT, 1, 1);
|
|
}
|