8e45593ff3
Joseph Myers <joseph@codesourcery.com>
Andrew Stubbs <ams@codesourcery.com>
bfd/
* config.bfd (sh-*-uclinux* | sh[12]-*-uclinux*): Add
bfd_elf32_shl_vec, and FDPIC vectors to targ_selvecs.
* configure.in: Handle FDPIC vectors.
* elf32-sh-relocs.h: Add FDPIC and movi20 relocations.
* elf32-sh.c (DEFAULT_STACK_SIZE): Define.
(SYMBOL_FUNCDESC_LOCAL): Define. Use it instead of
SYMBOL_REFERENCES_LOCAL for function descriptors.
(fdpic_object_p): New.
(sh_reloc_map): Add FDPIC and movi20 relocations.
(sh_elf_info_to_howto, sh_elf_relocate_section): Handle new invalid
range.
(struct elf_sh_plt_info): Add got20 and short_plt. Update all
definitions.
(FDPIC_PLT_ENTRY_SIZE, FDPIC_PLT_LAZY_OFFSET): Define.
(fdpic_sh_plt_entry_be, fdpic_sh_plt_entry_le, fdpic_sh_plts): New.
(FDPIC_SH2A_PLT_ENTRY_SIZE, FDPIC_SH2A_PLT_LAZY_OFFSET): Define.
(fdpic_sh2a_plt_entry_be, fdpic_sh2a_plt_entry_le)
(fdpic_sh2a_short_plt_be, fdpic_sh2a_short_plt_le, fdpic_sh2a_plts):
New.
(get_plt_info): Handle FDPIC.
(MAX_SHORT_PLT): Define.
(get_plt_index, get_plt_offset): Handle short_plt.
(union gotref): New.
(struct elf_sh_link_hash_entry): Add funcdesc, rename tls_type to
got_type and adjust all uses. Add GOT_FUNCDESC.
(struct sh_elf_obj_tdata): Add local_funcdesc. Rename
local_got_tls_type to local_got_type.
(sh_elf_local_got_type): Renamed from sh_elf_local_got_tls_type. All
users changed.
(sh_elf_local_funcdesc): Define.
(struct elf_sh_link_hash_table): Add sfuncdesc, srelfuncdesc, fdpic_p,
and srofixup.
(sh_elf_link_hash_newfunc): Initialize new fields.
(sh_elf_link_hash_table_create): Set fdpic_p.
(sh_elf_omit_section_dynsym): New.
(create_got_section): Create .got.funcdesc, .rela.got.funcdesc
and .rofixup.
(allocate_dynrelocs): Allocate local function descriptors and space
for R_SH_FUNCDESC-related relocations, and for rofixups.
Handle GOT_FUNCDESC. Create fixups. Handle GOT entries which
require function descriptors.
(sh_elf_always_size_sections): Handle PT_GNU_STACK and __stacksize.
(sh_elf_modify_program_headers): New.
(sh_elf_size_dynamic_sections): Allocate function descriptors for
local symbols. Allocate .got.funcdesc contents. Allocate rofixups.
Handle local GOT entries of type GOT_FUNCDESC. Create fixups for
local GOT entries. Ensure that FDPIC libraries always have a PLTGOT
entry in the .dynamic section.
(sh_elf_add_dyn_reloc, sh_elf_got_offset, sh_elf_initialize_funcdesc)
(sh_elf_add_rofixup, sh_elf_osec_to_segment)
(sh_elf_osec_readonly_p, install_movi20_field): New functions.
(sh_elf_relocate_section): Handle new relocations, R_SH_FUNCDESC,
R_SH_GOTFUNCDESC and R_SH_GOTOFFFUNCDESC. Use sh_elf_got_offset
and .got.plt throughout to find _GLOBAL_OFFSET_TABLE_. Add rofixup
read-only section warnings. Handle undefined weak symbols. Generate
fixups for R_SH_DIR32 and GOT entries. Check for cross-segment
relocations and clear EF_SH_PIC. Handle 20-bit relocations.
Always generate R_SH_DIR32 for FDPIC instead of R_SH_RELATIVE.
(sh_elf_gc_sweep_hook): Handle R_SH_FUNCDESC, R_SH_GOTOFF20,
R_SH_GOTFUNCDESC, R_SH_GOTFUNCDESC20, and R_SH_GOTOFFFUNCDESC.
Handle 20-bit relocations.
(sh_elf_copy_indirect_symbol): Copy function descriptor reference
counts.
(sh_elf_check_relocs): Handle new relocations. Make symbols
dynamic for FDPIC relocs. Account for rofixups. Error for FDPIC
symbol mismatches. Allocate a GOT for R_SH_DIR32. Allocate fixups
for R_SH_DIR32.
(sh_elf_copy_private_data): Copy PT_GNU_STACK size.
(sh_elf_merge_private_data): Copy initial flags. Do not clobber
non-mach flags. Set EF_SH_PIC for FDPIC. Reject FDPIC mismatches.
(sh_elf_finish_dynamic_symbol): Do not handle got_funcdesc entries
here. Rename sgot to sgotplt and srel to srelplt. Handle short_plt,
FDPIC descriptors, and got20. Create R_SH_FUNCDESC_VALUE for FDPIC.
Use install_movi20_field. Rename srel to srelgot. Always generate
R_SH_DIR32 for FDPIC instead of R_SH_RELATIVE.
(sh_elf_finish_dynamic_sections): Fill in the GOT pointer in rofixup.
Do not fill in reserved GOT entries for FDPIC. Correct DT_PLTGOT.
Rename sgot to sgotplt. Assert that the right number of rofixups
and dynamic relocations were allocated.
(sh_elf_use_relative_eh_frame, sh_elf_encode_eh_address): New.
(elf_backend_omit_section_dynsym): Use sh_elf_omit_section_dynsym.
(elf_backend_can_make_relative_eh_frame)
(elf_backend_can_make_lsda_relative_eh_frame)
(elf_backend_encode_eh_address): Define.
(TARGET_BIG_SYM, TARGET_BIG_NAME, TARGET_LITTLE_SYM)
(TARGET_LITTLE_NAME, elf_backend_modify_program_headers, elf32_bed):
Redefine for FDPIC vector.
* reloc.c: Add SH FDPIC and movi20 relocations.
* targets.c (_bfd_target_vector): Add FDPIC vectors.
* configure, bfd-in2.h, libbfd.h: Regenerated.
binutils/
* readelf.c (get_machine_flags): Handle EF_SH_PIC and EF_SH_FDPIC.
gas/
* config/tc-sh.c (sh_fdpic): New.
(sh_check_fixup): Handle relocations on movi20.
(parse_exp): Do not reject PIC operators here.
(build_Mytes): Check for unhandled PIC operators here. Use
sh_check_fixup for movi20.
(enum options): Add OPTION_FDPIC.
(md_longopts, md_parse_option, md_show_usage): Add --fdpic.
(sh_fix_adjustable, md_apply_fix): Handle FDPIC and movi20 relocations.
(sh_elf_final_processing): Handle --fdpic.
(sh_uclinux_target_format): New.
(sh_parse_name): Handle FDPIC relocation operators.
* config/tc-sh.h (TARGET_FORMAT): Define specially for TE_UCLINUX.
(sh_uclinux_target_format): Declare for TE_UCLINUX.
* configure.tgt (sh-*-uclinux* | sh[12]-*-uclinux*): Set
em=uclinux.
* doc/c-sh.texi (SH Options): Document --fdpic.
gas/testsuite/
* gas/sh/basic.exp: Run new tests. Handle uClinux like Linux.
* gas/sh/fdpic.d: New file.
* gas/sh/fdpic.s: New file.
* gas/sh/reg-prefix.d: Force big-endian.
* gas/sh/sh2a-pic.d: New file.
* gas/sh/sh2a-pic.s: New file.
* lib/gas-defs.exp (is_elf_format): Include sh*-*-uclinux*.
include/elf/
* sh.h (EF_SH_PIC, EF_SH_FDPIC): Define.
(R_SH_FIRST_INVALID_RELOC_6, R_SH_LAST_INVALID_RELOC_6): New. Adjust
other invalid ranges.
(R_SH_GOT20, R_SH_GOTOFF20, R_SH_GOTFUNCDESC, R_SH_GOTFUNCDESC20)
(R_SH_GOTOFFFUNCDESC, R_SH_GOTOFFFUNCDESC20, R_SH_FUNCDESC)
(R_SH_FUNCDESC_VALUE): New.
ld/
* Makefile.am (ALL_EMULATIONS): Add eshelf_fd.o and eshlelf_fd.o.
(eshelf_fd.c, eshlelf_fd.c): New rules.
* Makefile.in: Regenerate.
* configure.tgt (sh-*-uclinux*): Add shelf_fd and shlelf_fd
emulations.
* emulparams/shelf_fd.sh: New file.
* emulparams/shlelf_fd.sh: New file.
* emulparams/shlelf_linux.sh: Update comment.
ld/testsuite/
* ld-sh/sh.exp: Handle uClinux like Linux.
* lib/ld-lib.exp (is_elf_format): Include sh*-*-uclinux*.
* ld-sh/fdpic-funcdesc-shared.d: New file.
* ld-sh/fdpic-funcdesc-shared.s: New file.
* ld-sh/fdpic-funcdesc-static.d: New file.
* ld-sh/fdpic-funcdesc-static.s: New file.
* ld-sh/fdpic-gotfuncdesc-shared.d: New file.
* ld-sh/fdpic-gotfuncdesc-shared.s: New file.
* ld-sh/fdpic-gotfuncdesc-static.d: New file.
* ld-sh/fdpic-gotfuncdesc-static.s: New file.
* ld-sh/fdpic-gotfuncdesci20-shared.d: New file.
* ld-sh/fdpic-gotfuncdesci20-shared.s: New file.
* ld-sh/fdpic-gotfuncdesci20-static.d: New file.
* ld-sh/fdpic-gotfuncdesci20-static.s: New file.
* ld-sh/fdpic-goti20-shared.d: New file.
* ld-sh/fdpic-goti20-shared.s: New file.
* ld-sh/fdpic-goti20-static.d: New file.
* ld-sh/fdpic-goti20-static.s: New file.
* ld-sh/fdpic-gotofffuncdesc-shared.d: New file.
* ld-sh/fdpic-gotofffuncdesc-shared.s: New file.
* ld-sh/fdpic-gotofffuncdesc-static.d: New file.
* ld-sh/fdpic-gotofffuncdesc-static.s: New file.
* ld-sh/fdpic-gotofffuncdesci20-shared.d: New file.
* ld-sh/fdpic-gotofffuncdesci20-shared.s: New file.
* ld-sh/fdpic-gotofffuncdesci20-static.d: New file.
* ld-sh/fdpic-gotofffuncdesci20-static.s: New file.
* ld-sh/fdpic-gotoffi20-shared.d: New file.
* ld-sh/fdpic-gotoffi20-shared.s: New file.
* ld-sh/fdpic-gotoffi20-static.d: New file.
* ld-sh/fdpic-gotoffi20-static.s: New file.
* ld-sh/fdpic-plt-be.d: New file.
* ld-sh/fdpic-plt-le.d: New file.
* ld-sh/fdpic-plt.s: New file.
* ld-sh/fdpic-plti20-be.d: New file.
* ld-sh/fdpic-plti20-le.d: New file.
* ld-sh/fdpic-stack-default.d: New file.
* ld-sh/fdpic-stack-size.d: New file.
* ld-sh/fdpic-stack.s: New file.
339 lines
11 KiB
Plaintext
339 lines
11 KiB
Plaintext
@c Copyright 1991, 1992, 1993, 1994, 1995, 1997, 2001, 2003, 2004,
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@c 2005, 2008, 2010 Free Software Foundation, Inc.
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@c This is part of the GAS manual.
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@c For copying conditions, see the file as.texinfo.
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@page
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@node SH-Dependent
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@chapter Renesas / SuperH SH Dependent Features
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@cindex SH support
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@menu
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* SH Options:: Options
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* SH Syntax:: Syntax
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* SH Floating Point:: Floating Point
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* SH Directives:: SH Machine Directives
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* SH Opcodes:: Opcodes
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@end menu
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@node SH Options
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@section Options
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@cindex SH options
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@cindex options, SH
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@code{@value{AS}} has following command-line options for the Renesas
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(formerly Hitachi) / SuperH SH family.
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@table @code
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@kindex --little
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@kindex --big
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@kindex --relax
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@kindex --small
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@kindex --dsp
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@kindex --renesas
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@kindex --allow-reg-prefix
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@item --little
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Generate little endian code.
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@item --big
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Generate big endian code.
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@item --relax
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Alter jump instructions for long displacements.
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@item --small
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Align sections to 4 byte boundaries, not 16.
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@item --dsp
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Enable sh-dsp insns, and disable sh3e / sh4 insns.
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@item --renesas
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Disable optimization with section symbol for compatibility with
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Renesas assembler.
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@item --allow-reg-prefix
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Allow '$' as a register name prefix.
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@kindex --fdpic
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@item --fdpic
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Generate an FDPIC object file.
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@item --isa=sh4 | sh4a
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Specify the sh4 or sh4a instruction set.
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@item --isa=dsp
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Enable sh-dsp insns, and disable sh3e / sh4 insns.
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@item --isa=fp
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Enable sh2e, sh3e, sh4, and sh4a insn sets.
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@item --isa=all
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Enable sh1, sh2, sh2e, sh3, sh3e, sh4, sh4a, and sh-dsp insn sets.
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@item -h-tick-hex
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Support H'00 style hex constants in addition to 0x00 style.
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@end table
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@node SH Syntax
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@section Syntax
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@menu
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* SH-Chars:: Special Characters
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* SH-Regs:: Register Names
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* SH-Addressing:: Addressing Modes
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@end menu
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@node SH-Chars
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@subsection Special Characters
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@cindex line comment character, SH
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@cindex SH line comment character
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@samp{!} is the line comment character.
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@cindex line separator, SH
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@cindex statement separator, SH
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@cindex SH line separator
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You can use @samp{;} instead of a newline to separate statements.
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@cindex symbol names, @samp{$} in
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@cindex @code{$} in symbol names
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Since @samp{$} has no special meaning, you may use it in symbol names.
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@node SH-Regs
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@subsection Register Names
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@cindex SH registers
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@cindex registers, SH
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You can use the predefined symbols @samp{r0}, @samp{r1}, @samp{r2},
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@samp{r3}, @samp{r4}, @samp{r5}, @samp{r6}, @samp{r7}, @samp{r8},
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@samp{r9}, @samp{r10}, @samp{r11}, @samp{r12}, @samp{r13}, @samp{r14},
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and @samp{r15} to refer to the SH registers.
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The SH also has these control registers:
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@table @code
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@item pr
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procedure register (holds return address)
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@item pc
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program counter
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@item mach
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@itemx macl
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high and low multiply accumulator registers
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@item sr
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status register
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@item gbr
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global base register
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@item vbr
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vector base register (for interrupt vectors)
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@end table
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@node SH-Addressing
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@subsection Addressing Modes
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@cindex addressing modes, SH
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@cindex SH addressing modes
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@code{@value{AS}} understands the following addressing modes for the SH.
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@code{R@var{n}} in the following refers to any of the numbered
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registers, but @emph{not} the control registers.
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@table @code
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@item R@var{n}
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Register direct
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@item @@R@var{n}
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Register indirect
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@item @@-R@var{n}
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Register indirect with pre-decrement
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@item @@R@var{n}+
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Register indirect with post-increment
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@item @@(@var{disp}, R@var{n})
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Register indirect with displacement
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@item @@(R0, R@var{n})
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Register indexed
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@item @@(@var{disp}, GBR)
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@code{GBR} offset
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@item @@(R0, GBR)
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GBR indexed
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@item @var{addr}
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@itemx @@(@var{disp}, PC)
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PC relative address (for branch or for addressing memory). The
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@code{@value{AS}} implementation allows you to use the simpler form
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@var{addr} anywhere a PC relative address is called for; the alternate
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form is supported for compatibility with other assemblers.
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@item #@var{imm}
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Immediate data
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@end table
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@node SH Floating Point
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@section Floating Point
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@cindex floating point, SH (@sc{ieee})
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@cindex SH floating point (@sc{ieee})
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SH2E, SH3E and SH4 groups have on-chip floating-point unit (FPU). Other
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SH groups can use @code{.float} directive to generate @sc{ieee}
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floating-point numbers.
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SH2E and SH3E support single-precision floating point calculations as
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well as entirely PCAPI compatible emulation of double-precision
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floating point calculations. SH2E and SH3E instructions are a subset of
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the floating point calculations conforming to the IEEE754 standard.
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In addition to single-precision and double-precision floating-point
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operation capability, the on-chip FPU of SH4 has a 128-bit graphic
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engine that enables 32-bit floating-point data to be processed 128
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bits at a time. It also supports 4 * 4 array operations and inner
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product operations. Also, a superscalar architecture is employed that
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enables simultaneous execution of two instructions (including FPU
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instructions), providing performance of up to twice that of
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conventional architectures at the same frequency.
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@node SH Directives
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@section SH Machine Directives
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@cindex SH machine directives
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@cindex machine directives, SH
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@cindex @code{uaword} directive, SH
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@cindex @code{ualong} directive, SH
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@table @code
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@item uaword
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@itemx ualong
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@code{@value{AS}} will issue a warning when a misaligned @code{.word} or
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@code{.long} directive is used. You may use @code{.uaword} or
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@code{.ualong} to indicate that the value is intentionally misaligned.
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@end table
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@node SH Opcodes
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@section Opcodes
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@cindex SH opcode summary
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@cindex opcode summary, SH
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@cindex mnemonics, SH
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@cindex instruction summary, SH
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For detailed information on the SH machine instruction set, see
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@cite{SH-Microcomputer User's Manual} (Renesas) or
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@cite{SH-4 32-bit CPU Core Architecture} (SuperH) and
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@cite{SuperH (SH) 64-Bit RISC Series} (SuperH).
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@code{@value{AS}} implements all the standard SH opcodes. No additional
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pseudo-instructions are needed on this family. Note, however, that
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because @code{@value{AS}} supports a simpler form of PC-relative
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addressing, you may simply write (for example)
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@example
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mov.l bar,r0
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@end example
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@noindent
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where other assemblers might require an explicit displacement to
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@code{bar} from the program counter:
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@example
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mov.l @@(@var{disp}, PC)
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@end example
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@ifset SMALL
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@c this table, due to the multi-col faking and hardcoded order, looks silly
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@c except in smallbook. See comments below "@set SMALL" near top of this file.
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Here is a summary of SH opcodes:
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@page
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@smallexample
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@i{Legend:}
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Rn @r{a numbered register}
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Rm @r{another numbered register}
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#imm @r{immediate data}
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disp @r{displacement}
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disp8 @r{8-bit displacement}
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disp12 @r{12-bit displacement}
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add #imm,Rn lds.l @@Rn+,PR
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add Rm,Rn mac.w @@Rm+,@@Rn+
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addc Rm,Rn mov #imm,Rn
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addv Rm,Rn mov Rm,Rn
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and #imm,R0 mov.b Rm,@@(R0,Rn)
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and Rm,Rn mov.b Rm,@@-Rn
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and.b #imm,@@(R0,GBR) mov.b Rm,@@Rn
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bf disp8 mov.b @@(disp,Rm),R0
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bra disp12 mov.b @@(disp,GBR),R0
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bsr disp12 mov.b @@(R0,Rm),Rn
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bt disp8 mov.b @@Rm+,Rn
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clrmac mov.b @@Rm,Rn
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clrt mov.b R0,@@(disp,Rm)
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cmp/eq #imm,R0 mov.b R0,@@(disp,GBR)
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cmp/eq Rm,Rn mov.l Rm,@@(disp,Rn)
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cmp/ge Rm,Rn mov.l Rm,@@(R0,Rn)
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cmp/gt Rm,Rn mov.l Rm,@@-Rn
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cmp/hi Rm,Rn mov.l Rm,@@Rn
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cmp/hs Rm,Rn mov.l @@(disp,Rn),Rm
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cmp/pl Rn mov.l @@(disp,GBR),R0
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cmp/pz Rn mov.l @@(disp,PC),Rn
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cmp/str Rm,Rn mov.l @@(R0,Rm),Rn
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div0s Rm,Rn mov.l @@Rm+,Rn
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div0u mov.l @@Rm,Rn
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div1 Rm,Rn mov.l R0,@@(disp,GBR)
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exts.b Rm,Rn mov.w Rm,@@(R0,Rn)
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exts.w Rm,Rn mov.w Rm,@@-Rn
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extu.b Rm,Rn mov.w Rm,@@Rn
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extu.w Rm,Rn mov.w @@(disp,Rm),R0
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jmp @@Rn mov.w @@(disp,GBR),R0
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jsr @@Rn mov.w @@(disp,PC),Rn
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ldc Rn,GBR mov.w @@(R0,Rm),Rn
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ldc Rn,SR mov.w @@Rm+,Rn
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ldc Rn,VBR mov.w @@Rm,Rn
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|
ldc.l @@Rn+,GBR mov.w R0,@@(disp,Rm)
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|
ldc.l @@Rn+,SR mov.w R0,@@(disp,GBR)
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|
ldc.l @@Rn+,VBR mova @@(disp,PC),R0
|
|
lds Rn,MACH movt Rn
|
|
lds Rn,MACL muls Rm,Rn
|
|
lds Rn,PR mulu Rm,Rn
|
|
lds.l @@Rn+,MACH neg Rm,Rn
|
|
lds.l @@Rn+,MACL negc Rm,Rn
|
|
@page
|
|
nop stc VBR,Rn
|
|
not Rm,Rn stc.l GBR,@@-Rn
|
|
or #imm,R0 stc.l SR,@@-Rn
|
|
or Rm,Rn stc.l VBR,@@-Rn
|
|
or.b #imm,@@(R0,GBR) sts MACH,Rn
|
|
rotcl Rn sts MACL,Rn
|
|
rotcr Rn sts PR,Rn
|
|
rotl Rn sts.l MACH,@@-Rn
|
|
rotr Rn sts.l MACL,@@-Rn
|
|
rte sts.l PR,@@-Rn
|
|
rts sub Rm,Rn
|
|
sett subc Rm,Rn
|
|
shal Rn subv Rm,Rn
|
|
shar Rn swap.b Rm,Rn
|
|
shll Rn swap.w Rm,Rn
|
|
shll16 Rn tas.b @@Rn
|
|
shll2 Rn trapa #imm
|
|
shll8 Rn tst #imm,R0
|
|
shlr Rn tst Rm,Rn
|
|
shlr16 Rn tst.b #imm,@@(R0,GBR)
|
|
shlr2 Rn xor #imm,R0
|
|
shlr8 Rn xor Rm,Rn
|
|
sleep xor.b #imm,@@(R0,GBR)
|
|
stc GBR,Rn xtrct Rm,Rn
|
|
stc SR,Rn
|
|
@end smallexample
|
|
@end ifset
|
|
|
|
@ifset Renesas-all
|
|
@ifclear GENERIC
|
|
@raisesections
|
|
@end ifclear
|
|
@end ifset
|
|
|