280 lines
7.1 KiB
C
280 lines
7.1 KiB
C
/* Main simulator entry points specific to the OR1K.
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Copyright (C) 2017-2018 Free Software Foundation, Inc.
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This file is part of GDB, the GNU debugger.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#include "sim-main.h"
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#include "sim-options.h"
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#include "libiberty.h"
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#include "bfd.h"
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#ifdef HAVE_STRING_H
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#include <string.h>
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#else
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#ifdef HAVE_STRINGS_H
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#include <strings.h>
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#endif
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#endif
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#ifdef HAVE_STDLIB_H
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#include <stdlib.h>
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#endif
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static void free_state (SIM_DESC);
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/* Cover function of sim_state_free to free the cpu buffers as well. */
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static void
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free_state (SIM_DESC sd)
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{
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if (STATE_MODULES (sd) != NULL)
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sim_module_uninstall (sd);
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sim_cpu_free_all (sd);
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sim_state_free (sd);
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}
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/* Defaults for user passed arguments. */
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static const USI or1k_default_vr = 0x0;
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static const USI or1k_default_upr = 0x0
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| SPR_FIELD_MASK_SYS_UPR_UP;
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static const USI or1k_default_cpucfgr = 0x0
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| SPR_FIELD_MASK_SYS_CPUCFGR_OB32S
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| SPR_FIELD_MASK_SYS_CPUCFGR_OF32S;
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static UWI or1k_upr;
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static UWI or1k_vr;
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static UWI or1k_cpucfgr;
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enum
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{
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OPTION_OR1K_VR,
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OPTION_OR1K_UPR,
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OPTION_OR1K_CPUCFGR = OPTION_START,
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};
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/* Setup help and handlers for the user defined arguments. */
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DECLARE_OPTION_HANDLER (or1k_option_handler);
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static const OPTION or1k_options[] = {
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{{"or1k-cpucfgr", required_argument, NULL, OPTION_OR1K_CPUCFGR},
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'\0', "INTEGER|default", "Set simulator CPUCFGR value",
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or1k_option_handler},
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{{"or1k-vr", required_argument, NULL, OPTION_OR1K_VR},
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'\0', "INTEGER|default", "Set simulator VR value",
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or1k_option_handler},
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{{"or1k-upr", required_argument, NULL, OPTION_OR1K_UPR},
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'\0', "INTEGER|default", "Set simulator UPR value",
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or1k_option_handler},
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{{NULL, no_argument, NULL, 0}, '\0', NULL, NULL, NULL}
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};
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/* Handler for parsing user defined arguments. Currently we support
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configuring some of the CPU implementation specific registers including
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the Version Register (VR), the Unit Present Register (UPR) and the CPU
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Configuration Register (CPUCFGR). */
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SIM_RC
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or1k_option_handler (SIM_DESC sd, sim_cpu *cpu, int opt, char *arg,
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int is_command)
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{
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switch (opt)
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{
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case OPTION_OR1K_VR:
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if (strcmp ("default", arg) == 0)
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or1k_vr = or1k_default_vr;
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else
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{
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unsigned long long n;
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char *endptr;
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n = strtoull (arg, &endptr, 0);
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if (*arg != '\0' && *endptr == '\0')
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or1k_vr = n;
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else
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return SIM_RC_FAIL;
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}
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return SIM_RC_OK;
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case OPTION_OR1K_UPR:
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if (strcmp ("default", arg) == 0)
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or1k_upr = or1k_default_upr;
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else
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{
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unsigned long long n;
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char *endptr;
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n = strtoull (arg, &endptr, 0);
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if (*arg != '\0' && *endptr == '\0')
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or1k_upr = n;
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else
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{
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sim_io_eprintf
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(sd, "invalid argument to option --or1k-upr: `%s'\n", arg);
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return SIM_RC_FAIL;
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}
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}
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return SIM_RC_OK;
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case OPTION_OR1K_CPUCFGR:
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if (strcmp ("default", arg) == 0)
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or1k_cpucfgr = or1k_default_cpucfgr;
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else
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{
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unsigned long long n;
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char *endptr;
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n = strtoull (arg, &endptr, 0);
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if (*arg != '\0' && *endptr == '\0')
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or1k_cpucfgr = n;
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else
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{
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sim_io_eprintf
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(sd, "invalid argument to option --or1k-cpucfgr: `%s'\n", arg);
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return SIM_RC_FAIL;
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}
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}
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return SIM_RC_OK;
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default:
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sim_io_eprintf (sd, "Unknown or1k option %d\n", opt);
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return SIM_RC_FAIL;
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}
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return SIM_RC_FAIL;
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}
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/* Create an instance of the simulator. */
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SIM_DESC
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sim_open (SIM_OPEN_KIND kind, host_callback *callback, struct bfd *abfd,
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char * const *argv)
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{
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SIM_DESC sd = sim_state_alloc (kind, callback);
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char c;
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int i;
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/* The cpu data is kept in a separately allocated chunk of memory. */
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if (sim_cpu_alloc_all (sd, 1, cgen_cpu_max_extra_bytes ()) != SIM_RC_OK)
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{
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free_state (sd);
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return 0;
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}
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/* Perform initial sim setups. */
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if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
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{
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free_state (sd);
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return 0;
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}
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or1k_upr = or1k_default_upr;
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or1k_vr = or1k_default_vr;
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or1k_cpucfgr = or1k_default_cpucfgr;
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sim_add_option_table (sd, NULL, or1k_options);
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/* Parse the user passed arguments. */
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if (sim_parse_args (sd, argv) != SIM_RC_OK)
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{
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free_state (sd);
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return 0;
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}
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/* Allocate core managed memory if none specified by user.
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Use address 4 here in case the user wanted address 0 unmapped. */
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if (sim_core_read_buffer (sd, NULL, read_map, &c, 4, 1) == 0)
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{
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sim_do_commandf (sd, "memory region 0,0x%x", OR1K_DEFAULT_MEM_SIZE);
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}
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/* Check for/establish the reference program image. */
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if (sim_analyze_program (sd,
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(STATE_PROG_ARGV (sd) != NULL
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? *STATE_PROG_ARGV (sd)
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: NULL), abfd) != SIM_RC_OK)
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{
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free_state (sd);
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return 0;
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}
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/* Establish any remaining configuration options. */
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if (sim_config (sd) != SIM_RC_OK)
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{
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free_state (sd);
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return 0;
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}
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if (sim_post_argv_init (sd) != SIM_RC_OK)
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{
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free_state (sd);
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return 0;
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}
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/* Make sure delay slot mode is consistent with the loaded binary. */
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if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_or1knd)
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or1k_cpucfgr |= SPR_FIELD_MASK_SYS_CPUCFGR_ND;
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else
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or1k_cpucfgr &= ~SPR_FIELD_MASK_SYS_CPUCFGR_ND;
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/* Open a copy of the cpu descriptor table and initialize the
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disassembler. These initialization functions are generated by CGEN
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using the binutils scheme cpu description files. */
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{
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CGEN_CPU_DESC cd =
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or1k_cgen_cpu_open_1 (STATE_ARCHITECTURE (sd)->printable_name,
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CGEN_ENDIAN_BIG);
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for (i = 0; i < MAX_NR_PROCESSORS; ++i)
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{
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SIM_CPU *cpu = STATE_CPU (sd, i);
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CPU_CPU_DESC (cpu) = cd;
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CPU_DISASSEMBLER (cpu) = sim_cgen_disassemble_insn;
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}
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or1k_cgen_init_dis (cd);
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}
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/* Initialize various cgen things not done by common framework.
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Must be done after or1k_cgen_cpu_open. */
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cgen_init (sd);
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/* Do some final OpenRISC sim specific initializations. */
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for (c = 0; c < MAX_NR_PROCESSORS; ++c)
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{
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SIM_CPU *cpu = STATE_CPU (sd, i);
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/* Only needed for profiling, but the structure member is small. */
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memset (CPU_OR1K_MISC_PROFILE (cpu), 0,
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sizeof (*CPU_OR1K_MISC_PROFILE (cpu)));
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or1k_cpu_init (sd, cpu, or1k_vr, or1k_upr, or1k_cpucfgr);
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}
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return sd;
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}
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SIM_RC
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sim_create_inferior (SIM_DESC sd, struct bfd *abfd,
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char * const *argv, char * const *envp)
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{
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SIM_CPU *current_cpu = STATE_CPU (sd, 0);
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SIM_ADDR addr;
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if (abfd != NULL)
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addr = bfd_get_start_address (abfd);
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else
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addr = 0;
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sim_pc_set (current_cpu, addr);
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return SIM_RC_OK;
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}
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