0fd3a4776c
bfd: * elf32-xtensa.c (vsprint_msg): Add format attribute. Fix format bugs. * vms.h (_bfd_vms_debug): Add format attribute. (_bfd_vms_debug, _bfd_hexdump): Fix typos. binutils: * bucomm.h (report): Add format attribute. * dlltool.c (inform): Likewise. * dllwrap.c (display, inform, warn): Likewise. * objdump.c (objdump_sprintf): Likewise. * readelf.c (error, warn): Likewise. Fix format bugs. gas: * config/tc-tic30.c (debug): Add format attribute. Fix format bugs. include: * dis-asm.h (fprintf_ftype): Add format attribute. opcodes: * arc-dis.c, arm-dis.c, cris-dis.c, crx-dis.c, d10v-dis.c, d30v-dis.c, fr30-dis.c, h8300-dis.c, h8500-dis.c, i860-dis.c, ia64-dis.c, ip2k-dis.c, m10200-dis.c, m10300-dis.c, m88k-dis.c, mcore-dis.c, mips-dis.c, ms1-dis.c, or32-dis.c, ppc-dis.c, sh64-dis.c, sparc-dis.c, tic4x-dis.c, tic80-dis.c, v850-dis.c: Fix format bugs. * ia64-gen.c (fail, warn): Add format attribute. * or32-opc.c (debug): Likewise.
297 lines
7.3 KiB
C
297 lines
7.3 KiB
C
/* Disassemble D10V instructions.
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Copyright 1996, 1997, 1998, 2000, 2001, 2005 Free Software Foundation, Inc.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
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MA 02110-1301, USA. */
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#include <stdio.h>
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#include "sysdep.h"
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#include "opcode/d10v.h"
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#include "dis-asm.h"
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/* The PC wraps at 18 bits, except for the segment number,
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so use this mask to keep the parts we want. */
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#define PC_MASK 0x0303FFFF
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static void
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print_operand (struct d10v_operand *oper,
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unsigned long insn,
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struct d10v_opcode *op,
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bfd_vma memaddr,
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struct disassemble_info *info)
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{
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int num, shift;
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if (oper->flags == OPERAND_ATMINUS)
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{
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(*info->fprintf_func) (info->stream, "@-");
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return;
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}
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if (oper->flags == OPERAND_MINUS)
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{
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(*info->fprintf_func) (info->stream, "-");
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return;
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}
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if (oper->flags == OPERAND_PLUS)
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{
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(*info->fprintf_func) (info->stream, "+");
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return;
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}
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if (oper->flags == OPERAND_ATSIGN)
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{
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(*info->fprintf_func) (info->stream, "@");
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return;
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}
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if (oper->flags == OPERAND_ATPAR)
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{
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(*info->fprintf_func) (info->stream, "@(");
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return;
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}
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shift = oper->shift;
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/* The LONG_L format shifts registers over by 15. */
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if (op->format == LONG_L && (oper->flags & OPERAND_REG))
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shift += 15;
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num = (insn >> shift) & (0x7FFFFFFF >> (31 - oper->bits));
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if (oper->flags & OPERAND_REG)
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{
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int i;
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int match = 0;
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num += (oper->flags
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& (OPERAND_GPR | OPERAND_FFLAG | OPERAND_CFLAG | OPERAND_CONTROL));
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if (oper->flags & (OPERAND_ACC0 | OPERAND_ACC1))
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num += num ? OPERAND_ACC1 : OPERAND_ACC0;
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for (i = 0; i < d10v_reg_name_cnt (); i++)
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{
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if (num == (d10v_predefined_registers[i].value & ~ OPERAND_SP))
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{
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if (d10v_predefined_registers[i].pname)
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(*info->fprintf_func) (info->stream, "%s",
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d10v_predefined_registers[i].pname);
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else
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(*info->fprintf_func) (info->stream, "%s",
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d10v_predefined_registers[i].name);
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match = 1;
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break;
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}
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}
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if (match == 0)
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{
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/* This would only get executed if a register was not in the
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register table. */
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if (oper->flags & (OPERAND_ACC0 | OPERAND_ACC1))
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(*info->fprintf_func) (info->stream, "a");
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else if (oper->flags & OPERAND_CONTROL)
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(*info->fprintf_func) (info->stream, "cr");
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else if (oper->flags & OPERAND_REG)
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(*info->fprintf_func) (info->stream, "r");
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(*info->fprintf_func) (info->stream, "%d", num & REGISTER_MASK);
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}
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}
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else
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{
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/* Addresses are right-shifted by 2. */
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if (oper->flags & OPERAND_ADDR)
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{
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long max;
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int neg = 0;
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max = (1 << (oper->bits - 1));
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if (num & max)
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{
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num = -num & ((1 << oper->bits) - 1);
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neg = 1;
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}
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num = num << 2;
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if (info->flags & INSN_HAS_RELOC)
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(*info->print_address_func) (num & PC_MASK, info);
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else
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{
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if (neg)
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(*info->print_address_func) ((memaddr - num) & PC_MASK, info);
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else
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(*info->print_address_func) ((memaddr + num) & PC_MASK, info);
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}
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}
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else
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{
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if (oper->flags & OPERAND_SIGNED)
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{
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int max = (1 << (oper->bits - 1));
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if (num & max)
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{
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num = -num & ((1 << oper->bits) - 1);
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(*info->fprintf_func) (info->stream, "-");
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}
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}
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(*info->fprintf_func) (info->stream, "0x%x", num);
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}
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}
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}
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static void
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dis_long (unsigned long insn,
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bfd_vma memaddr,
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struct disassemble_info *info)
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{
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int i;
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struct d10v_opcode *op = (struct d10v_opcode *) d10v_opcodes;
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struct d10v_operand *oper;
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int need_paren = 0;
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int match = 0;
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while (op->name)
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{
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if ((op->format & LONG_OPCODE)
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&& ((op->mask & insn) == (unsigned long) op->opcode))
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{
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match = 1;
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(*info->fprintf_func) (info->stream, "%s\t", op->name);
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for (i = 0; op->operands[i]; i++)
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{
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oper = (struct d10v_operand *) &d10v_operands[op->operands[i]];
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if (oper->flags == OPERAND_ATPAR)
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need_paren = 1;
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print_operand (oper, insn, op, memaddr, info);
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if (op->operands[i + 1] && oper->bits
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&& d10v_operands[op->operands[i + 1]].flags != OPERAND_PLUS
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&& d10v_operands[op->operands[i + 1]].flags != OPERAND_MINUS)
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(*info->fprintf_func) (info->stream, ", ");
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}
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break;
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}
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op++;
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}
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if (!match)
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(*info->fprintf_func) (info->stream, ".long\t0x%08lx", insn);
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if (need_paren)
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(*info->fprintf_func) (info->stream, ")");
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}
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static void
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dis_2_short (unsigned long insn,
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bfd_vma memaddr,
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struct disassemble_info *info,
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int order)
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{
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int i, j;
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unsigned int ins[2];
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struct d10v_opcode *op;
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int match, num_match = 0;
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struct d10v_operand *oper;
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int need_paren = 0;
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ins[0] = (insn & 0x3FFFFFFF) >> 15;
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ins[1] = insn & 0x00007FFF;
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for (j = 0; j < 2; j++)
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{
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op = (struct d10v_opcode *) d10v_opcodes;
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match = 0;
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while (op->name)
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{
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if ((op->format & SHORT_OPCODE)
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&& ((((unsigned int) op->mask) & ins[j])
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== (unsigned int) op->opcode))
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{
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(*info->fprintf_func) (info->stream, "%s\t", op->name);
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for (i = 0; op->operands[i]; i++)
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{
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oper = (struct d10v_operand *) &d10v_operands[op->operands[i]];
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if (oper->flags == OPERAND_ATPAR)
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need_paren = 1;
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print_operand (oper, ins[j], op, memaddr, info);
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if (op->operands[i + 1] && oper->bits
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&& d10v_operands[op->operands[i + 1]].flags != OPERAND_PLUS
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&& d10v_operands[op->operands[i + 1]].flags != OPERAND_MINUS)
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(*info->fprintf_func) (info->stream, ", ");
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}
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match = 1;
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num_match++;
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break;
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}
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op++;
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}
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if (!match)
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(*info->fprintf_func) (info->stream, "unknown");
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switch (order)
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{
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case 0:
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(*info->fprintf_func) (info->stream, "\t->\t");
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order = -1;
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break;
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case 1:
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(*info->fprintf_func) (info->stream, "\t<-\t");
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order = -1;
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break;
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case 2:
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(*info->fprintf_func) (info->stream, "\t||\t");
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order = -1;
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break;
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default:
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break;
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}
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}
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if (num_match == 0)
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(*info->fprintf_func) (info->stream, ".long\t0x%08lx", insn);
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if (need_paren)
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(*info->fprintf_func) (info->stream, ")");
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}
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int
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print_insn_d10v (bfd_vma memaddr, struct disassemble_info *info)
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{
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int status;
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bfd_byte buffer[4];
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unsigned long insn;
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status = (*info->read_memory_func) (memaddr, buffer, 4, info);
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if (status != 0)
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{
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(*info->memory_error_func) (status, memaddr, info);
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return -1;
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}
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insn = bfd_getb32 (buffer);
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status = insn & FM11;
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switch (status)
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{
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case 0:
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dis_2_short (insn, memaddr, info, 2);
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break;
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case FM01:
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dis_2_short (insn, memaddr, info, 0);
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break;
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case FM10:
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dis_2_short (insn, memaddr, info, 1);
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break;
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case FM11:
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dis_long (insn, memaddr, info);
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break;
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}
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return 4;
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}
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