5eb3690ee9
* bfin-dis.c: Likewise. * i860-dis.c: Likewise. * ia64-dis.c: Likewise. * ia64-gen.c: Likewise. * m68hc11-dis.c: Likewise. * mmix-dis.c: Likewise. * msp430-dis.c: Likewise. * or32-dis.c: Likewise. * rl78-dis.c: Likewise. * rx-dis.c: Likewise. * tic4x-dis.c: Likewise. * tilegx-opc.c: Likewise. * tilepro-opc.c: Likewise. * rx-decode.c: Regenerate.
287 lines
8.2 KiB
C
287 lines
8.2 KiB
C
/* Disassembler for the i860.
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Copyright 2000, 2003, 2005, 2007, 2012 Free Software Foundation, Inc.
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Contributed by Jason Eckhardt <jle@cygnus.com>.
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This file is part of the GNU opcodes library.
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This library is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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It is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
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MA 02110-1301, USA. */
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#include "sysdep.h"
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#include "dis-asm.h"
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#include "opcode/i860.h"
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/* Later we should probably choose the prefix based on which OS flavor. */
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#define I860_REG_PREFIX "%"
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/* Integer register names (encoded as 0..31 in the instruction). */
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static const char *const grnames[] =
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{"r0", "r1", "sp", "fp", "r4", "r5", "r6", "r7",
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"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
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"r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
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"r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"};
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/* FP register names (encoded as 0..31 in the instruction). */
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static const char *const frnames[] =
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{"f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
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"f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
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"f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
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"f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31"};
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/* Control/status register names (encoded as 0..11 in the instruction).
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Registers bear, ccr, p0, p1, p2 and p3 are XP only. */
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static const char *const crnames[] =
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{"fir", "psr", "dirbase", "db", "fsr", "epsr", "bear", "ccr",
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"p0", "p1", "p2", "p3", "--", "--", "--", "--" };
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/* True if opcode is xor, xorh, and, andh, or, orh, andnot, andnoth. */
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#define BITWISE_OP(op) ((op) == 0x30 || (op) == 0x31 \
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|| (op) == 0x34 || (op) == 0x35 \
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|| (op) == 0x38 || (op) == 0x39 \
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|| (op) == 0x3c || (op) == 0x3d \
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|| (op) == 0x33 || (op) == 0x37 \
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|| (op) == 0x3b || (op) == 0x3f)
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/* Sign extend N-bit number. */
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static int
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sign_ext (unsigned int x, int n)
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{
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int t;
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t = x >> (n - 1);
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t = ((-t) << n) | x;
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return t;
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}
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/* Print a PC-relative branch offset. VAL is the sign extended value
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from the branch instruction. */
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static void
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print_br_address (disassemble_info *info, bfd_vma memaddr, long val)
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{
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long adj = (long)memaddr + 4 + (val << 2);
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(*info->fprintf_func) (info->stream, "0x%08lx", adj);
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/* Attempt to obtain a symbol for the target address. */
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if (info->print_address_func && adj != 0)
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{
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(*info->fprintf_func) (info->stream, "\t// ");
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(*info->print_address_func) (adj, info);
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}
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}
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/* Print one instruction. */
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int
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print_insn_i860 (bfd_vma memaddr, disassemble_info *info)
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{
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bfd_byte buff[4];
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unsigned int insn, i;
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int status;
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const struct i860_opcode *opcode = 0;
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status = (*info->read_memory_func) (memaddr, buff, sizeof (buff), info);
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if (status != 0)
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{
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(*info->memory_error_func) (status, memaddr, info);
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return -1;
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}
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/* Note that i860 instructions are always accessed as little endian
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data, regardless of the endian mode of the i860. */
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insn = bfd_getl32 (buff);
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status = 0;
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i = 0;
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while (i860_opcodes[i].name != NULL)
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{
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opcode = &i860_opcodes[i];
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if ((insn & opcode->match) == opcode->match
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&& (insn & opcode->lose) == 0)
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{
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status = 1;
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break;
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}
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++i;
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}
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if (status == 0)
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{
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/* Instruction not in opcode table. */
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(*info->fprintf_func) (info->stream, ".long %#08x", insn);
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}
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else
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{
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const char *s;
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int val;
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/* If this a flop (or a shrd) and its dual bit is set,
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prefix with 'd.'. */
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if (((insn & 0xfc000000) == 0x48000000
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|| (insn & 0xfc000000) == 0xb0000000)
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&& (insn & 0x200))
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(*info->fprintf_func) (info->stream, "d.%s\t", opcode->name);
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else
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(*info->fprintf_func) (info->stream, "%s\t", opcode->name);
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for (s = opcode->args; *s; s++)
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{
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switch (*s)
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{
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/* Integer register (src1). */
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case '1':
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(*info->fprintf_func) (info->stream, "%s%s", I860_REG_PREFIX,
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grnames[(insn >> 11) & 0x1f]);
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break;
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/* Integer register (src2). */
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case '2':
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(*info->fprintf_func) (info->stream, "%s%s", I860_REG_PREFIX,
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grnames[(insn >> 21) & 0x1f]);
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break;
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/* Integer destination register. */
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case 'd':
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(*info->fprintf_func) (info->stream, "%s%s", I860_REG_PREFIX,
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grnames[(insn >> 16) & 0x1f]);
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break;
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/* Floating-point register (src1). */
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case 'e':
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(*info->fprintf_func) (info->stream, "%s%s", I860_REG_PREFIX,
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frnames[(insn >> 11) & 0x1f]);
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break;
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/* Floating-point register (src2). */
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case 'f':
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(*info->fprintf_func) (info->stream, "%s%s", I860_REG_PREFIX,
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frnames[(insn >> 21) & 0x1f]);
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break;
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/* Floating-point destination register. */
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case 'g':
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(*info->fprintf_func) (info->stream, "%s%s", I860_REG_PREFIX,
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frnames[(insn >> 16) & 0x1f]);
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break;
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/* Control register. */
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case 'c':
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(*info->fprintf_func) (info->stream, "%s%s", I860_REG_PREFIX,
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crnames[(insn >> 21) & 0xf]);
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break;
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/* 16-bit immediate (sign extend, except for bitwise ops). */
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case 'i':
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if (BITWISE_OP ((insn & 0xfc000000) >> 26))
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(*info->fprintf_func) (info->stream, "0x%04x",
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(unsigned int) (insn & 0xffff));
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else
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(*info->fprintf_func) (info->stream, "%d",
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sign_ext ((insn & 0xffff), 16));
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break;
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/* 16-bit immediate, aligned (2^0, ld.b). */
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case 'I':
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(*info->fprintf_func) (info->stream, "%d",
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sign_ext ((insn & 0xffff), 16));
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break;
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/* 16-bit immediate, aligned (2^1, ld.s). */
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case 'J':
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(*info->fprintf_func) (info->stream, "%d",
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sign_ext ((insn & 0xfffe), 16));
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break;
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/* 16-bit immediate, aligned (2^2, ld.l, {p}fld.l, fst.l). */
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case 'K':
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(*info->fprintf_func) (info->stream, "%d",
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sign_ext ((insn & 0xfffc), 16));
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break;
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/* 16-bit immediate, aligned (2^3, {p}fld.d, fst.d). */
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case 'L':
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(*info->fprintf_func) (info->stream, "%d",
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sign_ext ((insn & 0xfff8), 16));
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break;
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/* 16-bit immediate, aligned (2^4, {p}fld.q, fst.q). */
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case 'M':
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(*info->fprintf_func) (info->stream, "%d",
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sign_ext ((insn & 0xfff0), 16));
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break;
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/* 5-bit immediate (zero extend). */
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case '5':
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(*info->fprintf_func) (info->stream, "%d",
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((insn >> 11) & 0x1f));
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break;
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/* Split 16 bit immediate (20..16:10..0). */
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case 's':
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val = ((insn >> 5) & 0xf800) | (insn & 0x07ff);
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(*info->fprintf_func) (info->stream, "%d",
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sign_ext (val, 16));
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break;
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/* Split 16 bit immediate, aligned. (2^0, st.b). */
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case 'S':
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val = ((insn >> 5) & 0xf800) | (insn & 0x07ff);
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(*info->fprintf_func) (info->stream, "%d",
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sign_ext (val, 16));
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break;
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/* Split 16 bit immediate, aligned. (2^1, st.s). */
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case 'T':
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val = ((insn >> 5) & 0xf800) | (insn & 0x07fe);
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(*info->fprintf_func) (info->stream, "%d",
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sign_ext (val, 16));
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break;
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/* Split 16 bit immediate, aligned. (2^2, st.l). */
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case 'U':
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val = ((insn >> 5) & 0xf800) | (insn & 0x07fc);
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(*info->fprintf_func) (info->stream, "%d",
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sign_ext (val, 16));
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break;
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/* 26-bit PC relative immediate (lbroff). */
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case 'l':
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val = sign_ext ((insn & 0x03ffffff), 26);
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print_br_address (info, memaddr, val);
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break;
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/* 16-bit PC relative immediate (sbroff). */
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case 'r':
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val = sign_ext ((((insn >> 5) & 0xf800) | (insn & 0x07ff)), 16);
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print_br_address (info, memaddr, val);
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break;
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default:
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(*info->fprintf_func) (info->stream, "%c", *s);
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break;
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}
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}
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}
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return sizeof (insn);
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}
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