364 lines
14 KiB
C
Executable File
364 lines
14 KiB
C
Executable File
/* Mips opcde list for GDB, the GNU debugger.
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Copyright (C) 1989 Free Software Foundation, Inc.
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Contributed by Nobuyuki Hikichi(hikichi@sra.junet)
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Made to work for little-endian machines, and debugged
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by Per Bothner (bothner@cs.wisc.edu).
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Many fixes contributed by Frank Yellin (fy@lucid.com).
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This file is part of GDB.
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GDB is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 1, or (at your option)
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any later version.
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GDB is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with GDB; see the file COPYING. If not, write to
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the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
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#if BITS_BIG_ENDIAN
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#define BIT_FIELDS_2(a,b) a;b;
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#define BIT_FIELDS_4(a,b,c,d) a;b;c;d;
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#define BIT_FIELDS_6(a,b,c,d,e,f) a;b;c;d;e;f;
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#else
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#define BIT_FIELDS_2(a,b) b;a;
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#define BIT_FIELDS_4(a,b,c,d) d;c;b;a;
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#define BIT_FIELDS_6(a,b,c,d,e,f) f;e;d;c;b;a;
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#endif
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struct op_i_fmt
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{
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BIT_FIELDS_4(
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unsigned op : 6,
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unsigned rs : 5,
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unsigned rt : 5,
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unsigned immediate : 16)
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};
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struct op_j_fmt
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{
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BIT_FIELDS_2(
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unsigned op : 6,
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unsigned target : 26)
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};
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struct op_r_fmt
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{
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BIT_FIELDS_6(
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unsigned op : 6,
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unsigned rs : 5,
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unsigned rt : 5,
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unsigned rd : 5,
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unsigned shamt : 5,
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unsigned funct : 6)
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};
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struct fop_i_fmt
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{
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BIT_FIELDS_4(
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unsigned op : 6,
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unsigned rs : 5,
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unsigned rt : 5,
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unsigned immediate : 16)
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};
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struct op_b_fmt
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{
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BIT_FIELDS_4(
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unsigned op : 6,
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unsigned rs : 5,
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unsigned rt : 5,
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short delta : 16)
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};
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struct fop_r_fmt
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{
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BIT_FIELDS_6(
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unsigned op : 6,
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unsigned fmt : 5,
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unsigned ft : 5,
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unsigned fs : 5,
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unsigned fd : 5,
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unsigned funct : 6)
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};
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struct mips_opcode
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{
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char *name;
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unsigned long opcode;
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unsigned long match;
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char *args;
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int bdelay; /* Nonzero if delayed branch. */
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};
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/* args format;
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"s" rs: source register specifier
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"t" rt: target register
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"i" immediate
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"a" target address
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"c" branch condition
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"d" rd: destination register specifier
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"h" shamt: shift amount
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"f" funct: function field
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for fpu
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"S" fs source 1 register
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"T" ft source 2 register
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"D" distination register
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*/
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#define one(x) (x << 26)
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#define op_func(x, y) ((x << 26) | y)
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#define op_cond(x, y) ((x << 26) | (y << 16))
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#define op_rs_func(x, y, z) ((x << 26) | (y << 21) | z)
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#define op_rs_b11(x, y, z) ((x << 26) | (y << 21) | z)
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#define op_o16(x, y) ((x << 26) | (y << 16))
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#define op_bc(x, y, z) ((x << 26) | (y << 21) | (z << 16))
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struct mips_opcode mips_opcodes[] =
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{
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/* These first opcodes are special cases of the ones in the comments */
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{"nop", 0, 0xffffffff, /*li*/ "", 0},
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{"li", op_bc(9,0,0), op_bc(0x3f,31,0), /*addiu*/ "t,j", 0},
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{"b", one(4), 0xffff0000, /*beq*/ "b", 1},
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{"move", op_func(0, 33), op_cond(0x3f,31)|0x7ff,/*addu*/ "d,s", 0},
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{"sll", op_func(0, 0), op_func(0x3f, 0x3f), "d,t,h", 0},
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{"srl", op_func(0, 2), op_func(0x3f, 0x3f), "d,t,h", 0},
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{"sra", op_func(0, 3), op_func(0x3f, 0x3f), "d,t,h", 0},
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{"sllv", op_func(0, 4), op_func(0x3f, 0x7ff), "d,t,s", 0},
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{"srlv", op_func(0, 6), op_func(0x3f, 0x7ff), "d,t,s", 0},
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{"srav", op_func(0, 7), op_func(0x3f, 0x7ff), "d,t,s", 0},
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{"jr", op_func(0, 8), op_func(0x3f, 0x1fffff), "s", 1},
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{"jalr", op_func(0, 9), op_func(0x3f, 0x1f07ff), "d,s", 1},
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{"syscall", op_func(0, 12), op_func(0x3f, 0x3f), "", 0},
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{"break", op_func(0, 13), op_func(0x3f, 0x3f), "", 0},
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{"mfhi", op_func(0, 16), op_func(0x3f, 0x03ff07ff), "d", 0},
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{"mthi", op_func(0, 17), op_func(0x3f, 0x1fffff), "s", 0},
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{"mflo", op_func(0, 18), op_func(0x3f, 0x03ff07ff), "d", 0},
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{"mtlo", op_func(0, 19), op_func(0x3f, 0x1fffff), "s", 0},
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{"mult", op_func(0, 24), op_func(0x3f, 0xffff), "s,t", 0},
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{"multu", op_func(0, 25), op_func(0x3f, 0xffff), "s,t", 0},
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{"div", op_func(0, 26), op_func(0x3f, 0xffff), "s,t", 0},
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{"divu", op_func(0, 27), op_func(0x3f, 0xffff), "s,t", 0},
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{"add", op_func(0, 32), op_func(0x3f, 0x7ff), "d,s,t", 0},
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{"addu", op_func(0, 33), op_func(0x3f, 0x7ff), "d,s,t", 0},
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{"sub", op_func(0, 34), op_func(0x3f, 0x7ff), "d,s,t", 0},
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{"subu", op_func(0, 35), op_func(0x3f, 0x7ff), "d,s,t", 0},
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{"and", op_func(0, 36), op_func(0x3f, 0x7ff), "d,s,t", 0},
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{"or", op_func(0, 37), op_func(0x3f, 0x7ff), "d,s,t", 0},
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{"xor", op_func(0, 38), op_func(0x3f, 0x7ff), "d,s,t", 0},
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{"nor", op_func(0, 39), op_func(0x3f, 0x7ff), "d,s,t", 0},
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{"slt", op_func(0, 42), op_func(0x3f, 0x7ff), "d,s,t", 0},
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{"sltu", op_func(0, 43), op_func(0x3f, 0x7ff), "d,s,t", 0},
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{"bltz", op_cond (1, 0), op_cond(0x3f, 0x1f), "s,b", 1},
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{"bgez", op_cond (1, 1), op_cond(0x3f, 0x1f), "s,b", 1},
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{"bltzal", op_cond (1, 16),op_cond(0x3f, 0x1f), "s,b", 1},
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{"bgezal", op_cond (1, 17),op_cond(0x3f, 0x1f), "s,b", 1},
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{"j", one(2), one(0x3f), "a", 1},
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{"jal", one(3), one(0x3f), "a", 1},
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{"beq", one(4), one(0x3f), "s,t,b", 1},
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{"bne", one(5), one(0x3f), "s,t,b", 1},
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{"blez", one(6), one(0x3f) | 0x1f0000, "s,b", 1},
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{"bgtz", one(7), one(0x3f) | 0x1f0000, "s,b", 1},
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{"addi", one(8), one(0x3f), "t,s,j", 0},
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{"addiu", one(9), one(0x3f), "t,s,j", 0},
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{"slti", one(10), one(0x3f), "t,s,j", 0},
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{"sltiu", one(11), one(0x3f), "t,s,j", 0},
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{"andi", one(12), one(0x3f), "t,s,i", 0},
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{"ori", one(13), one(0x3f), "t,s,i", 0},
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{"xori", one(14), one(0x3f), "t,s,i", 0},
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/* rs field is don't care field? */
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{"lui", one(15), one(0x3f), "t,i", 0},
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/* co processor 0 instruction */
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{"mfc0", op_rs_b11 (16, 0, 0), op_rs_b11(0x3f, 0x1f, 0x1ffff), "t,d", 0},
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{"cfc0", op_rs_b11 (16, 2, 0), op_rs_b11(0x3f, 0x1f, 0x1ffff), "t,d", 0},
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{"mtc0", op_rs_b11 (16, 4, 0), op_rs_b11(0x3f, 0x1f, 0x1ffff), "t,d", 0},
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{"ctc0", op_rs_b11 (16, 6, 0), op_rs_b11(0x3f, 0x1f, 0x1ffff), "t,d", 0},
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{"bc0f", op_o16(16, 0x100), op_o16(0x3f, 0x3ff), "b", 1},
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{"bc0f", op_o16(16, 0x180), op_o16(0x3f, 0x3ff), "b", 1},
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{"bc0t", op_o16(16, 0x101), op_o16(0x3f, 0x3ff), "b", 1},
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{"bc0t", op_o16(16, 0x181), op_o16(0x3f, 0x3ff), "b", 1},
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{"tlbr", op_rs_func(16, 0x10, 1), ~0, "", 0},
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{"tlbwi", op_rs_func(16, 0x10, 2), ~0, "", 0},
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{"tlbwr", op_rs_func(16, 0x10, 6), ~0, "", 0},
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{"tlbp", op_rs_func(16, 0x10, 8), ~0, "", 0},
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{"rfe", op_rs_func(16, 0x10, 16), ~0, "", 0},
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{"mfc1", op_rs_b11 (17, 0, 0), op_rs_b11(0x3f, 0x1f, 0),"t,S", 0},
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{"cfc1", op_rs_b11 (17, 2, 0), op_rs_b11(0x3f, 0x1f, 0),"t,S", 0},
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{"mtc1", op_rs_b11 (17, 4, 0), op_rs_b11(0x3f, 0x1f, 0),"t,S", 0},
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{"ctc1", op_rs_b11 (17, 6, 0), op_rs_b11(0x3f, 0x1f, 0),"t,S", 0},
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{"bc1f", op_o16(17, 0x100), op_o16(0x3f, 0x3ff), "b", 1},
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{"bc1f", op_o16(17, 0x180), op_o16(0x3f, 0x3ff), "b", 1},
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{"bc1t", op_o16(17, 0x101), op_o16(0x3f, 0x3ff), "b", 1},
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{"bc1t", op_o16(17, 0x181), op_o16(0x3f, 0x3ff), "b", 1},
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/* fpu instruction */
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{"add.s", op_rs_func(17, 0x10, 0),
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op_rs_func(0x3f, 0x1f, 0x3f), "D,S,T", 0},
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{"add.d", op_rs_func(17, 0x11, 0),
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op_rs_func(0x3f, 0x1f, 0x3f), "D,S,T", 0},
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{"sub.s", op_rs_func(17, 0x10, 1),
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op_rs_func(0x3f, 0x1f, 0x3f), "D,S,T", 0},
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{"sub.d", op_rs_func(17, 0x11, 1),
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op_rs_func(0x3f, 0x1f, 0x3f), "D,S,T", 0},
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{"mul.s", op_rs_func(17, 0x10, 2),
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op_rs_func(0x3f, 0x1f, 0x3f), "D,S,T", 0},
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{"mul.d", op_rs_func(17, 0x11, 2),
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op_rs_func(0x3f, 0x1f, 0x3f), "D,S,T", 0},
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{"div.s", op_rs_func(17, 0x10, 3),
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op_rs_func(0x3f, 0x1f, 0x3f), "D,S,T", 0},
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{"div.d", op_rs_func(17, 0x11, 3),
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op_rs_func(0x3f, 0x1f, 0x3f), "D,S,T", 0},
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{"abs.s", op_rs_func(17, 0x10, 5),
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op_rs_func(0x3f, 0x1f, 0x1f003f), "D,S", 0},
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{"abs.d", op_rs_func(17, 0x11, 5),
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op_rs_func(0x3f, 0x1f, 0x1f003f), "D,S", 0},
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{"mov.s", op_rs_func(17, 0x10, 6),
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op_rs_func(0x3f, 0x1f, 0x1f003f), "D,S", 0},
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{"mov.d", op_rs_func(17, 0x11, 6),
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op_rs_func(0x3f, 0x1f, 0x1f003f), "D,S", 0},
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{"neg.s", op_rs_func(17, 0x10, 7),
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op_rs_func(0x3f, 0x1f, 0x1f003f), "D,S", 0},
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{"neg.d", op_rs_func(17, 0x11, 7),
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op_rs_func(0x3f, 0x1f, 0x1f003f), "D,S", 0},
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{"cvt.s.s", op_rs_func(17, 0x10, 32),
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op_rs_func(0x3f, 0x1f, 0x1f003f), "D,S", 0},
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{"cvt.s.d", op_rs_func(17, 0x11, 32),
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op_rs_func(0x3f, 0x1f, 0x1f003f), "D,S", 0},
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{"cvt.s.w", op_rs_func(17, 0x14, 32),
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op_rs_func(0x3f, 0x1f, 0x1f003f), "D,S", 0},
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{"cvt.d.s", op_rs_func(17, 0x10, 33),
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op_rs_func(0x3f, 0x1f, 0x1f003f), "D,S", 0},
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{"cvt.d.d", op_rs_func(17, 0x11, 33),
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op_rs_func(0x3f, 0x1f, 0x1f003f), "D,S", 0},
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{"cvt.d.w", op_rs_func(17, 0x14, 33),
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op_rs_func(0x3f, 0x1f, 0x1f003f), "D,S", 0},
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{"cvt.w.s", op_rs_func(17, 0x10, 36),
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op_rs_func(0x3f, 0x1f, 0x1f003f), "D,S", 0},
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{"cvt.w.d", op_rs_func(17, 0x11, 36),
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op_rs_func(0x3f, 0x1f, 0x1f003f), "D,S", 0},
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{"c.f.s", op_rs_func(17, 0x10, 48),
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op_rs_func(0x3f, 0x1f, 0x7ff), "S,T", 0},
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{"c.f.d", op_rs_func(17, 0x11, 48),
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op_rs_func(0x3f, 0x1f, 0x7ff), "S,T", 0},
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{"c.un.s", op_rs_func(17, 0x10, 49),
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op_rs_func(0x3f, 0x1f, 0x7ff), "S,T", 0},
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{"c.un.d", op_rs_func(17, 0x11, 49),
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op_rs_func(0x3f, 0x1f, 0x7ff), "S,T", 0},
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{"c.eq.s", op_rs_func(17, 0x10, 50),
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op_rs_func(0x3f, 0x1f, 0x7ff), "S,T", 0},
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{"c.eq.d", op_rs_func(17, 0x11, 50),
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op_rs_func(0x3f, 0x1f, 0x7ff), "S,T", 0},
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{"c.ueq.s", op_rs_func(17, 0x10, 51),
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op_rs_func(0x3f, 0x1f, 0x7ff), "S,T", 0},
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{"c.ueq.d", op_rs_func(17, 0x11, 51),
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op_rs_func(0x3f, 0x1f, 0x7ff), "S,T", 0},
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{"c.olt.s", op_rs_func(17, 0x10, 52),
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op_rs_func(0x3f, 0x1f, 0x7ff), "S,T", 0},
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{"c.olt.d", op_rs_func(17, 0x11, 52),
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op_rs_func(0x3f, 0x1f, 0x7ff), "S,T", 0},
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{"c.ult.s", op_rs_func(17, 0x10, 53),
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op_rs_func(0x3f, 0x1f, 0x7ff), "S,T", 0},
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{"c.ult.d", op_rs_func(17, 0x11, 53),
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op_rs_func(0x3f, 0x1f, 0x7ff), "S,T", 0},
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{"c.ole.s", op_rs_func(17, 0x10, 54),
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op_rs_func(0x3f, 0x1f, 0x7ff), "S,T", 0},
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{"c.ole.d", op_rs_func(17, 0x11, 54),
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op_rs_func(0x3f, 0x1f, 0x7ff), "S,T", 0},
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{"c.ule.s", op_rs_func(17, 0x10, 55),
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op_rs_func(0x3f, 0x1f, 0x7ff), "S,T", 0},
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{"c.ule.d", op_rs_func(17, 0x11, 55),
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op_rs_func(0x3f, 0x1f, 0x7ff), "S,T", 0},
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{"c.sf.s", op_rs_func(17, 0x10, 56),
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op_rs_func(0x3f, 0x1f, 0x7ff), "S,T", 0},
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{"c.sf.d", op_rs_func(17, 0x11, 56),
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op_rs_func(0x3f, 0x1f, 0x7ff), "S,T", 0},
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{"c.ngle.s", op_rs_func(17, 0x10, 57),
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op_rs_func(0x3f, 0x1f, 0x7ff), "S,T", 0},
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{"c.ngle.d", op_rs_func(17, 0x11, 57),
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op_rs_func(0x3f, 0x1f, 0x7ff), "S,T", 0},
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{"c.seq.s", op_rs_func(17, 0x10, 58),
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op_rs_func(0x3f, 0x1f, 0x7ff), "S,T", 0},
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{"c.seq.d", op_rs_func(17, 0x11, 58),
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op_rs_func(0x3f, 0x1f, 0x7ff), "S,T", 0},
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{"c.ngl.s", op_rs_func(17, 0x10, 59),
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op_rs_func(0x3f, 0x1f, 0x7ff), "S,T", 0},
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{"c.ngl.d", op_rs_func(17, 0x11, 59),
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op_rs_func(0x3f, 0x1f, 0x7ff), "S,T", 0},
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{"c.lt.s", op_rs_func(17, 0x10, 60),
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op_rs_func(0x3f, 0x1f, 0x7ff), "S,T", 0},
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{"c.lt.d", op_rs_func(17, 0x11, 60),
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op_rs_func(0x3f, 0x1f, 0x7ff), "S,T", 0},
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{"c.nge.s", op_rs_func(17, 0x10, 61),
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op_rs_func(0x3f, 0x1f, 0x7ff), "S,T", 0},
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{"c.nge.d", op_rs_func(17, 0x11, 61),
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op_rs_func(0x3f, 0x1f, 0x7ff), "S,T", 0},
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{"c.le.s", op_rs_func(17, 0x10, 62),
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op_rs_func(0x3f, 0x1f, 0x7ff), "S,T", 0},
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{"c.le.d", op_rs_func(17, 0x11, 62),
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op_rs_func(0x3f, 0x1f, 0x7ff), "S,T", 0},
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{"c.ngt.s", op_rs_func(17, 0x10, 63),
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op_rs_func(0x3f, 0x1f, 0x7ff), "S,T", 0},
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{"c.ngt.d", op_rs_func(17, 0x11, 63),
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op_rs_func(0x3f, 0x1f, 0x7ff), "S,T", 0},
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/* co processor 2 instruction */
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{"mfc2", op_rs_b11 (18, 0, 0), op_rs_b11(0x3f, 0x1f, 0x1ffff), "t,d", 0},
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{"cfc2", op_rs_b11 (18, 2, 0), op_rs_b11(0x3f, 0x1f, 0x1ffff), "t,d", 0},
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{"mtc2", op_rs_b11 (18, 4, 0), op_rs_b11(0x3f, 0x1f, 0x1ffff), "t,d", 0},
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{"ctc2", op_rs_b11 (18, 6, 0), op_rs_b11(0x3f, 0x1f, 0x1ffff), "t,d", 0},
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{"bc2f", op_o16(18, 0x100), op_o16(0x3f, 0x3ff), "b", 1},
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{"bc2f", op_o16(18, 0x180), op_o16(0x3f, 0x3ff), "b", 1},
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{"bc2f", op_o16(18, 0x101), op_o16(0x3f, 0x3ff), "b", 1},
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{"bc2t", op_o16(18, 0x181), op_o16(0x3f, 0x3ff), "b", 1},
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|
|
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/* co processor 3 instruction */
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{"mtc3", op_rs_b11 (19, 0, 0), op_rs_b11(0x3f, 0x1f, 0x1ffff), "t,d", 0},
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{"cfc3", op_rs_b11 (19, 2, 0), op_rs_b11(0x3f, 0x1f, 0x1ffff), "t,d", 0},
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{"mtc3", op_rs_b11 (19, 4, 0), op_rs_b11(0x3f, 0x1f, 0x1ffff), "t,d", 0},
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{"ctc3", op_rs_b11 (19, 6, 0), op_rs_b11(0x3f, 0x1f, 0x1ffff), "t,d", 0},
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{"bc3f", op_o16(19, 0x100), op_o16(0x3f, 0x3ff), "b", 1},
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{"bc3f", op_o16(19, 0x180), op_o16(0x3f, 0x3ff), "b", 1},
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{"bc3t", op_o16(19, 0x101), op_o16(0x3f, 0x3ff), "b", 1},
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{"bc3t", op_o16(19, 0x181), op_o16(0x3f, 0x3ff), "b", 1},
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|
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{"lb", one(32), one(0x3f), "t,j(s)", 0},
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|
{"lh", one(33), one(0x3f), "t,j(s)", 0},
|
|
{"lwl", one(34), one(0x3f), "t,j(s)", 0},
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|
{"lw", one(35), one(0x3f), "t,j(s)", 0},
|
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{"lbu", one(36), one(0x3f), "t,j(s)", 0},
|
|
{"lhu", one(37), one(0x3f), "t,j(s)", 0},
|
|
{"lwr", one(38), one(0x3f), "t,j(s)", 0},
|
|
{"sb", one(40), one(0x3f), "t,j(s)", 0},
|
|
{"sh", one(41), one(0x3f), "t,j(s)", 0},
|
|
{"swl", one(42), one(0x3f), "t,j(s)", 0},
|
|
{"swr", one(46), one(0x3f), "t,j(s)", 0},
|
|
{"sw", one(43), one(0x3f), "t,j(s)", 0},
|
|
{"lwc0", one(48), one(0x3f), "t,j(s)", 0},
|
|
/* for fpu */
|
|
{"lwc1", one(49), one(0x3f), "T,j(s)", 0},
|
|
{"lwc2", one(50), one(0x3f), "t,j(s)", 0},
|
|
{"lwc3", one(51), one(0x3f), "t,j(s)", 0},
|
|
{"swc0", one(56), one(0x3f), "t,j(s)", 0},
|
|
/* for fpu */
|
|
{"swc1", one(57), one(0x3f), "T,j(s)", 0},
|
|
{"swc2", one(58), one(0x3f), "t,j(s)", 0},
|
|
{"swc3", one(59), one(0x3f), "t,j(s)", 0},
|
|
};
|