968519095a
autoconf. * gencode.c (write_opcodes): Pad operands field to account for MSVC braindamage. * simops.c: Include errno.h. Exclude SYS_chown, since MSVC doesn't support it. (Why is this here in the first place?!?) * v850_sim.h: Get rid of 64 bit defs. Also, get rid of #elif's. Change number of operands in struct simops from 9 to 6. Define SIGTRAP and SIGQUIT for MSVC.
144 lines
3.1 KiB
C
144 lines
3.1 KiB
C
#include <stdio.h>
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#include <ctype.h>
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#include "ansidecl.h"
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#include "callback.h"
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#include "opcode/v850.h"
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#include <limits.h>
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#include "remote-sim.h"
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extern host_callback *v850_callback;
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#define DEBUG_TRACE 0x00000001
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#define DEBUG_VALUES 0x00000002
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extern int v850_debug;
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#if UCHAR_MAX == 255
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typedef unsigned char uint8;
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typedef signed char int8;
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#else
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#error "Char is not an 8-bit type"
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#endif
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#if SHRT_MAX == 32767
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typedef unsigned short uint16;
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typedef signed short int16;
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#else
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#error "Short is not a 16-bit type"
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#endif
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#if INT_MAX == 2147483647
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typedef unsigned int uint32;
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typedef signed int int32;
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#else
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# if LONG_MAX == 2147483647
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typedef unsigned long uint32;
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typedef signed long int32;
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# else
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# error "Neither int nor long is a 32-bit type"
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# endif
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#endif
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/* FIXME: V850 defines */
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typedef uint32 reg_t;
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struct simops
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{
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long opcode;
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long mask;
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void (*func)();
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int numops;
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int operands[6];
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};
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struct _state
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{
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reg_t regs[32]; /* general-purpose registers */
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reg_t sregs[32]; /* system regsiters, including psw */
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reg_t pc;
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uint8 *mem;
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int exception;
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} State;
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extern uint32 OP[4];
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extern struct simops Simops[];
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#define PC (State.pc)
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#define PSW_NP 0x80
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#define PSW_EP 0x40
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#define PSW_ID 0x20
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#define PSW_SAT 0x10
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#define PSW_CY 0x8
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#define PSW_OV 0x4
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#define PSW_S 0x2
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#define PSW_Z 0x1
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#define SEXT3(x) ((((x)&0x7)^(~0x3))+0x4)
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/* sign-extend a 4-bit number */
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#define SEXT4(x) ((((x)&0xf)^(~0x7))+0x8)
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/* sign-extend a 5-bit number */
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#define SEXT5(x) ((((x)&0x1f)^(~0xf))+0x10)
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/* sign-extend a 7-bit number */
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#define SEXT7(x) ((((x)&0x7f)^(~0x4f))+0x40)
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/* sign-extend an 8-bit number */
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#define SEXT8(x) ((((x)&0xff)^(~0x7f))+0x80)
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/* sign-extend a 9-bit number */
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#define SEXT9(x) ((((x)&0x1ff)^(~0xff))+0x100)
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/* sign-extend a 16-bit number */
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#define SEXT16(x) ((((x)&0xffff)^(~0x7fff))+0x8000)
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/* sign-extend a 22-bit number */
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#define SEXT22(x) ((((x)&0x3fffff)^(~0x1fffff))+0x200000)
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/* sign-extend a 32-bit number */
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#define SEXT32(x) ((((x)&0xffffffffLL)^(~0x7fffffffLL))+0x80000000LL)
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/* sign extend a 40 bit number */
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#define SEXT40(x) ((((x)&0xffffffffffLL)^(~0x7fffffffffLL))+0x8000000000LL)
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/* sign extend a 44 bit number */
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#define SEXT44(x) ((((x)&0xfffffffffffLL)^(~0x7ffffffffffLL))+0x80000000000LL)
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/* sign extend a 60 bit number */
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#define SEXT60(x) ((((x)&0xfffffffffffffffLL)^(~0x7ffffffffffffffLL))+0x800000000000000LL)
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#define MAX32 0x7fffffffLL
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#define MIN32 0xff80000000LL
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#define MASK32 0xffffffffLL
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#define MASK40 0xffffffffffLL
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#define INC_ADDR(x,i) x = ((State.MD && x == MOD_E) ? MOD_S : (x)+(i))
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/*#define RB(x) (*((uint8 *)((x)+State.mem)))*/
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/*#define SB(addr,data) ( RB(addr) = (data & 0xff))*/
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uint32 get_word PARAMS ((uint8 *));
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uint16 get_half PARAMS ((uint8 *));
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uint8 get_byte PARAMS ((uint8 *));
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void put_word PARAMS ((uint8 *, uint32));
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void put_half PARAMS ((uint8 *, uint16));
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void put_byte PARAMS ((uint8 *, uint8));
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uint32 load_mem PARAMS ((SIM_ADDR addr, int len));
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void store_mem PARAMS ((SIM_ADDR addr, int len, uint32 data));
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uint8 *map PARAMS ((SIM_ADDR addr));
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#define RLW(x) load_mem (x, 4)
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#ifdef _WIN32
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#define SIGTRAP 5
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#define SIGQUIT 3
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#endif
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