b015e599c7
* doc/binutils.texi: Document -Mvirt disassembler option. gas/ChangeLog: * config/tc-mips.c (struct mips_set_options): New ase_virt field. (mips_opts): Update for the new field. (file_ase_virt): New variable. (ISA_SUPPORTS_VIRT_ASE): New macro. (ISA_SUPPORTS_VIRT64_ASE): New macro. (MIPS_CPU_ASE_VIRT): New define. (is_opcode_valid): Handle ase_virt. (macro_build): Handle "+J". (validate_mips_insn): Likewise. (mips_ip): Likewise. (enum options): Add OPTION_VIRT and OPTION_NO_VIRT. (md_longopts): Add mvirt and mnovirt (md_parse_option): Handle OPTION_VIRT and OPTION_NO_VIRT. (mips_after_parse_args): Handle ase_virt field. (s_mipsset): Handle "virt" and "novirt". (mips_elf_final_processing): Add a comment about virt ASE might need a new flag. (md_show_usage): Print out the usage of -mvirt and mno-virt options. * doc/c-mips.texi: Document -mvirt and -mno-virt. Document ".set virt" and ".set novirt". gas/testsuite/ChangeLog: * gas/mips/mips.exp: Run virt and virt64 testcases. * gas/mips/virt.d: New file. * gas/mips/virt.s: New file. * gas/mips/virt64.d: New file. * gas/mips/virt64.s: New file. include/opcode/ChangeLog: * mips.h (OP_MASK_CODE10): Correct definition. (OP_SH_CODE10): Likewise. Add a comment that "+J" is used now for OP_*CODE10. (INSN_ASE_MASK): Update. (INSN_VIRT): New macro. (INSN_VIRT64): New macro opcodes/ChangeLog: * mips-dis.c (mips_arch_choices): Add INSN_VIRT to mips32r2 . Add INSN_VIRT and INSN_VIRT64 to mips64r2. (parse_mips_dis_option): Handle the virt option. (print_insn_args): Handle "+J". (print_mips_disassembler_options): Print out message about virt64. * mips-opc.c (IVIRT): New define. (IVIRT64): New define. (mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0, tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp VIRT instructions. Move rfe to the bottom as it conflicts with tlbgp.
750 lines
26 KiB
Plaintext
750 lines
26 KiB
Plaintext
@c Copyright 1991, 1992, 1993, 1994, 1995, 1997, 1999, 2000, 2001,
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@c 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2013
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@c Free Software Foundation, Inc.
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@c This is part of the GAS manual.
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@c For copying conditions, see the file as.texinfo.
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@ifset GENERIC
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@page
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@node MIPS-Dependent
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@chapter MIPS Dependent Features
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@end ifset
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@ifclear GENERIC
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@node Machine Dependencies
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@chapter MIPS Dependent Features
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@end ifclear
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@cindex MIPS processor
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@sc{gnu} @code{@value{AS}} for @sc{mips} architectures supports several
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different @sc{mips} processors, and MIPS ISA levels I through V, MIPS32,
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and MIPS64. For information about the @sc{mips} instruction set, see
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@cite{MIPS RISC Architecture}, by Kane and Heindrich (Prentice-Hall).
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For an overview of @sc{mips} assembly conventions, see ``Appendix D:
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Assembly Language Programming'' in the same work.
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@menu
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* MIPS Opts:: Assembler options
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* MIPS Object:: ECOFF object code
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* MIPS Stabs:: Directives for debugging information
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* MIPS ISA:: Directives to override the ISA level
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* MIPS symbol sizes:: Directives to override the size of symbols
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* MIPS autoextend:: Directives for extending MIPS 16 bit instructions
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* MIPS insn:: Directive to mark data as an instruction
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* MIPS option stack:: Directives to save and restore options
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* MIPS ASE instruction generation overrides:: Directives to control
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generation of MIPS ASE instructions
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* MIPS floating-point:: Directives to override floating-point options
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* MIPS Syntax:: MIPS specific syntactical considerations
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@end menu
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@node MIPS Opts
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@section Assembler options
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The @sc{mips} configurations of @sc{gnu} @code{@value{AS}} support these
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special options:
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@table @code
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@cindex @code{-G} option (MIPS)
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@item -G @var{num}
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This option sets the largest size of an object that can be referenced
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implicitly with the @code{gp} register. It is only accepted for targets
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that use @sc{ecoff} format. The default value is 8.
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@cindex @code{-EB} option (MIPS)
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@cindex @code{-EL} option (MIPS)
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@cindex MIPS big-endian output
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@cindex MIPS little-endian output
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@cindex big-endian output, MIPS
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@cindex little-endian output, MIPS
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@item -EB
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@itemx -EL
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Any @sc{mips} configuration of @code{@value{AS}} can select big-endian or
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little-endian output at run time (unlike the other @sc{gnu} development
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tools, which must be configured for one or the other). Use @samp{-EB}
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to select big-endian output, and @samp{-EL} for little-endian.
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@item -KPIC
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@cindex PIC selection, MIPS
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@cindex @option{-KPIC} option, MIPS
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Generate SVR4-style PIC. This option tells the assembler to generate
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SVR4-style position-independent macro expansions. It also tells the
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assembler to mark the output file as PIC.
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@item -mvxworks-pic
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@cindex @option{-mvxworks-pic} option, MIPS
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Generate VxWorks PIC. This option tells the assembler to generate
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VxWorks-style position-independent macro expansions.
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@cindex MIPS architecture options
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@item -mips1
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@itemx -mips2
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@itemx -mips3
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@itemx -mips4
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@itemx -mips5
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@itemx -mips32
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@itemx -mips32r2
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@itemx -mips64
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@itemx -mips64r2
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Generate code for a particular MIPS Instruction Set Architecture level.
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@samp{-mips1} corresponds to the @sc{r2000} and @sc{r3000} processors,
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@samp{-mips2} to the @sc{r6000} processor, @samp{-mips3} to the
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@sc{r4000} processor, and @samp{-mips4} to the @sc{r8000} and
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@sc{r10000} processors. @samp{-mips5}, @samp{-mips32}, @samp{-mips32r2},
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@samp{-mips64}, and @samp{-mips64r2}
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correspond to generic
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@sc{MIPS V}, @sc{MIPS32}, @sc{MIPS32 Release 2}, @sc{MIPS64},
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and @sc{MIPS64 Release 2}
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ISA processors, respectively. You can also switch
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instruction sets during the assembly; see @ref{MIPS ISA, Directives to
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override the ISA level}.
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@item -mgp32
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@itemx -mfp32
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Some macros have different expansions for 32-bit and 64-bit registers.
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The register sizes are normally inferred from the ISA and ABI, but these
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flags force a certain group of registers to be treated as 32 bits wide at
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all times. @samp{-mgp32} controls the size of general-purpose registers
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and @samp{-mfp32} controls the size of floating-point registers.
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The @code{.set gp=32} and @code{.set fp=32} directives allow the size
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of registers to be changed for parts of an object. The default value is
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restored by @code{.set gp=default} and @code{.set fp=default}.
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On some MIPS variants there is a 32-bit mode flag; when this flag is
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set, 64-bit instructions generate a trap. Also, some 32-bit OSes only
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save the 32-bit registers on a context switch, so it is essential never
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to use the 64-bit registers.
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@item -mgp64
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@itemx -mfp64
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Assume that 64-bit registers are available. This is provided in the
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interests of symmetry with @samp{-mgp32} and @samp{-mfp32}.
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The @code{.set gp=64} and @code{.set fp=64} directives allow the size
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of registers to be changed for parts of an object. The default value is
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restored by @code{.set gp=default} and @code{.set fp=default}.
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@item -mips16
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@itemx -no-mips16
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Generate code for the MIPS 16 processor. This is equivalent to putting
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@code{.set mips16} at the start of the assembly file. @samp{-no-mips16}
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turns off this option.
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@item -mmicromips
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@itemx -mno-micromips
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Generate code for the microMIPS processor. This is equivalent to putting
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@code{.set micromips} at the start of the assembly file. @samp{-mno-micromips}
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turns off this option. This is equivalent to putting @code{.set nomicromips}
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at the start of the assembly file.
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@item -msmartmips
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@itemx -mno-smartmips
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Enables the SmartMIPS extensions to the MIPS32 instruction set, which
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provides a number of new instructions which target smartcard and
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cryptographic applications. This is equivalent to putting
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@code{.set smartmips} at the start of the assembly file.
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@samp{-mno-smartmips} turns off this option.
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@item -mips3d
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@itemx -no-mips3d
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Generate code for the MIPS-3D Application Specific Extension.
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This tells the assembler to accept MIPS-3D instructions.
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@samp{-no-mips3d} turns off this option.
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@item -mdmx
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@itemx -no-mdmx
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Generate code for the MDMX Application Specific Extension.
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This tells the assembler to accept MDMX instructions.
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@samp{-no-mdmx} turns off this option.
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@item -mdsp
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@itemx -mno-dsp
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Generate code for the DSP Release 1 Application Specific Extension.
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This tells the assembler to accept DSP Release 1 instructions.
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@samp{-mno-dsp} turns off this option.
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@item -mdspr2
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@itemx -mno-dspr2
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Generate code for the DSP Release 2 Application Specific Extension.
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This option implies -mdsp.
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This tells the assembler to accept DSP Release 2 instructions.
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@samp{-mno-dspr2} turns off this option.
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@item -mmt
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@itemx -mno-mt
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Generate code for the MT Application Specific Extension.
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This tells the assembler to accept MT instructions.
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@samp{-mno-mt} turns off this option.
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@item -mmcu
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@itemx -mno-mcu
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Generate code for the MCU Application Specific Extension.
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This tells the assembler to accept MCU instructions.
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@samp{-mno-mcu} turns off this option.
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@item -mvirt
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@itemx -mno-virt
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Generate code for the Virtualization Application Specific Extension.
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This tells the assembler to accept Virtualization instructions.
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@samp{-mno-virt} turns off this option.
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@item -mfix7000
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@itemx -mno-fix7000
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Cause nops to be inserted if the read of the destination register
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of an mfhi or mflo instruction occurs in the following two instructions.
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@item -mfix-loongson2f-jump
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@itemx -mno-fix-loongson2f-jump
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Eliminate instruction fetch from outside 256M region to work around the
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Loongson2F @samp{jump} instructions. Without it, under extreme cases,
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the kernel may crash. The issue has been solved in latest processor
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batches, but this fix has no side effect to them.
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@item -mfix-loongson2f-nop
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@itemx -mno-fix-loongson2f-nop
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Replace nops by @code{or at,at,zero} to work around the Loongson2F
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@samp{nop} errata. Without it, under extreme cases, cpu might
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deadlock. The issue has been solved in latest loongson2f batches, but
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this fix has no side effect to them.
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@item -mfix-vr4120
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@itemx -mno-fix-vr4120
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Insert nops to work around certain VR4120 errata. This option is
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intended to be used on GCC-generated code: it is not designed to catch
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all problems in hand-written assembler code.
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@item -mfix-vr4130
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@itemx -mno-fix-vr4130
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Insert nops to work around the VR4130 @samp{mflo}/@samp{mfhi} errata.
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@item -mfix-24k
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@itemx -mno-fix-24k
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Insert nops to work around the 24K @samp{eret}/@samp{deret} errata.
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@item -mfix-cn63xxp1
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@itemx -mno-fix-cn63xxp1
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Replace @code{pref} hints 0 - 4 and 6 - 24 with hint 28 to work around
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certain CN63XXP1 errata.
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@item -m4010
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@itemx -no-m4010
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Generate code for the LSI @sc{r4010} chip. This tells the assembler to
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accept the @sc{r4010} specific instructions (@samp{addciu}, @samp{ffc},
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etc.), and to not schedule @samp{nop} instructions around accesses to
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the @samp{HI} and @samp{LO} registers. @samp{-no-m4010} turns off this
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option.
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@item -m4650
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@itemx -no-m4650
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Generate code for the MIPS @sc{r4650} chip. This tells the assembler to accept
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the @samp{mad} and @samp{madu} instruction, and to not schedule @samp{nop}
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instructions around accesses to the @samp{HI} and @samp{LO} registers.
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@samp{-no-m4650} turns off this option.
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@item -m3900
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@itemx -no-m3900
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@itemx -m4100
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@itemx -no-m4100
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For each option @samp{-m@var{nnnn}}, generate code for the MIPS
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@sc{r@var{nnnn}} chip. This tells the assembler to accept instructions
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specific to that chip, and to schedule for that chip's hazards.
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@item -march=@var{cpu}
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Generate code for a particular MIPS cpu. It is exactly equivalent to
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@samp{-m@var{cpu}}, except that there are more value of @var{cpu}
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understood. Valid @var{cpu} value are:
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@quotation
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2000,
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3000,
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3900,
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4000,
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4010,
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4100,
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4111,
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vr4120,
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vr4130,
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vr4181,
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4300,
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4400,
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4600,
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4650,
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5000,
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rm5200,
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rm5230,
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rm5231,
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rm5261,
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rm5721,
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vr5400,
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vr5500,
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6000,
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rm7000,
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8000,
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rm9000,
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10000,
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12000,
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14000,
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16000,
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4kc,
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4km,
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4kp,
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4ksc,
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4kec,
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4kem,
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4kep,
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4ksd,
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m4k,
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m4kp,
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m14k,
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m14kc,
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m14ke,
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m14kec,
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24kc,
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24kf2_1,
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24kf,
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24kf1_1,
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24kec,
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24kef2_1,
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24kef,
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24kef1_1,
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34kc,
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34kf2_1,
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34kf,
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34kf1_1,
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34kn,
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74kc,
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74kf2_1,
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74kf,
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74kf1_1,
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74kf3_2,
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1004kc,
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1004kf2_1,
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1004kf,
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1004kf1_1,
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5kc,
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5kf,
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20kc,
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25kf,
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sb1,
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sb1a,
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loongson2e,
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loongson2f,
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loongson3a,
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octeon,
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octeon+,
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octeon2,
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xlr,
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xlp
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@end quotation
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For compatibility reasons, @samp{@var{n}x} and @samp{@var{b}fx} are
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accepted as synonyms for @samp{@var{n}f1_1}. These values are
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deprecated.
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@item -mtune=@var{cpu}
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Schedule and tune for a particular MIPS cpu. Valid @var{cpu} values are
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identical to @samp{-march=@var{cpu}}.
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@item -mabi=@var{abi}
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Record which ABI the source code uses. The recognized arguments
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are: @samp{32}, @samp{n32}, @samp{o64}, @samp{64} and @samp{eabi}.
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@item -msym32
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@itemx -mno-sym32
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@cindex -msym32
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@cindex -mno-sym32
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Equivalent to adding @code{.set sym32} or @code{.set nosym32} to
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the beginning of the assembler input. @xref{MIPS symbol sizes}.
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@cindex @code{-nocpp} ignored (MIPS)
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@item -nocpp
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This option is ignored. It is accepted for command-line compatibility with
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other assemblers, which use it to turn off C style preprocessing. With
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@sc{gnu} @code{@value{AS}}, there is no need for @samp{-nocpp}, because the
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@sc{gnu} assembler itself never runs the C preprocessor.
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@item -msoft-float
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@itemx -mhard-float
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Disable or enable floating-point instructions. Note that by default
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floating-point instructions are always allowed even with CPU targets
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that don't have support for these instructions.
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@item -msingle-float
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@itemx -mdouble-float
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Disable or enable double-precision floating-point operations. Note
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that by default double-precision floating-point operations are always
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allowed even with CPU targets that don't have support for these
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operations.
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@item --construct-floats
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@itemx --no-construct-floats
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The @code{--no-construct-floats} option disables the construction of
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double width floating point constants by loading the two halves of the
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value into the two single width floating point registers that make up
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the double width register. This feature is useful if the processor
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support the FR bit in its status register, and this bit is known (by
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the programmer) to be set. This bit prevents the aliasing of the double
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width register by the single width registers.
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By default @code{--construct-floats} is selected, allowing construction
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of these floating point constants.
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@item --trap
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@itemx --no-break
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@c FIXME! (1) reflect these options (next item too) in option summaries;
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@c (2) stop teasing, say _which_ instructions expanded _how_.
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@code{@value{AS}} automatically macro expands certain division and
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|
multiplication instructions to check for overflow and division by zero. This
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option causes @code{@value{AS}} to generate code to take a trap exception
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|
rather than a break exception when an error is detected. The trap instructions
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are only supported at Instruction Set Architecture level 2 and higher.
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|
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@item --break
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@itemx --no-trap
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|
Generate code to take a break exception rather than a trap exception when an
|
|
error is detected. This is the default.
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@item -mpdr
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@itemx -mno-pdr
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Control generation of @code{.pdr} sections. Off by default on IRIX, on
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elsewhere.
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@item -mshared
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@itemx -mno-shared
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When generating code using the Unix calling conventions (selected by
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@samp{-KPIC} or @samp{-mcall_shared}), gas will normally generate code
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|
which can go into a shared library. The @samp{-mno-shared} option
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|
tells gas to generate code which uses the calling convention, but can
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|
not go into a shared library. The resulting code is slightly more
|
|
efficient. This option only affects the handling of the
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@samp{.cpload} and @samp{.cpsetup} pseudo-ops.
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@end table
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@node MIPS Object
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@section MIPS ECOFF object code
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@cindex ECOFF sections
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@cindex MIPS ECOFF sections
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|
Assembling for a @sc{mips} @sc{ecoff} target supports some additional sections
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|
besides the usual @code{.text}, @code{.data} and @code{.bss}. The
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|
additional sections are @code{.rdata}, used for read-only data,
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|
@code{.sdata}, used for small data, and @code{.sbss}, used for small
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|
common objects.
|
|
|
|
@cindex small objects, MIPS ECOFF
|
|
@cindex @code{gp} register, MIPS
|
|
When assembling for @sc{ecoff}, the assembler uses the @code{$gp} (@code{$28})
|
|
register to form the address of a ``small object''. Any object in the
|
|
@code{.sdata} or @code{.sbss} sections is considered ``small'' in this sense.
|
|
For external objects, or for objects in the @code{.bss} section, you can use
|
|
the @code{@value{GCC}} @samp{-G} option to control the size of objects addressed via
|
|
@code{$gp}; the default value is 8, meaning that a reference to any object
|
|
eight bytes or smaller uses @code{$gp}. Passing @samp{-G 0} to
|
|
@code{@value{AS}} prevents it from using the @code{$gp} register on the basis
|
|
of object size (but the assembler uses @code{$gp} for objects in @code{.sdata}
|
|
or @code{sbss} in any case). The size of an object in the @code{.bss} section
|
|
is set by the @code{.comm} or @code{.lcomm} directive that defines it. The
|
|
size of an external object may be set with the @code{.extern} directive. For
|
|
example, @samp{.extern sym,4} declares that the object at @code{sym} is 4 bytes
|
|
in length, whie leaving @code{sym} otherwise undefined.
|
|
|
|
Using small @sc{ecoff} objects requires linker support, and assumes that the
|
|
@code{$gp} register is correctly initialized (normally done automatically by
|
|
the startup code). @sc{mips} @sc{ecoff} assembly code must not modify the
|
|
@code{$gp} register.
|
|
|
|
@node MIPS Stabs
|
|
@section Directives for debugging information
|
|
|
|
@cindex MIPS debugging directives
|
|
@sc{mips} @sc{ecoff} @code{@value{AS}} supports several directives used for
|
|
generating debugging information which are not support by traditional @sc{mips}
|
|
assemblers. These are @code{.def}, @code{.endef}, @code{.dim}, @code{.file},
|
|
@code{.scl}, @code{.size}, @code{.tag}, @code{.type}, @code{.val},
|
|
@code{.stabd}, @code{.stabn}, and @code{.stabs}. The debugging information
|
|
generated by the three @code{.stab} directives can only be read by @sc{gdb},
|
|
not by traditional @sc{mips} debuggers (this enhancement is required to fully
|
|
support C++ debugging). These directives are primarily used by compilers, not
|
|
assembly language programmers!
|
|
|
|
@node MIPS symbol sizes
|
|
@section Directives to override the size of symbols
|
|
|
|
@cindex @code{.set sym32}
|
|
@cindex @code{.set nosym32}
|
|
The n64 ABI allows symbols to have any 64-bit value. Although this
|
|
provides a great deal of flexibility, it means that some macros have
|
|
much longer expansions than their 32-bit counterparts. For example,
|
|
the non-PIC expansion of @samp{dla $4,sym} is usually:
|
|
|
|
@smallexample
|
|
lui $4,%highest(sym)
|
|
lui $1,%hi(sym)
|
|
daddiu $4,$4,%higher(sym)
|
|
daddiu $1,$1,%lo(sym)
|
|
dsll32 $4,$4,0
|
|
daddu $4,$4,$1
|
|
@end smallexample
|
|
|
|
whereas the 32-bit expansion is simply:
|
|
|
|
@smallexample
|
|
lui $4,%hi(sym)
|
|
daddiu $4,$4,%lo(sym)
|
|
@end smallexample
|
|
|
|
n64 code is sometimes constructed in such a way that all symbolic
|
|
constants are known to have 32-bit values, and in such cases, it's
|
|
preferable to use the 32-bit expansion instead of the 64-bit
|
|
expansion.
|
|
|
|
You can use the @code{.set sym32} directive to tell the assembler
|
|
that, from this point on, all expressions of the form
|
|
@samp{@var{symbol}} or @samp{@var{symbol} + @var{offset}}
|
|
have 32-bit values. For example:
|
|
|
|
@smallexample
|
|
.set sym32
|
|
dla $4,sym
|
|
lw $4,sym+16
|
|
sw $4,sym+0x8000($4)
|
|
@end smallexample
|
|
|
|
will cause the assembler to treat @samp{sym}, @code{sym+16} and
|
|
@code{sym+0x8000} as 32-bit values. The handling of non-symbolic
|
|
addresses is not affected.
|
|
|
|
The directive @code{.set nosym32} ends a @code{.set sym32} block and
|
|
reverts to the normal behavior. It is also possible to change the
|
|
symbol size using the command-line options @option{-msym32} and
|
|
@option{-mno-sym32}.
|
|
|
|
These options and directives are always accepted, but at present,
|
|
they have no effect for anything other than n64.
|
|
|
|
@node MIPS ISA
|
|
@section Directives to override the ISA level
|
|
|
|
@cindex MIPS ISA override
|
|
@kindex @code{.set mips@var{n}}
|
|
@sc{gnu} @code{@value{AS}} supports an additional directive to change
|
|
the @sc{mips} Instruction Set Architecture level on the fly: @code{.set
|
|
mips@var{n}}. @var{n} should be a number from 0 to 5, or 32, 32r2, 64
|
|
or 64r2.
|
|
The values other than 0 make the assembler accept instructions
|
|
for the corresponding @sc{isa} level, from that point on in the
|
|
assembly. @code{.set mips@var{n}} affects not only which instructions
|
|
are permitted, but also how certain macros are expanded. @code{.set
|
|
mips0} restores the @sc{isa} level to its original level: either the
|
|
level you selected with command line options, or the default for your
|
|
configuration. You can use this feature to permit specific @sc{mips3}
|
|
instructions while assembling in 32 bit mode. Use this directive with
|
|
care!
|
|
|
|
@cindex MIPS CPU override
|
|
@kindex @code{.set arch=@var{cpu}}
|
|
The @code{.set arch=@var{cpu}} directive provides even finer control.
|
|
It changes the effective CPU target and allows the assembler to use
|
|
instructions specific to a particular CPU. All CPUs supported by the
|
|
@samp{-march} command line option are also selectable by this directive.
|
|
The original value is restored by @code{.set arch=default}.
|
|
|
|
The directive @code{.set mips16} puts the assembler into MIPS 16 mode,
|
|
in which it will assemble instructions for the MIPS 16 processor. Use
|
|
@code{.set nomips16} to return to normal 32 bit mode.
|
|
|
|
Traditional @sc{mips} assemblers do not support this directive.
|
|
|
|
The directive @code{.set micromips} puts the assembler into microMIPS mode,
|
|
in which it will assemble instructions for the microMIPS processor. Use
|
|
@code{.set nomicromips} to return to normal 32 bit mode.
|
|
|
|
Traditional @sc{mips} assemblers do not support this directive.
|
|
|
|
@node MIPS autoextend
|
|
@section Directives for extending MIPS 16 bit instructions
|
|
|
|
@kindex @code{.set autoextend}
|
|
@kindex @code{.set noautoextend}
|
|
By default, MIPS 16 instructions are automatically extended to 32 bits
|
|
when necessary. The directive @code{.set noautoextend} will turn this
|
|
off. When @code{.set noautoextend} is in effect, any 32 bit instruction
|
|
must be explicitly extended with the @code{.e} modifier (e.g.,
|
|
@code{li.e $4,1000}). The directive @code{.set autoextend} may be used
|
|
to once again automatically extend instructions when necessary.
|
|
|
|
This directive is only meaningful when in MIPS 16 mode. Traditional
|
|
@sc{mips} assemblers do not support this directive.
|
|
|
|
@node MIPS insn
|
|
@section Directive to mark data as an instruction
|
|
|
|
@kindex @code{.insn}
|
|
The @code{.insn} directive tells @code{@value{AS}} that the following
|
|
data is actually instructions. This makes a difference in MIPS 16 and
|
|
microMIPS modes: when loading the address of a label which precedes
|
|
instructions, @code{@value{AS}} automatically adds 1 to the value, so
|
|
that jumping to the loaded address will do the right thing.
|
|
|
|
@kindex @code{.global}
|
|
The @code{.global} and @code{.globl} directives supported by
|
|
@code{@value{AS}} will by default mark the symbol as pointing to a
|
|
region of data not code. This means that, for example, any
|
|
instructions following such a symbol will not be disassembled by
|
|
@code{objdump} as it will regard them as data. To change this
|
|
behaviour an optional section name can be placed after the symbol name
|
|
in the @code{.global} directive. If this section exists and is known
|
|
to be a code section, then the symbol will be marked as poiting at
|
|
code not data. Ie the syntax for the directive is:
|
|
|
|
@code{.global @var{symbol}[ @var{section}][, @var{symbol}[ @var{section}]] ...},
|
|
|
|
Here is a short example:
|
|
|
|
@example
|
|
.global foo .text, bar, baz .data
|
|
foo:
|
|
nop
|
|
bar:
|
|
.word 0x0
|
|
baz:
|
|
.word 0x1
|
|
|
|
@end example
|
|
|
|
@node MIPS option stack
|
|
@section Directives to save and restore options
|
|
|
|
@cindex MIPS option stack
|
|
@kindex @code{.set push}
|
|
@kindex @code{.set pop}
|
|
The directives @code{.set push} and @code{.set pop} may be used to save
|
|
and restore the current settings for all the options which are
|
|
controlled by @code{.set}. The @code{.set push} directive saves the
|
|
current settings on a stack. The @code{.set pop} directive pops the
|
|
stack and restores the settings.
|
|
|
|
These directives can be useful inside an macro which must change an
|
|
option such as the ISA level or instruction reordering but does not want
|
|
to change the state of the code which invoked the macro.
|
|
|
|
Traditional @sc{mips} assemblers do not support these directives.
|
|
|
|
@node MIPS ASE instruction generation overrides
|
|
@section Directives to control generation of MIPS ASE instructions
|
|
|
|
@cindex MIPS MIPS-3D instruction generation override
|
|
@kindex @code{.set mips3d}
|
|
@kindex @code{.set nomips3d}
|
|
The directive @code{.set mips3d} makes the assembler accept instructions
|
|
from the MIPS-3D Application Specific Extension from that point on
|
|
in the assembly. The @code{.set nomips3d} directive prevents MIPS-3D
|
|
instructions from being accepted.
|
|
|
|
@cindex SmartMIPS instruction generation override
|
|
@kindex @code{.set smartmips}
|
|
@kindex @code{.set nosmartmips}
|
|
The directive @code{.set smartmips} makes the assembler accept
|
|
instructions from the SmartMIPS Application Specific Extension to the
|
|
MIPS32 @sc{isa} from that point on in the assembly. The
|
|
@code{.set nosmartmips} directive prevents SmartMIPS instructions from
|
|
being accepted.
|
|
|
|
@cindex MIPS MDMX instruction generation override
|
|
@kindex @code{.set mdmx}
|
|
@kindex @code{.set nomdmx}
|
|
The directive @code{.set mdmx} makes the assembler accept instructions
|
|
from the MDMX Application Specific Extension from that point on
|
|
in the assembly. The @code{.set nomdmx} directive prevents MDMX
|
|
instructions from being accepted.
|
|
|
|
@cindex MIPS DSP Release 1 instruction generation override
|
|
@kindex @code{.set dsp}
|
|
@kindex @code{.set nodsp}
|
|
The directive @code{.set dsp} makes the assembler accept instructions
|
|
from the DSP Release 1 Application Specific Extension from that point
|
|
on in the assembly. The @code{.set nodsp} directive prevents DSP
|
|
Release 1 instructions from being accepted.
|
|
|
|
@cindex MIPS DSP Release 2 instruction generation override
|
|
@kindex @code{.set dspr2}
|
|
@kindex @code{.set nodspr2}
|
|
The directive @code{.set dspr2} makes the assembler accept instructions
|
|
from the DSP Release 2 Application Specific Extension from that point
|
|
on in the assembly. This dirctive implies @code{.set dsp}. The
|
|
@code{.set nodspr2} directive prevents DSP Release 2 instructions from
|
|
being accepted.
|
|
|
|
@cindex MIPS MT instruction generation override
|
|
@kindex @code{.set mt}
|
|
@kindex @code{.set nomt}
|
|
The directive @code{.set mt} makes the assembler accept instructions
|
|
from the MT Application Specific Extension from that point on
|
|
in the assembly. The @code{.set nomt} directive prevents MT
|
|
instructions from being accepted.
|
|
|
|
@cindex MIPS MCU instruction generation override
|
|
@kindex @code{.set mcu}
|
|
@kindex @code{.set nomcu}
|
|
The directive @code{.set mcu} makes the assembler accept instructions
|
|
from the MCU Application Specific Extension from that point on
|
|
in the assembly. The @code{.set nomcu} directive prevents MCU
|
|
instructions from being accepted.
|
|
|
|
@cindex Virtualization instruction generation override
|
|
@kindex @code{.set virt}
|
|
@kindex @code{.set novirt}
|
|
The directive @code{.set virt} makes the assembler accept instructions
|
|
from the Virtualization Application Specific Extension from that point
|
|
on in the assembly. The @code{.set novirt} directive prevents Virtualization
|
|
instructions from being accepted.
|
|
|
|
Traditional @sc{mips} assemblers do not support these directives.
|
|
|
|
@node MIPS floating-point
|
|
@section Directives to override floating-point options
|
|
|
|
@cindex Disable floating-point instructions
|
|
@kindex @code{.set softfloat}
|
|
@kindex @code{.set hardfloat}
|
|
The directives @code{.set softfloat} and @code{.set hardfloat} provide
|
|
finer control of disabling and enabling float-point instructions.
|
|
These directives always override the default (that hard-float
|
|
instructions are accepted) or the command-line options
|
|
(@samp{-msoft-float} and @samp{-mhard-float}).
|
|
|
|
@cindex Disable single-precision floating-point operations
|
|
@kindex @code{.set singlefloat}
|
|
@kindex @code{.set doublefloat}
|
|
The directives @code{.set singlefloat} and @code{.set doublefloat}
|
|
provide finer control of disabling and enabling double-precision
|
|
float-point operations. These directives always override the default
|
|
(that double-precision operations are accepted) or the command-line
|
|
options (@samp{-msingle-float} and @samp{-mdouble-float}).
|
|
|
|
Traditional @sc{mips} assemblers do not support these directives.
|
|
|
|
@node MIPS Syntax
|
|
@section Syntactical considerations for the MIPS assembler
|
|
@menu
|
|
* MIPS-Chars:: Special Characters
|
|
@end menu
|
|
|
|
@node MIPS-Chars
|
|
@subsection Special Characters
|
|
|
|
@cindex line comment character, MIPS
|
|
@cindex MIPS line comment character
|
|
The presence of a @samp{#} on a line indicates the start of a comment
|
|
that extends to the end of the current line.
|
|
|
|
If a @samp{#} appears as the first character of a line, the whole line
|
|
is treated as a comment, but in this case the line can also be a
|
|
logical line number directive (@pxref{Comments}) or a
|
|
preprocessor control command (@pxref{Preprocessing}).
|
|
|
|
@cindex line separator, MIPS
|
|
@cindex statement separator, MIPS
|
|
@cindex MIPS line separator
|
|
The @samp{;} character can be used to separate statements on the same
|
|
line.
|