303 lines
9.7 KiB
C
303 lines
9.7 KiB
C
/* CPU family header for sh64.
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THIS FILE IS MACHINE GENERATED WITH CGEN.
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Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
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This file is part of the GNU Simulators.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2, or (at your option)
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any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License along
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with this program; if not, write to the Free Software Foundation, Inc.,
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59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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#ifndef CPU_SH64_H
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#define CPU_SH64_H
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/* Maximum number of instructions that are fetched at a time.
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This is for LIW type instructions sets (e.g. m32r). */
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#define MAX_LIW_INSNS 1
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/* Maximum number of instructions that can be executed in parallel. */
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#define MAX_PARALLEL_INSNS 1
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/* CPU state information. */
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typedef struct {
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/* Hardware elements. */
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struct {
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/* Program counter */
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UDI h_pc;
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#define GET_H_PC() CPU (h_pc)
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#define SET_H_PC(x) \
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do { \
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{\
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CPU (h_ism) = ANDDI ((x), 1);\
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CPU (h_pc) = ANDDI ((x), INVDI (1));\
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}\
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;} while (0)
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/* General purpose integer registers */
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DI h_gr[64];
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#define GET_H_GR(index) ((((index) == (63))) ? (0) : (CPU (h_gr[index])))
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#define SET_H_GR(index, x) \
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do { \
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if ((((index)) != (63))) {\
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CPU (h_gr[(index)]) = (x);\
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} else {\
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((void) 0); /*nop*/\
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}\
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;} while (0)
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/* Control registers */
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DI h_cr[64];
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#define GET_H_CR(index) ((((index) == (0))) ? (ZEXTSIDI (CPU (h_sr))) : (CPU (h_cr[index])))
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#define SET_H_CR(index, x) \
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do { \
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if ((((index)) == (0))) {\
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CPU (h_sr) = (x);\
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} else {\
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CPU (h_cr[(index)]) = (x);\
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}\
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;} while (0)
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/* Status register */
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SI h_sr;
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#define GET_H_SR() CPU (h_sr)
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#define SET_H_SR(x) (CPU (h_sr) = (x))
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/* Floating point status and control register */
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SI h_fpscr;
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#define GET_H_FPSCR() CPU (h_fpscr)
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#define SET_H_FPSCR(x) (CPU (h_fpscr) = (x))
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/* Single precision floating point registers */
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SF h_fr[64];
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#define GET_H_FR(a1) CPU (h_fr)[a1]
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#define SET_H_FR(a1, x) (CPU (h_fr)[a1] = (x))
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/* Single precision floating point register pairs */
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DF h_fp[32];
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#define GET_H_FP(a1) CPU (h_fp)[a1]
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#define SET_H_FP(a1, x) (CPU (h_fp)[a1] = (x))
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/* Branch target registers */
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DI h_tr[8];
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#define GET_H_TR(a1) CPU (h_tr)[a1]
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#define SET_H_TR(a1, x) (CPU (h_tr)[a1] = (x))
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/* Current instruction set mode */
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BI h_ism;
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#define GET_H_ISM() CPU (h_ism)
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#define SET_H_ISM(x) \
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do { \
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cgen_rtx_error (current_cpu, "cannot set ism directly");\
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;} while (0)
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} hardware;
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#define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware)
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} SH64_CPU_DATA;
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/* Virtual regs. */
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#define GET_H_GRC(index) ANDDI (CPU (h_gr[index]), ZEXTSIDI (0xffffffff))
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#define SET_H_GRC(index, x) \
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do { \
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CPU (h_gr[(index)]) = EXTSIDI ((x));\
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;} while (0)
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#define GET_H_FRBIT() ANDSI (SRLSI (CPU (h_sr), 14), 1)
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#define SET_H_FRBIT(x) \
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do { \
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CPU (h_sr) = ORSI (ANDSI (CPU (h_sr), (~ (((1) << (14))))), SLLSI ((x), 14));\
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;} while (0)
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#define GET_H_SZBIT() ANDSI (SRLSI (CPU (h_sr), 13), 1)
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#define SET_H_SZBIT(x) \
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do { \
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CPU (h_sr) = ORSI (ANDSI (CPU (h_sr), (~ (((1) << (13))))), SLLSI ((x), 13));\
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;} while (0)
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#define GET_H_PRBIT() ANDSI (SRLSI (CPU (h_sr), 12), 1)
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#define SET_H_PRBIT(x) \
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do { \
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CPU (h_sr) = ORSI (ANDSI (CPU (h_sr), (~ (((1) << (12))))), SLLSI ((x), 12));\
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;} while (0)
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#define GET_H_SBIT() ANDSI (SRLSI (CPU (h_sr), 1), 1)
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#define SET_H_SBIT(x) \
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do { \
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CPU (h_sr) = ORSI (ANDSI (CPU (h_sr), (~ (2))), SLLSI ((x), 1));\
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;} while (0)
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#define GET_H_MBIT() ANDSI (SRLSI (CPU (h_sr), 9), 1)
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#define SET_H_MBIT(x) \
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do { \
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CPU (h_sr) = ORSI (ANDSI (CPU (h_sr), (~ (((1) << (9))))), SLLSI ((x), 9));\
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;} while (0)
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#define GET_H_QBIT() ANDSI (SRLSI (CPU (h_sr), 8), 1)
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#define SET_H_QBIT(x) \
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do { \
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CPU (h_sr) = ORSI (ANDSI (CPU (h_sr), (~ (((1) << (8))))), SLLSI ((x), 8));\
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;} while (0)
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#define GET_H_FV(index) CPU (h_fr[MULQI (ANDQI (index, 15), 4)])
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#define SET_H_FV(index, x) \
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do { \
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CPU (h_fr[MULQI (ANDQI ((index), 15), 4)]) = (x);\
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;} while (0)
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#define GET_H_FMTX(index) CPU (h_fr[MULQI (ANDQI (index, 3), 16)])
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#define SET_H_FMTX(index, x) \
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do { \
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CPU (h_fr[MULQI (ANDQI ((index), 3), 16)]) = (x);\
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;} while (0)
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#define GET_H_DR(index) SUBWORDDIDF (ORDI (SLLDI (ZEXTSIDI (SUBWORDSFSI (CPU (h_fr[index]))), 32), ZEXTSIDI (SUBWORDSFSI (CPU (h_fr[((index) + (1))])))))
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#define SET_H_DR(index, x) \
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do { \
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{\
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CPU (h_fr[(index)]) = SUBWORDSISF (SUBWORDDFSI ((x), 0));\
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CPU (h_fr[(((index)) + (1))]) = SUBWORDSISF (SUBWORDDFSI ((x), 1));\
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}\
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;} while (0)
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#define GET_H_ENDIAN() sh64_endian (current_cpu)
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#define SET_H_ENDIAN(x) \
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do { \
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cgen_rtx_error (current_cpu, "cannot alter target byte order mid-program");\
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;} while (0)
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#define GET_H_FRC(index) CPU (h_fr[((((16) * (GET_H_FRBIT ()))) + (index))])
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#define SET_H_FRC(index, x) \
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do { \
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CPU (h_fr[((((16) * (GET_H_FRBIT ()))) + ((index)))]) = (x);\
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;} while (0)
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#define GET_H_DRC(index) GET_H_DR (((((16) * (GET_H_FRBIT ()))) + (index)))
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#define SET_H_DRC(index, x) \
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do { \
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SET_H_DR (((((16) * (GET_H_FRBIT ()))) + ((index))), (x));\
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;} while (0)
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#define GET_H_XF(index) CPU (h_fr[((((16) * (NOTBI (GET_H_FRBIT ())))) + (index))])
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#define SET_H_XF(index, x) \
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do { \
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CPU (h_fr[((((16) * (NOTBI (GET_H_FRBIT ())))) + ((index)))]) = (x);\
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;} while (0)
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#define GET_H_XD(index) GET_H_DR (((((16) * (NOTBI (GET_H_FRBIT ())))) + (index)))
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#define SET_H_XD(index, x) \
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do { \
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SET_H_DR (((((16) * (NOTBI (GET_H_FRBIT ())))) + ((index))), (x));\
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;} while (0)
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#define GET_H_FVC(index) CPU (h_fr[((((16) * (GET_H_FRBIT ()))) + (index))])
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#define SET_H_FVC(index, x) \
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do { \
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CPU (h_fr[((((16) * (GET_H_FRBIT ()))) + ((index)))]) = (x);\
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;} while (0)
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#define GET_H_FPCCR() ORSI (ORSI (ORSI (CPU (h_fpscr), SLLSI (GET_H_PRBIT (), 19)), SLLSI (GET_H_SZBIT (), 20)), SLLSI (GET_H_FRBIT (), 21))
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#define SET_H_FPCCR(x) \
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do { \
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{\
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CPU (h_fpscr) = (x);\
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SET_H_PRBIT (ANDSI (SRLSI ((x), 19), 1));\
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SET_H_SZBIT (ANDSI (SRLSI ((x), 20), 1));\
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SET_H_FRBIT (ANDSI (SRLSI ((x), 21), 1));\
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}\
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;} while (0)
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#define GET_H_GBR() SUBWORDDISI (CPU (h_gr[((UINT) 16)]), 1)
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#define SET_H_GBR(x) \
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do { \
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CPU (h_gr[((UINT) 16)]) = EXTSIDI ((x));\
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;} while (0)
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#define GET_H_PR() SUBWORDDISI (CPU (h_gr[((UINT) 18)]), 1)
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#define SET_H_PR(x) \
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do { \
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CPU (h_gr[((UINT) 18)]) = EXTSIDI ((x));\
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;} while (0)
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#define GET_H_MACL() SUBWORDDISI (CPU (h_gr[((UINT) 17)]), 1)
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#define SET_H_MACL(x) \
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do { \
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CPU (h_gr[((UINT) 17)]) = ORDI (SLLDI (ZEXTSIDI (SUBWORDDISI (CPU (h_gr[((UINT) 17)]), 0)), 32), ZEXTSIDI ((x)));\
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;} while (0)
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#define GET_H_MACH() SUBWORDDISI (CPU (h_gr[((UINT) 17)]), 0)
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#define SET_H_MACH(x) \
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do { \
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CPU (h_gr[((UINT) 17)]) = ORDI (SLLDI (ZEXTSIDI ((x)), 32), ZEXTSIDI (SUBWORDDISI (CPU (h_gr[((UINT) 17)]), 1)));\
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;} while (0)
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#define GET_H_TBIT() ANDBI (CPU (h_gr[((UINT) 19)]), 1)
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#define SET_H_TBIT(x) \
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do { \
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CPU (h_gr[((UINT) 19)]) = ORDI (ANDDI (CPU (h_gr[((UINT) 19)]), INVDI (1)), ZEXTBIDI ((x)));\
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;} while (0)
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/* Cover fns for register access. */
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UDI sh64_h_pc_get (SIM_CPU *);
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void sh64_h_pc_set (SIM_CPU *, UDI);
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DI sh64_h_gr_get (SIM_CPU *, UINT);
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void sh64_h_gr_set (SIM_CPU *, UINT, DI);
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SI sh64_h_grc_get (SIM_CPU *, UINT);
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void sh64_h_grc_set (SIM_CPU *, UINT, SI);
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DI sh64_h_cr_get (SIM_CPU *, UINT);
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void sh64_h_cr_set (SIM_CPU *, UINT, DI);
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SI sh64_h_sr_get (SIM_CPU *);
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void sh64_h_sr_set (SIM_CPU *, SI);
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SI sh64_h_fpscr_get (SIM_CPU *);
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void sh64_h_fpscr_set (SIM_CPU *, SI);
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BI sh64_h_frbit_get (SIM_CPU *);
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void sh64_h_frbit_set (SIM_CPU *, BI);
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BI sh64_h_szbit_get (SIM_CPU *);
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void sh64_h_szbit_set (SIM_CPU *, BI);
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BI sh64_h_prbit_get (SIM_CPU *);
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void sh64_h_prbit_set (SIM_CPU *, BI);
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BI sh64_h_sbit_get (SIM_CPU *);
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void sh64_h_sbit_set (SIM_CPU *, BI);
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BI sh64_h_mbit_get (SIM_CPU *);
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void sh64_h_mbit_set (SIM_CPU *, BI);
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BI sh64_h_qbit_get (SIM_CPU *);
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void sh64_h_qbit_set (SIM_CPU *, BI);
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SF sh64_h_fr_get (SIM_CPU *, UINT);
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void sh64_h_fr_set (SIM_CPU *, UINT, SF);
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DF sh64_h_fp_get (SIM_CPU *, UINT);
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void sh64_h_fp_set (SIM_CPU *, UINT, DF);
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SF sh64_h_fv_get (SIM_CPU *, UINT);
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void sh64_h_fv_set (SIM_CPU *, UINT, SF);
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SF sh64_h_fmtx_get (SIM_CPU *, UINT);
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void sh64_h_fmtx_set (SIM_CPU *, UINT, SF);
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DF sh64_h_dr_get (SIM_CPU *, UINT);
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void sh64_h_dr_set (SIM_CPU *, UINT, DF);
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DI sh64_h_tr_get (SIM_CPU *, UINT);
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void sh64_h_tr_set (SIM_CPU *, UINT, DI);
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BI sh64_h_endian_get (SIM_CPU *);
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void sh64_h_endian_set (SIM_CPU *, BI);
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BI sh64_h_ism_get (SIM_CPU *);
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void sh64_h_ism_set (SIM_CPU *, BI);
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SF sh64_h_frc_get (SIM_CPU *, UINT);
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void sh64_h_frc_set (SIM_CPU *, UINT, SF);
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DF sh64_h_drc_get (SIM_CPU *, UINT);
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void sh64_h_drc_set (SIM_CPU *, UINT, DF);
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SF sh64_h_xf_get (SIM_CPU *, UINT);
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void sh64_h_xf_set (SIM_CPU *, UINT, SF);
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DF sh64_h_xd_get (SIM_CPU *, UINT);
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void sh64_h_xd_set (SIM_CPU *, UINT, DF);
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SF sh64_h_fvc_get (SIM_CPU *, UINT);
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void sh64_h_fvc_set (SIM_CPU *, UINT, SF);
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SI sh64_h_fpccr_get (SIM_CPU *);
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void sh64_h_fpccr_set (SIM_CPU *, SI);
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SI sh64_h_gbr_get (SIM_CPU *);
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void sh64_h_gbr_set (SIM_CPU *, SI);
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SI sh64_h_pr_get (SIM_CPU *);
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void sh64_h_pr_set (SIM_CPU *, SI);
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SI sh64_h_macl_get (SIM_CPU *);
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void sh64_h_macl_set (SIM_CPU *, SI);
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SI sh64_h_mach_get (SIM_CPU *);
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void sh64_h_mach_set (SIM_CPU *, SI);
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BI sh64_h_tbit_get (SIM_CPU *);
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void sh64_h_tbit_set (SIM_CPU *, BI);
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/* These must be hand-written. */
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extern CPUREG_FETCH_FN sh64_fetch_register;
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extern CPUREG_STORE_FN sh64_store_register;
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typedef struct {
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int empty;
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} MODEL_SH5_DATA;
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/* Collection of various things for the trace handler to use. */
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typedef struct trace_record {
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IADDR pc;
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/* FIXME:wip */
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} TRACE_RECORD;
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#endif /* CPU_SH64_H */
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