b4714c7c30
2014-11-06 Sandra Loosemore <sandra@codesourcery.com> include/opcode/ * nios2.h (nios2_find_opcode_hash): Add mach parameter to declaration. Fix obsolete comment. opcodes/ * nios2-dis.c (nios2_find_opcode_hash): Add mach parameter. (nios2_disassemble): Adjust call to nios2_find_opcode_hash. gas/ * config/tc-nios2.c (nios2_diagnose_overflow): Adjust call to nios2_find_opcode_hash.
794 lines
29 KiB
Plaintext
794 lines
29 KiB
Plaintext
2014-11-06 Sandra Loosemore <sandra@codesourcery.com>
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* nios2-dis.c (nios2_find_opcode_hash): Add mach parameter.
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(nios2_disassemble): Adjust call to nios2_find_opcode_hash.
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2014-11-03 Nick Clifton <nickc@redhat.com>
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* po/fi.po: Updated Finnish translation.
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2014-10-31 Andrew Pinski <apinski@cavium.com>
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Naveen H.S <Naveen.Hurugalawadi@caviumnetworks.com>
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* mips-dis.c (mips_arch_choices): Add octeon3.
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* mips-opc.c (IOCT): Include INSN_OCTEON3.
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(IOCT2): Likewise.
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(IOCT3): New define.
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(IVIRT): New define.
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(mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
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tlbinv, tlbinvf, tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp, tlti
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IVIRT instructions.
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Extend mtm0, mtm1, mtm2, mtp0, mtp1, mtp2 instructions to take another
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operand for IOCT3.
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2014-10-29 Nick Clifton <nickc@redhat.com>
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* po/de.po: Updated German translation.
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2014-10-23 Sandra Loosemore <sandra@codesourcery.com>
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* nios2-opc.c (nios2_builtin_regs): Add regtype field initializers.
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(nios2_builtin_opcodes): Rename to nios2_r1_opcodes. Use new
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MATCH_R1_<insn> and MASK_R1_<insn> macros in initializers. Add
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size and format initializers. Merge 'b' arguments into 'j'.
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(NIOS2_NUM_OPCODES): Adjust definition.
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(bfd_nios2_num_builtin_opcodes): Rename to nios2_num_r1_opcodes.
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(nios2_opcodes): Adjust.
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(bfd_nios2_num_opcodes): Rename to nios2_num_opcodes.
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* nios2-dis.c (INSNLEN): Update comment.
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(nios2_hash_init, nios2_hash): Delete.
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(OPCODE_HASH_SIZE): New.
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(nios2_r1_extract_opcode): New.
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(nios2_disassembler_state): New.
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(nios2_r1_disassembler_state): New.
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(nios2_init_opcode_hash): Add state parameter. Adjust to use it.
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(nios2_find_opcode_hash): Use state object.
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(bad_opcode): New.
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(nios2_print_insn_arg): Add op parameter. Use it to access
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format. Remove 'b' case.
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(nios2_disassemble): Remove special case for nop. Remove
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hard-coded instruction size.
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2014-10-21 Jan Beulich <jbeulich@suse.com>
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* ppc-opc.c (powerpc_opcodes): Enable msgclr and msgsnd on Power8.
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2014-10-17 Jose E. Marchesi <jose.marchesi@oracle.com>
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* sparc-opc.c (sparc-opcodes): Fix several misplaced hwcap
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entries.
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Annotate several instructions with the HWCAP2_VIS3B hwcap.
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2014-10-15 Tristan Gingold <gingold@adacore.com>
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* configure: Regenerate.
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2014-10-09 Jose E. Marchesi <jose.marchesi@oracle.com>
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* sparc-opc.c (sparc-opcodes): Remove instructions `chkpt',
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`commit', `random', `wr r,r,%cps', `wr r,i,%cps' and `rd %cps,r'.
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Annotate table with HWCAP2 bits.
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Add instructions xmontmul, xmontsqr, xmpmul.
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(sparc-opcodes): Add the `mwait', `wr r,r,%mwait', `wr
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r,i,%mwait' and `rd %mwait,r' instructions.
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Add rd/wr instructions for accessing the %mcdper ancillary state
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register.
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(sparc-opcodes): Add sparc5/vis4.0 instructions:
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subxc, subxccc, fpadd8, fpadds8, fpaddus8, fpaddus16, fpcmple8,
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fpcmpgt8, fpcmpule16, fpcmpugt16, fpcmpule32, fpcmpugt32, fpmax8,
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fpmax16, fpmax32, fpmaxu8, fpmaxu16, fpmaxu32, fpmin8, fpmin16,
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fpmin32, fpminu8, fpminu16, fpminu32, fpsub8, fpsubs8, fpsubus8,
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fpsubus16, and faligndatai.
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* sparc-dis.c (v9a_asr_reg_names): Add the %mwait (%asr28)
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ancillary state register to the table.
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(print_insn_sparc): Handle the %mcdper ancillary state register.
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(print_insn_sparc): Handle new operand type '}'.
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2014-09-22 H.J. Lu <hongjiu.lu@intel.com>
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* i386-dis.c (MOD_0F20): Removed.
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(MOD_0F21): Likewise.
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(MOD_0F22): Likewise.
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(MOD_0F23): Likewise.
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(dis386_twobyte): Replace MOD_0F20, MOD_0F21, MOD_0F22 and
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MOD_0F23 with "movZ".
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(mod_table): Remove MOD_0F20, MOD_0F21, MOD_0F22 and MOD_0F23.
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(OP_R): Check mod/rm byte and call OP_E_register.
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2014-09-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
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* nds32-asm.c (nds32_opcodes, operand_fields, keyword_im5_i,
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keyword_im5_m, keyword_accumulator, keyword_aridx, keyword_aridx2,
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keyword_aridxi): Add audio ISA extension.
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(keyword_gpr, keyword_usr, keyword_sr, keyword_cp, keyword_cpr,
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keyword_fsr, keyword_fdr, keyword_abdim, keyword_abm, keyword_dpref_st,
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keyword_cctl_lv, keyword_standby_st, keyword_msync_st): Adjust scrope
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for nds32-dis.c using.
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(build_opcode_syntax): Remove dead code.
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(parse_re, parse_a30b20, parse_rt21, parse_rte_start, parse_rte_end,
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parse_rte69_start, parse_rte69_end, parse_im5_ip, parse_im5_mr,
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parse_im6_ip, parse_im6_iq, parse_im6_mr, parse_im6_ms): Add audio ISA
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operand parser.
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* nds32-asm.h: Declare.
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* nds32-dis.c: Use array nds32_opcodes to disassemble instead of
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decoding by switch.
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2014-09-15 Andrew Bennett <andrew.bennett@imgtec.com>
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Matthew Fortune <matthew.fortune@imgtec.com>
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* mips-dis.c (mips_arch_choices): Add entries for mips32r6 and
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mips64r6.
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(parse_mips_dis_option): Allow MSA and virtualization support for
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mips64r6.
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(mips_print_arg_state): Add fields dest_regno and seen_dest.
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(mips_seen_register): New function.
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(print_insn_arg): Refactored code to use mips_seen_register
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function. Add support for OP_SAME_RS_RT, OP_CHECK_PREV and
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OP_NON_ZERO_REG. Changed OP_REPEAT_DEST_REG case to print out
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the register rather than aborting.
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(print_insn_args): Add length argument. Add code to correctly
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calculate the instruction address for pc relative instructions.
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(validate_insn_args): New static function.
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(print_insn_mips): Prevent jalx disassembling for r6. Use
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validate_insn_args.
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(print_insn_micromips): Use validate_insn_args.
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all the arguments are valid.
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* mips-formats.h (PREV_CHECK): New define.
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* mips-opc.c (decode_mips_operand): Add support for -a, -b, -d, -s,
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-t, -u, -v, -w, -x, -y, -A, -B, +I, +O, +R, +:, +\, +", +;
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(RD_pc): New define.
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(FS): New define.
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(I37): New define.
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(I69): New define.
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(mips_builtin_opcodes): Add MIPS R6 instructions. Exclude recoded
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MIPS R6 instructions from MIPS R2 instructions.
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2014-09-10 H.J. Lu <hongjiu.lu@intel.com>
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* i386-dis.c (dis386): Replace "P" with "%LP" for iret and sysret.
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(putop): Handle "%LP".
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2014-09-03 Jiong Wang <jiong.wang@arm.com>
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* aarch64-tbl.h (aarch64_opcode_table): Update encoding for mrs/msr.
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* aarch64-dis-2.c: Update auto-generated file.
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2014-09-03 Jiong Wang <jiong.wang@arm.com>
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* aarch64-tbl.h (QL_R4NIL): New qualifiers.
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(aarch64_feature_lse): New feature added.
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(LSE): New Added.
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(aarch64_opcode_table): New LSE instructions added. Improve
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descriptions for ldarb/ldarh/ldar.
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(aarch64_opcode_table): Describe PAIRREG.
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* aarch64-opc.h (aarch64_field_kind): Add FLD_lse_sz.
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* aarch64-opc.c (fields): Add entry for F_LSE_SZ.
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(aarch64_print_operand): Recognize PAIRREG.
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(operand_general_constraint_met_p): Check reg pair constraints for CASP
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instructions.
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* aarch64-dis.c (aarch64_ext_regno_pair): New extractor for paired reg.
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(do_special_decoding): Recognize F_LSE_SZ.
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* aarch64-asm.c (do_special_encoding): Recognize F_LSE_SZ.
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2014-08-26 Maciej W. Rozycki <macro@codesourcery.com>
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* micromips-opc.c (decode_micromips_operand): Rename `B' to `+J'.
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(micromips_opcodes): Use "+J" in place of "B" for "hypcall",
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"sdbbp", "syscall" and "wait".
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2014-08-21 Nathan Sidwell <nathan@codesourcery.com>
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Maciej W. Rozycki <macro@codesourcery.com>
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* arm-dis.c (print_arm_address): Negate the GPR-relative offset
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returned if the U bit is set.
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2014-08-21 Maciej W. Rozycki <macro@codesourcery.com>
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* micromips-opc.c (micromips_opcodes): Remove #ifdef-ed out
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48-bit "li" encoding.
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2014-08-19 Andreas Arnez <arnez@linux.vnet.ibm.com>
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* s390-dis.c (s390_insn_length, s390_insn_matches_opcode)
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(s390_print_insn_with_opcode, opcode_mask_more_specific): New
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static functions, code was moved from...
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(print_insn_s390): ...here.
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(s390_extract_operand): Adjust comment. Change type of first
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parameter from 'unsigned char *' to 'const bfd_byte *'.
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(union operand_value): New.
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(s390_extract_operand): Change return type to union operand_value.
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Also avoid integer overflow in sign-extension.
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(s390_print_insn_with_opcode): Adjust to changed return value from
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s390_extract_operand(). Change "%i" printf format to "%u" for
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unsigned values.
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(init_disasm): Simplify initialization of opc_index[]. This also
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fixes an access after the last element of s390_opcodes[].
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(print_insn_s390): Simplify the opcode search loop.
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Check architecture mask against all searched opcodes, not just the
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first matching one.
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(s390_print_insn_with_opcode): Drop function pointer dereferences
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without effect.
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(print_insn_s390): Likewise.
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(s390_insn_length): Simplify formula for return value.
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(s390_print_insn_with_opcode): Avoid special handling for the
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separator before the first operand. Use new local variable
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'flags' in place of 'operand->flags'.
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2014-08-14 Mike Frysinger <vapier@gentoo.org>
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* bfin-dis.c (struct private): Change int's to bfd_boolean's.
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(decode_LOGI2op_0, decode_COMPI2opD_0, decode_COMPI2opP_0,
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decode_dagMODik_0, decode_LDIMMhalf_0, decode_linkage_0):
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Change assignment of 1 to priv->comment to TRUE.
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(print_insn_bfin): Change legal to a bfd_boolean. Change
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assignment of 0/1 with priv comment and parallel and legal
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to FALSE/TRUE.
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2014-08-14 Mike Frysinger <vapier@gentoo.org>
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* bfin-dis.c (OUT): Define.
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(decode_CC2stat_0): Declare new op_names array.
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Replace multiple if statements with a single one.
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2014-08-14 Mike Frysinger <vapier@gentoo.org>
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* bfin-dis.c (struct private): Add iw0.
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(_print_insn_bfin): Assign iw0 to priv.iw0.
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(print_insn_bfin): Drop ifetch and use priv.iw0.
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2014-08-13 Mike Frysinger <vapier@gentoo.org>
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* bfin-dis.c (comment, parallel): Move from global scope ...
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(struct private): ... to this new struct.
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(decode_ProgCtrl_0, decode_CaCTRL_0, decode_PushPopReg_0,
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decode_PushPopMultiple_0, decode_ccMV_0, decode_CCflag_0,
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decode_CC2dreg_0, decode_CC2stat_0, decode_BRCC_0, decode_UJUMP_0,
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decode_LOGI2op_0, decode_COMPI2opD_0, decode_COMPI2opP_0,
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decode_dagMODik_0, decode_LoopSetup_0, decode_LDIMMhalf_0,
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decode_CALLa_0, decode_linkage_0, decode_pseudoDEBUG_0,
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decode_pseudoOChar_0, decode_pseudodbg_assert_0, _print_insn_bfin,
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print_insn_bfin): Declare private struct. Use priv's comment and
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parallel members.
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2014-08-13 Mike Frysinger <vapier@gentoo.org>
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* bfin-dis.c (ifetch): Do not align pc to 2 bytes.
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(_print_insn_bfin): Add check for unaligned pc.
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2014-08-13 Mike Frysinger <vapier@gentoo.org>
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* bfin-dis.c (ifetch): New function.
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(_print_insn_bfin, print_insn_bfin): Call new ifetch and return
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-1 when it errors.
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2014-07-29 Matthew Fortune <matthew.fortune@imgtec.com>
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* micromips-opc.c (COD): Rename throughout to...
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(CM): New define, update to use INSN_COPROC_MOVE.
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(LCD): Rename throughout to...
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(LC): New define, update to use INSN_LOAD_COPROC.
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* mips-opc.c: Likewise.
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2014-07-29 Matthew Fortune <matthew.fortune@imgtec.com>
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* micromips-opc.c (COD, LCD) New macros.
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(cfc1, ctc1): Remove FP_S attribute.
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(dmfc1, mfc1, mfhc1): Add LCD attribute.
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(dmtc1, mtc1, mthc1): Add COD attribute.
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* mips-opc.c (cfc1, cftc1, ctc, cttc1): Remove FP_S attribute.
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2014-07-22 Sergey Guriev <sergey.s.guriev@intel.com>
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Alexander Ivchenko <alexander.ivchenko@intel.com>
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Maxim Kuznetsov <maxim.kuznetsov@intel.com>
|
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Sergey Lega <sergey.s.lega@intel.com>
|
||
Anna Tikhonova <anna.tikhonova@intel.com>
|
||
Ilya Tocar <ilya.tocar@intel.com>
|
||
Andrey Turetskiy <andrey.turetskiy@intel.com>
|
||
Ilya Verbin <ilya.verbin@intel.com>
|
||
Kirill Yukhin <kirill.yukhin@intel.com>
|
||
Michael Zolotukhin <michael.v.zolotukhin@intel.com>
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||
|
||
* i386-dis-evex.h: Updated.
|
||
* i386-dis.c (PREFIX enum): Add PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
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PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0F3A16,
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PREFIX_EVEX_0F3A22, PREFIX_EVEX_0F3A50, PREFIX_EVEX_0F3A51,
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PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66,
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PREFIX_EVEX_0F3A67.
|
||
(VEX_LEN enum): Add VEX_LEN_0F92_P_2, VEX_LEN_0F93_P_2,
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VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_2_LEN_0.
|
||
(VEX_W enum): Add EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
|
||
EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2, EVEX_W_0F57_P_0,
|
||
EVEX_W_0F57_P_2, EVEX_W_0F78_P_2, EVEX_W_0F79_P_2, EVEX_W_0F7A_P_2,
|
||
EVEX_W_0F7B_P_2, EVEX_W_0F3838_P_1, EVEX_W_0F3839_P_1,
|
||
EVEX_W_0F3A16_P_2, EVEX_W_0F3A22_P_2, EVEX_W_0F3A50_P_2,
|
||
EVEX_W_0F3A51_P_2, EVEX_W_0F3A56_P_2, EVEX_W_0F3A57_P_2,
|
||
EVEX_W_0F3A66_P_2, EVEX_W_0F3A67_P_2.
|
||
(prefix_table): Add entries for new instructions.
|
||
(vex_len_table): Ditto.
|
||
(vex_w_table): Ditto.
|
||
(OP_E_memory): Update xmmq_mode handling.
|
||
* i386-gen.c (cpu_flag_init): Add CPU_AVX512DQ_FLAGS.
|
||
(cpu_flags): Add CpuAVX512DQ.
|
||
* i386-init.h: Regenerared.
|
||
* i386-opc.h (CpuAVX512DQ): New.
|
||
(i386_cpu_flags): Add cpuavx512dq.
|
||
* i386-opc.tbl: Add AVX512DQ instructions.
|
||
* i386-tbl.h: Regenerate.
|
||
|
||
2014-07-22 Sergey Guriev <sergey.s.guriev@intel.com>
|
||
Alexander Ivchenko <alexander.ivchenko@intel.com>
|
||
Maxim Kuznetsov <maxim.kuznetsov@intel.com>
|
||
Sergey Lega <sergey.s.lega@intel.com>
|
||
Anna Tikhonova <anna.tikhonova@intel.com>
|
||
Ilya Tocar <ilya.tocar@intel.com>
|
||
Andrey Turetskiy <andrey.turetskiy@intel.com>
|
||
Ilya Verbin <ilya.verbin@intel.com>
|
||
Kirill Yukhin <kirill.yukhin@intel.com>
|
||
Michael Zolotukhin <michael.v.zolotukhin@intel.com>
|
||
|
||
* i386-dis-evex.h: Add new instructions (prefixes bellow).
|
||
* i386-dis.c (fetch_data): Add EdqwS, Edb, Edw, MaskBDE.
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(enum): Add dqw_swap_mode, db_mode, dw_mode, mask_bd_mode, REG_EVEX_0F71.
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||
(PREFIX enum): Add PREFIX_VEX_0F4A, PREFIX_VEX_0F99, PREFIX_VEX_0F3A31,
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PREFIX_VEX_0F3A33, PREFIX_EVEX_0F60, PREFIX_EVEX_0F61, PREFIX_EVEX_0F63,
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||
PREFIX_EVEX_0F64, PREFIX_EVEX_0F65, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
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||
PREFIX_EVEX_0F69, PREFIX_EVEX_0F6B, PREFIX_EVEX_0F71_REG_2, PREFIX_EVEX_0F71_REG_4,
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||
PREFIX_EVEX_0F71_REG_6, PREFIX_EVEX_0F73_REG_3, PREFIX_EVEX_0F73_REG_7,
|
||
PREFIX_EVEX_0F74, PREFIX_EVEX_0F75, PREFIX_EVEX_0FC4, PREFIX_EVEX_0FC5,
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||
PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5, PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9,
|
||
PREFIX_EVEX_0FDA, PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
|
||
PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3, PREFIX_EVEX_0FE4,
|
||
PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8, PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA,
|
||
PREFIX_EVEX_0FEC, PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
|
||
PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8, PREFIX_EVEX_0FF9,
|
||
PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD, PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804,
|
||
PREFIX_EVEX_0F380B, PREFIX_EVEX_0F3810, PREFIX_EVEX_0F381C, PREFIX_EVEX_0F381D,
|
||
PREFIX_EVEX_0F3820, PREFIX_EVEX_0F3826, PREFIX_EVEX_0F382B, PREFIX_EVEX_0F3830,
|
||
PREFIX_EVEX_0F3838, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E, PREFIX_EVEX_0F3866,
|
||
PREFIX_EVEX_0F3875, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879, PREFIX_EVEX_0F387A,
|
||
PREFIX_EVEX_0F387B, PREFIX_EVEX_0F387D, PREFIX_EVEX_0F388D, PREFIX_EVEX_0F3A0F,
|
||
PREFIX_EVEX_0F3A14, PREFIX_EVEX_0F3A15, PREFIX_EVEX_0F3A20, PREFIX_EVEX_0F3A3E,
|
||
PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A42.
|
||
(VEX_LEN enum): Add VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_2, VEX_LEN_0F44_P_2,
|
||
VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_2, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
|
||
VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_2,
|
||
VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_2, VEX_LEN_0F99_P_0,
|
||
VEX_LEN_0F99_P_2, VEX_LEN_0F3A31_P_2, VEX_LEN_0F3A33_P_2, VEX_W_0F41_P_2_LEN_1,
|
||
VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_2_LEN_1,
|
||
VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
|
||
VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1, VEX_W_0F90_P_2_LEN_0,
|
||
VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_3_LEN_0, VEX_W_0F93_P_3_LEN_0,
|
||
VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0, VEX_W_0F99_P_2_LEN_0,
|
||
VEX_W_0F3A31_P_2_LEN_0, VEX_W_0F3A33_P_2_LEN_0.
|
||
(VEX_W enum): Add EVEX_W_0F6B_P_2, EVEX_W_0F6F_P_3, EVEX_W_0F7F_P_3,
|
||
EVEX_W_0F3810_P_1, EVEX_W_0F3810_P_2, EVEX_W_0F3811_P_2, EVEX_W_0F3812_P_2,
|
||
EVEX_W_0F3820_P_1, EVEX_W_0F3826_P_1, EVEX_W_0F3826_P_2, EVEX_W_0F3828_P_1,
|
||
EVEX_W_0F3829_P_1, EVEX_W_0F382B_P_2, EVEX_W_0F3830_P_1, EVEX_W_0F3866_P_2,
|
||
EVEX_W_0F3875_P_2, EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2, EVEX_W_0F387A_P_2,
|
||
EVEX_W_0F387B_P_2, EVEX_W_0F387D_P_2, EVEX_W_0F388D_P_2, EVEX_W_0F3A3E_P_2,
|
||
EVEX_W_0F3A3F_P_2, EVEX_W_0F3A42_P_2.
|
||
(prefix_table): Add entries for new instructions.
|
||
(vex_table) : Ditto.
|
||
(vex_len_table): Ditto.
|
||
(vex_w_table): Ditto.
|
||
(intel_operand_size): Add db_mode, dw_mode, dqw_swap_mode,
|
||
mask_bd_mode handling.
|
||
(OP_E_register): Add dqw_swap_mode, dw_mode, db_mode, mask_bd_mode
|
||
handling.
|
||
(OP_E_memory): Add dqw_mode, dw_mode, dqw_swap_mode, dqb_mode, db_mode
|
||
handling.
|
||
(OP_G): Add db_mode, dw_mode, dqw_swap_mode, mask_bd_mode handling.
|
||
(OP_EX): Add dqw_swap_mode handling.
|
||
(OP_VEX): Add mask_bd_mode handling.
|
||
(OP_Mask): Add mask_bd_mode handling.
|
||
* i386-gen.c (cpu_flag_init): Add CPU_AVX512BW_FLAGS.
|
||
(cpu_flags): Add CpuAVX512BW.
|
||
* i386-init.h: Regenerated.
|
||
* i386-opc.h (CpuAVX512BW): New.
|
||
(i386_cpu_flags): Add cpuavx512bw.
|
||
* i386-opc.tbl: Add AVX512BW instructions.
|
||
* i386-tbl.h: Regenerate.
|
||
|
||
2014-07-22 Sergey Guriev <sergey.s.guriev@intel.com>
|
||
Alexander Ivchenko <alexander.ivchenko@intel.com>
|
||
Maxim Kuznetsov <maxim.kuznetsov@intel.com>
|
||
Sergey Lega <sergey.s.lega@intel.com>
|
||
Anna Tikhonova <anna.tikhonova@intel.com>
|
||
Ilya Tocar <ilya.tocar@intel.com>
|
||
Andrey Turetskiy <andrey.turetskiy@intel.com>
|
||
Ilya Verbin <ilya.verbin@intel.com>
|
||
Kirill Yukhin <kirill.yukhin@intel.com>
|
||
Michael Zolotukhin <michael.v.zolotukhin@intel.com>
|
||
|
||
* i386-opc.tbl: Add AVX512VL and AVX512CD instructions.
|
||
* i386-tbl.h: Regenerate.
|
||
|
||
2014-07-22 Sergey Guriev <sergey.s.guriev@intel.com>
|
||
Alexander Ivchenko <alexander.ivchenko@intel.com>
|
||
Maxim Kuznetsov <maxim.kuznetsov@intel.com>
|
||
Sergey Lega <sergey.s.lega@intel.com>
|
||
Anna Tikhonova <anna.tikhonova@intel.com>
|
||
Ilya Tocar <ilya.tocar@intel.com>
|
||
Andrey Turetskiy <andrey.turetskiy@intel.com>
|
||
Ilya Verbin <ilya.verbin@intel.com>
|
||
Kirill Yukhin <kirill.yukhin@intel.com>
|
||
Michael Zolotukhin <michael.v.zolotukhin@intel.com>
|
||
|
||
* i386-dis.c (intel_operand_size): Support 128/256 length in
|
||
vex_vsib_q_w_dq_mode.
|
||
(OP_E_memory): Add ymmq_mode handling, handle new broadcast.
|
||
* i386-gen.c (cpu_flag_init): Add CPU_AVX512VL_FLAGS.
|
||
(cpu_flags): Add CpuAVX512VL.
|
||
* i386-init.h: Regenerated.
|
||
* i386-opc.h (CpuAVX512VL): New.
|
||
(i386_cpu_flags): Add cpuavx512vl.
|
||
(BROADCAST_1TO4, BROADCAST_1TO2): Define.
|
||
* i386-opc.tbl: Add AVX512VL instructions.
|
||
* i386-tbl.h: Regenerate.
|
||
|
||
2014-07-20 Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
|
||
|
||
* or1k-desc.c, * or1k-desc.h, * or1k-opc.c, * or1k-opc.h,
|
||
* or1k-opinst.c: Regenerate.
|
||
|
||
2014-07-08 Ilya Tocar <ilya.tocar@intel.com>
|
||
|
||
* i386-dis-evex.h (EVEX_W_0F10_P_1_M_1): Fix vmovss.
|
||
(EVEX_W_0F10_P_3_M_1): Fix vmovsd.
|
||
|
||
2014-07-04 Alan Modra <amodra@gmail.com>
|
||
|
||
* configure.ac: Rename from configure.in.
|
||
* Makefile.in: Regenerate.
|
||
* config.in: Regenerate.
|
||
|
||
2014-07-04 Alan Modra <amodra@gmail.com>
|
||
|
||
* configure.in: Include bfd/version.m4.
|
||
(AC_INIT, AM_INIT_AUTOMAKE): Use modern form.
|
||
(BFD_VERSION): Delete.
|
||
* Makefile.am (CONFIG_STATUS_DEPENDENCIES): Remove bfd/configure.in.
|
||
* configure: Regenerate.
|
||
* Makefile.in: Regenerate.
|
||
|
||
2014-07-01 Barney Stratford <barney_stratford@fastmail.fm>
|
||
Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
|
||
Pitchumani Sivanupandi <pitchumani.s@atmel.com>
|
||
Soundararajan <Sounderarajan.D@atmel.com>
|
||
|
||
* avr-dis.c (avr_operand): Handle constraint j for 16 bit lds/sts.
|
||
(print_insn_avr): Do not select opcode if insn ISA is avrtiny and
|
||
machine is not avrtiny.
|
||
|
||
2014-06-26 Philippe De Muyter <phdm@macqel.be>
|
||
|
||
* or1k-desc.h (spr_field_masks): Add U suffix to the end of long
|
||
constants.
|
||
|
||
2014-06-12 Alan Modra <amodra@gmail.com>
|
||
|
||
* or1k-asm.c, * or1k-desc.c, * or1k-desc.h, * or1k-dis.c,
|
||
* or1k-ibld.c, * or1k-opc.c, * or1k-opc.h, * or1k-opinst.c: Regenerate.
|
||
|
||
2014-06-10 H.J. Lu <hongjiu.lu@intel.com>
|
||
|
||
* i386-dis.c (fwait_prefix): New.
|
||
(ckprefix): Set fwait_prefix.
|
||
(print_insn): Properly print prefixes before fwait.
|
||
|
||
2014-06-07 Alan Modra <amodra@gmail.com>
|
||
|
||
* ppc-opc.c (UISIGNOPT): Define and use with cmpli.
|
||
|
||
2014-06-05 Joel Brobecker <brobecker@adacore.com>
|
||
|
||
* Makefile.am (CONFIG_STATUS_DEPENDENCIES): Add dependency on
|
||
bfd's development.sh.
|
||
* Makefile.in, configure: Regenerate.
|
||
|
||
2014-06-03 Nick Clifton <nickc@redhat.com>
|
||
|
||
* msp430-dis.c (msp430_doubleoperand): Use extension_word to
|
||
decide when extended addressing is being used.
|
||
|
||
2014-06-02 Eric Botcazou <ebotcazou@adacore.com>
|
||
|
||
* sparc-opc.c (cas): Disable for LEON.
|
||
(casl): Likewise.
|
||
|
||
2014-05-20 Alan Modra <amodra@gmail.com>
|
||
|
||
* m68k-dis.c: Don't include setjmp.h.
|
||
|
||
2014-05-09 H.J. Lu <hongjiu.lu@intel.com>
|
||
|
||
* i386-dis.c (ADDR16_PREFIX): Removed.
|
||
(ADDR32_PREFIX): Likewise.
|
||
(DATA16_PREFIX): Likewise.
|
||
(DATA32_PREFIX): Likewise.
|
||
(prefix_name): Updated.
|
||
(print_insn): Simplify data and address size prefixes processing.
|
||
|
||
2014-05-08 Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
|
||
|
||
* or1k-desc.c: Regenerated.
|
||
* or1k-desc.h: Likewise.
|
||
* or1k-opc.c: Likewise.
|
||
* or1k-opc.h: Likewise.
|
||
* or1k-opinst.c: Likewise.
|
||
|
||
2014-05-07 Andrew Bennett <andrew.bennett@imgtec.com>
|
||
|
||
* mips-opc.c (mips_builtin_opcodes): Add MIPS32r5 eretnc instruction.
|
||
(I34): New define.
|
||
(I36): New define.
|
||
(I66): New define.
|
||
(I68): New define.
|
||
* mips-dis.c (mips_arch_choices): Add mips32r3, mips32r5, mips64r3 and
|
||
mips64r5.
|
||
(parse_mips_dis_option): Update MSA and virtualization support to
|
||
allow mips64r3 and mips64r5.
|
||
|
||
2014-05-07 Andrew Bennett <andrew.bennett@imgtec.com>
|
||
|
||
* mips-opc.c (G3): Remove I4.
|
||
|
||
2014-05-05 H.J. Lu <hongjiu.lu@intel.com>
|
||
|
||
PR binutils/16893
|
||
* i386-dis.c (twobyte_has_mandatory_prefix): New variable.
|
||
(end_codep): Likewise.
|
||
(mandatory_prefix): Likewise.
|
||
(active_seg_prefix): Likewise.
|
||
(ckprefix): Set active_seg_prefix to the active segment register
|
||
prefix.
|
||
(seg_prefix): Removed.
|
||
(get_valid_dis386): Use the last of PREFIX_REPNZ and PREFIX_REPZ
|
||
for prefix index. Ignore the index if it is invalid and the
|
||
mandatory prefix isn't required.
|
||
(print_insn): Set mandatory_prefix if the PREFIX_XXX prefix is
|
||
mandatory. Don't set PREFIX_REPZ/PREFIX_REPNZ/PREFIX_LOCK bits
|
||
in used_prefixes here. Don't print unused prefixes. Check
|
||
active_seg_prefix for the active segment register prefix.
|
||
Restore the DFLAG bit in sizeflag if the data size prefix is
|
||
unused. Check the unused mandatory PREFIX_XXX prefixes
|
||
(append_seg): Only print the segment register which gets used.
|
||
(OP_E_memory): Check active_seg_prefix for the segment register
|
||
prefix.
|
||
(OP_OFF): Likewise.
|
||
(OP_OFF64): Likewise.
|
||
(OP_DSreg): Set active_seg_prefix to PREFIX_DS if it is unset.
|
||
|
||
2014-05-02 H.J. Lu <hongjiu.lu@intel.com>
|
||
|
||
PR binutils/16886
|
||
* config.in: Regenerated.
|
||
* configure: Likewise.
|
||
* configure.in: Check if sigsetjmp is available.
|
||
* h8500-dis.c (private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
|
||
(fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
|
||
(print_insn_h8500): Replace setjmp with OPCODES_SIGSETJMP.
|
||
* i386-dis.c (dis_private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
|
||
(fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
|
||
(print_insn): Replace setjmp with OPCODES_SIGSETJMP.
|
||
* ns32k-dis.c (private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
|
||
(fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
|
||
(print_insn_ns32k): Replace setjmp with OPCODES_SIGSETJMP.
|
||
* sysdep.h (OPCODES_SIGJMP_BUF): New macro.
|
||
(OPCODES_SIGSETJMP): Likewise.
|
||
(OPCODES_SIGLONGJMP): Likewise.
|
||
* vax-dis.c (private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
|
||
(fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
|
||
(print_insn_vax): Replace setjmp with OPCODES_SIGSETJMP.
|
||
* xtensa-dis.c (dis_private): Replace jmp_buf with
|
||
OPCODES_SIGJMP_BUF.
|
||
(fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
|
||
(print_insn_xtensa): Replace setjmp with OPCODES_SIGSETJMP.
|
||
* z8k-dis.c(instr_data_s): Replace jmp_buf with OPCODES_SIGJMP_BUF.
|
||
(fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
|
||
(print_insn_z8k): Replace setjmp with OPCODES_SIGSETJMP.
|
||
|
||
2014-05-01 H.J. Lu <hongjiu.lu@intel.com>
|
||
|
||
PR binutils/16891
|
||
* i386-dis.c (print_insn): Handle prefixes before fwait.
|
||
|
||
2014-04-26 Alan Modra <amodra@gmail.com>
|
||
|
||
* po/POTFILES.in: Regenerate.
|
||
|
||
2014-04-23 Andrew Bennett <andrew.bennett@imgtec.com>
|
||
|
||
* mips-dis.c (mips_arch_choices): Update mips32r2 and mips64r2
|
||
to allow the MIPS XPA ASE.
|
||
(parse_mips_dis_option): Process the -Mxpa option.
|
||
* mips-opc.c (XPA): New define.
|
||
(mips_builtin_opcodes): Add MIPS XPA instructions and move the
|
||
locations of the ctc0 and cfc0 instructions.
|
||
|
||
2014-04-22 Christian Svensson <blue@cmd.nu>
|
||
|
||
* Makefile.am: Remove openrisc and or32 support. Add support for or1k.
|
||
* configure.in: Likewise.
|
||
* disassemble.c: Likewise.
|
||
* or1k-asm.c: New file.
|
||
* or1k-desc.c: New file.
|
||
* or1k-desc.h: New file.
|
||
* or1k-dis.c: New file.
|
||
* or1k-ibld.c: New file.
|
||
* or1k-opc.c: New file.
|
||
* or1k-opc.h: New file.
|
||
* or1k-opinst.c: New file.
|
||
* Makefile.in: Regenerate.
|
||
* configure: Regenerate.
|
||
* openrisc-asm.c: Delete.
|
||
* openrisc-desc.c: Delete.
|
||
* openrisc-desc.h: Delete.
|
||
* openrisc-dis.c: Delete.
|
||
* openrisc-ibld.c: Delete.
|
||
* openrisc-opc.c: Delete.
|
||
* openrisc-opc.h: Delete.
|
||
* or32-dis.c: Delete.
|
||
* or32-opc.c: Delete.
|
||
|
||
2014-04-04 Ilya Tocar <ilya.tocar@intel.com>
|
||
|
||
* i386-dis.c (rm_table): Add encls, enclu.
|
||
* i386-gen.c (cpu_flag_init): Add CPU_SE1_FLAGS,
|
||
(cpu_flags): Add CpuSE1.
|
||
* i386-opc.h (enum): Add CpuSE1.
|
||
(i386_cpu_flags): Add cpuse1.
|
||
* i386-opc.tbl: Add encls, enclu.
|
||
* i386-init.h: Regenerated.
|
||
* i386-tbl.h: Likewise.
|
||
|
||
2014-04-02 Anthony Green <green@moxielogic.com>
|
||
|
||
* moxie-opc.c (moxie_form1_opc_info): Add sign-extension
|
||
instructions, sex.b and sex.s.
|
||
|
||
2014-03-26 Jiong Wang <jiong.wang@arm.com>
|
||
|
||
* aarch64-dis.c (aarch64_ext_ldst_elemlist): Check H/S undefined
|
||
instructions.
|
||
|
||
2014-03-20 Ilya Tocar <ilya.tocar@intel.com>
|
||
|
||
* i386-opc.tbl: Change memory size for vgatherpf0qps, vgatherpf1qps,
|
||
vscatterpf0qps, vscatterpf1qps, vgatherqps, vpgatherqd, vpscatterqd,
|
||
vscatterqps.
|
||
* i386-tbl.h: Regenerate.
|
||
|
||
2014-03-19 Jose E. Marchesi <jose.marchesi@oracle.com>
|
||
|
||
* sparc-dis.c (v9_hpriv_reg_names): Names for %hstick_offset and
|
||
%hstick_enable added.
|
||
|
||
2014-03-19 Nick Clifton <nickc@redhat.com>
|
||
|
||
* rx-decode.opc (bwl): Allow for bogus instructions with a size
|
||
field of 3.
|
||
(sbwl, ubwl, SCALE): Likewise.
|
||
* rx-decode.c: Regenerate.
|
||
|
||
2014-03-12 Alan Modra <amodra@gmail.com>
|
||
|
||
* Makefile.in: Regenerate.
|
||
|
||
2014-03-05 Alan Modra <amodra@gmail.com>
|
||
|
||
Update copyright years.
|
||
|
||
2014-03-04 Heiher <r@hev.cc>
|
||
|
||
* mips-dis.c (mips_arch_choices): Usee ISA_MIPS64R2 for Loongson-3A.
|
||
|
||
2014-03-04 Richard Sandiford <rdsandiford@googlemail.com>
|
||
|
||
* mips-opc.c (mips_builtin_opcodes): Move the udi* instructions
|
||
so that they come after the Loongson extensions.
|
||
|
||
2014-03-03 Alan Modra <amodra@gmail.com>
|
||
|
||
* i386-gen.c (process_copyright): Emit copyright notice on one line.
|
||
|
||
2014-02-28 Alan Modra <amodra@gmail.com>
|
||
|
||
* msp430-decode.c: Regenerate.
|
||
|
||
2014-02-27 Jiong Wang <jiong.wang@arm.com>
|
||
|
||
* aarch64-tbl.h (aarch64_opcode_table): Replace IMM0 with
|
||
FPIMM0 for fcmeq, fcmgt, fcmge, fcmlt and fcmle.
|
||
|
||
2014-02-27 Yufeng Zhang <yufeng.zhang@arm.com>
|
||
|
||
* aarch64-opc.c (print_register_offset_address): Call
|
||
get_int_reg_name to prepare the register name.
|
||
|
||
2014-02-25 Ilya Tocar <ilya.tocar@intel.com>
|
||
|
||
* i386-opc.tbl: Remove wrong variant of vcvtps2ph
|
||
* i386-tbl.h: Regenerate.
|
||
|
||
2014-02-20 Ilya Tocar <ilya.tocar@intel.com>
|
||
|
||
* i386-gen.c (cpu_flag_init): Add CPU_PREFETCHWT1_FLAGS/
|
||
(cpu_flags): Add CpuPREFETCHWT1.
|
||
* i386-init.h: Regenerate.
|
||
* i386-opc.h (CpuPREFETCHWT1): New.
|
||
(i386_cpu_flags): Add cpuprefetchwt1.
|
||
* i386-opc.tbl: Cahnge CPU of prefetchwt1 from CpuAVX512PF to CpuPREFETCHWT1.
|
||
* i386-tbl.h: Regenerate.
|
||
|
||
2014-02-20 Ilya Tocar <ilya.tocar@intel.com>
|
||
|
||
* i386-opc.tbl: Change CPU of vptestnmq, vptestnmd from CpuAVX512CD,
|
||
to CpuAVX512F.
|
||
* i386-tbl.h: Regenerate.
|
||
|
||
2014-02-19 H.J. Lu <hongjiu.lu@intel.com>
|
||
|
||
* i386-gen.c (output_cpu_flags): Don't output trailing space.
|
||
(output_opcode_modifier): Likewise.
|
||
(output_operand_type): Likewise.
|
||
* i386-init.h: Regenerated.
|
||
* i386-tbl.h: Likewise.
|
||
|
||
2014-02-12 Ilya Tocar <ilya.tocar@intel.com>
|
||
|
||
* i386-dis.c (MOD enum): Add MOD_0FC7_REG_3, MOD_0FC7_REG_4,
|
||
MOD_0FC7_REG_5.
|
||
(PREFIX enum): Add PREFIX_0FAE_REG_7.
|
||
(reg_table): Add MOD_0FC7_REG_3, MOD_0FC7_REG_4 MOD_0FC7_REG_5.
|
||
(prefix_table): Add clflusopt.
|
||
(mod_table): Add xrstors, xsavec, xsaves.
|
||
* i386-gen.c (cpu_flag_init): Add CPU_CLFLUSHOPT_FLAGS,
|
||
CPU_XSAVES_FLAGS, CPU_XSAVEC_FLAGS.
|
||
(cpu_flags): Add CpuClflushOpt, CpuXSAVES, CpuXSAVEC.
|
||
* i386-init.h: Regenerate.
|
||
* i386-opc.tbl: Add clflushopt, xrstors, xrstors64, xsaves,
|
||
xsaves64, xsavec, xsavec64.
|
||
* i386-tbl.h: Regenerate.
|
||
|
||
2014-02-10 Alan Modra <amodra@gmail.com>
|
||
|
||
* po/POTFILES.in: Regenerate.
|
||
* po/opcodes.pot: Regenerate.
|
||
|
||
2014-01-30 Michael Zolotukhin <michael.v.zolotukhin@gmail.com>
|
||
Jan Beulich <jbeulich@suse.com>
|
||
|
||
PR binutils/16490
|
||
* i386-dis.c (OP_E_memory): Fix shift computation for
|
||
vex_vsib_q_w_dq_mode.
|
||
|
||
2014-01-09 Bradley Nelson <bradnelson@google.com>
|
||
Roland McGrath <mcgrathr@google.com>
|
||
|
||
* i386-dis.c (print_insn): Do not touch all_prefixes[-1] when
|
||
last_rex_prefix is -1.
|
||
|
||
2014-01-08 H.J. Lu <hongjiu.lu@intel.com>
|
||
|
||
* i386-gen.c (process_copyright): Update copyright year to 2014.
|
||
|
||
2014-01-03 Maciej W. Rozycki <macro@codesourcery.com>
|
||
|
||
* nds32-asm.c (parse_operand): Fix out-of-range integer constant.
|
||
|
||
For older changes see ChangeLog-2013
|
||
|
||
Copyright (C) 2014 Free Software Foundation, Inc.
|
||
|
||
Copying and distribution of this file, with or without modification,
|
||
are permitted in any medium without royalty provided the copyright
|
||
notice and this notice are preserved.
|
||
|
||
Local Variables:
|
||
mode: change-log
|
||
left-margin: 8
|
||
fill-column: 74
|
||
version-control: never
|
||
End:
|